Scribd
Upload
120 views6 pages

32 Bit Multiplier

This document contains VHDL code for a 32-bit multiplier. It includes the entity and architecture for the multiplier, as well as a component for the basic multiplication cell (mult). It also contains a testbench that applies random 16-bit inputs to the multiplier and checks that the output matches the expected product.

Uploaded by

Protyay Ghosh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
120 views6 pages

32 Bit Multiplier

This document contains VHDL code for a 32-bit multiplier. It includes the entity and architecture for the multiplier, as well as a component for the basic multiplication cell (mult). It also contains a testbench that applies random 16-bit inputs to the multiplier and checks that the output matches the expected product.

Uploaded by

Protyay Ghosh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 6

32 bit Multiplier Codes

Multiplier behavioral
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:36:52 05/22/2021
-- Design Name:
-- Module Name: multiplier16x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity multiplier is
generic (N: integer; M: integer);
port ( a : in std_logic_vector(N-1 downto 0);
b : in std_logic_vector(M-1 downto 0);
prod : out std_logic_vector(M+N-1 downto 0) );
end entity multiplier;

architecture behavioral of multiplier is

component mult is
port (
a : in std_logic;
b : in std_logic;
pin : in std_logic;
cin : in std_logic;
pout : out std_logic;
cout : out std_logic );
end component;
type mem_word is array (0 to M-1) of std_logic_vector(N-1 downto 0);
signal cin : mem_word;
signal cout : mem_word;
signal pin : mem_word;
signal pout : mem_word;

begin
m_loop: for i in 0 to M-1 generate
n_loop: for j in 0 to N-1 generate
mult_inst : mult
port map (
a => a(j),
b => b(i),
pin => pin(i)(j),
cin => cin(i)(j),
pout => pout(i)(j),
cout => cout(i)(j) );
end generate;
end generate;
cin_init: for j in 0 to N-1 generate
cin(0)(j) <= '0';
end generate;

cin_mloop: for i in 1 to M-1 generate


cin_nloop: for j in 0 to N-2 generate
cin(i)(j) <= pout(i-1)(j+1);
end generate;
cin(i)(N-1) <= cout(i-1)(N-1);
end generate;
pin_mloop: for i in 0 to M-1 generate
pin(i)(0) <= '0';
pin_nloop: for j in 1 to N-1 generate
pin(i)(j) <= cout(i)(j-1);
end generate;
end generate;
prod_loop: for j in 0 to M-1 generate
prod(j) <= pout(j)(0);
end generate;

prod(M+N-2 downto M) <= pout(M-1)(N-1 downto 1);


prod(M+N-1) <= cout(M-1)(N-1);

end behavioral;
Mult instances

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:48:19 05/21/2021
-- Design Name:
-- Module Name: mult - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity mult is
port ( a : in std_logic;
b : in std_logic;
pin : in std_logic;
cin : in std_logic;
pout : out std_logic;
cout : out std_logic );
end mult;

architecture mult of mult is


begin
pout <= (a and b) xor cin xor pin;
cout <= (a and b and cin) or (a and b and pin) or (cin and pin);
end mult;
Simulation Codes (test)

Input 16 bits (Random Inputs)

A -0101010101010101
B -1010101010101010

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:26:57 05/23/2021
-- Design Name:
-- Module Name: E:/Users/Multiplier32_bit/test16x16.vhd
-- Project Name: Multiplier32_bit
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: multiplier
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity test16x16 is
end test16x16;

architecture behavioral of test16x16 is


component multiplier
generic (M: integer := 16; N: integer := 16);
port (
a : in std_logic_vector(M-1 downto 0);
b : in std_logic_vector(N-1 downto 0);
prod : out std_logic_vector(M+N-1 downto 0) );
end component;

-- signals
signal a : std_logic_vector(15 downto 0) :="0101010101010101";
signal b : std_logic_vector(15 downto 0) :="1010101010101010";
signal answer : std_logic_vector(31 downto 0);
signal correct : std_logic;

begin

dut: multiplier
generic map (
M => 16,
N => 16 )
port map (
a => a,
b => b,
prod => answer );

-- Stimulus process
stim_proc: process
begin
wait for 1 ns;
a <= a + 1;
if a = "0" then
b <= b + 1;
end if;
end process;

-- Check results
correct <= '1' when to_integer(unsigned(a))*to_integer(unsigned(b)) =
to_integer(unsigned(answer)) else '0';

end behavioral;
Output :

We got a 32 bit result

You might also like