Appendix A GATE-LEVEL DETAILS

Chapters 2 and 3 briefly introduced the built-in primitives. This appendix will
briefly describe each of the built-in primitives and the options when instantiating
them. The delay and strength options for primitive instances will be explained.

PRIMITIVE DESCRIPTIONS

Logic Gates

AND

Figure A-1 AND Gate

282 Verilog Quickstart

The and primitive can have two or more inputs, and has one output. When all of the
inputs are “1” then the output is “1”.

Table A-1 Logic Table for and Primitive

0 1 x z
0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x

NAND

Figure A-2 NAND Gate

The nand primitive can have two or more inputs, and has one output. When all of
the inputs are “1” then the output is “0”.

Table A-2 Logic Table for nand Primitive

0 1 x z
0 1 1 1 1
1 1 0 x x
x l x x x
z l x x x
Gate-Level Details 283

OR

Figure A-3 OR Gate

The or primitive can have two or more inputs, and has one output. When any of the
inputs is “1” then the output is “1”.

Table A-3 Logic Table for or Primitive

0 1 x z
0 0 1 x x
1 1 1 1 1
x x l x x
z x l x x

NOR

Figure A-4 NOR Gate

The nor primitive can have two or more inputs, and has one output. When any of
the inputs is “1” then the output is “0”.

Table A-4 Logic Table for nor Primitive

0 1 x z
0 1 0 x x
1 0 0 0 0
x x 0 x x
z x 0 x x
284 Verilog Quickstart

XOR

Figure A-5 XOR Gate

The xor primitive can have two or more inputs, and has one output. When an odd
number of inputs is “1” then the output is “1”, unless any input is “x”. When any of
the inputs is “x” then the output is “x”.

Table A-5 Logic Table for xor Primitive

0 1 x z
0 0 1 x x
1 1 0 x x
x x x x x
z x x x x

XNOR

Figure A-6 XNOR Gate

The xnor primitive can have two or more inputs, and has one output. When an odd
number of inputs is “1” then the output is “0”, unless any input is “x”. When any of
the inputs is “x” then the output is “x”.

Table A-6 Logic Table for xnor Primitive

0 1 x z
0 1 0 x x
1 0 1 x x
x x x x x
z x x x x
Gate-Level Details 285

Buffers

BUF

Figure A-7 BUF Gate

The buf primitive has one input and can have one or more outputs. The output(s)
pass the same value as the input, except an input of “z” produces an output of “x”.

Table A-7 Logic Table for buf Primitive

Input Output
0 0
1 1
x x
z x

NOT

Figure A-8 NOT Gate

The not primitive has one input and can have one or more outputs. The output(s)
pass the opposite value as the input, except an input of “x” or “z” produces an
output of “x”.

Table A-8 Logic Table for not Primitive

Input Output
0 1
1 0
x x
z x
286 Verilog Quickstart

BUFIF0

Figure A-9 BUFIF0 Gate

The bufif0 primitive has two inputs, (data and control) and one output. When the
control input is “0” the output passes the same value as the data input, except that
an input of “z’ produces an output of “x”. When the control input is “1” the output
is “z”. The port order of the primitive is output, input, control.

The remaining logic tables in the section show both strength and value. Verilog
uses a notation of three characters, two for the strength, and one for the value. Table
A-20 lists the two character codes used for the strength and the value is 0, 1, x, or z.

Table A-9 Logic Table for bufif0 Primitive

Data 0 1 x z
0 St0 HiZ StL StL
1 Stl HiZ StH StH
x StX HiZ StX StX
z StX HiZ StX StX

BUFlF1

Figure A-10 BUFIF1 Gate

The bufif1 primitive has two inputs, (data and control) and one output. When the
control input is “1” the output passes the same value as the data input, except that
an input of “z” produces an output of “x”. When the control input is “0” the output
is “z”. The port order of the primitive is output, input, control.
Gate-Level Details 287

Table A-10 Logic Table for bufif1 Primitive

Data 0 1 x z
1 HiZ St0 StL StL
1 HiZ St1 StH StH
x HiZ StX StX StX
z HiZ StX StX StX

NOTIF0

Figure A-11 NOTIF0 Gate

The notif0 primitive has two inputs, (data and control) and one output. When the
control input is “0” the output passes the opposite value as the data input, except
that an input of “z” produces an output of “x”. When the control input is “1” the
output is “z”. The port order of the primitive is output, input, control.

Table A-11 Logic Table for notif0 Primitive

Data 0 1 x z
0 Stl HiZ StH StH
1 St0 HiZ StL StL
x StX HiZ StX StX
z StX HiZ StX StX
288 Verilog Quickstart

NOTlF1

Figure A-12 NOTIF1 Gate

The notif1 primitive has two inputs, data and control and one output. When the
control input is “1” the output passes the opposite value as the data input, except
that an input of “z” produces an output of “x”. When the control input is “0” the
output is “z”. The port order of the primitive is output, input, control.

Table A-12 Logic Table for notif1 Primitive

Data 0 1 x z
0 HiZ Stl StH StH
1 HiZ St0 StL StL
x HiZ StX StX StX
Z HiZ StX StX StX

PULLDOWN

Figure A-13 Pulldown

The pulldown primitive has only one terminal. It outputs a 0 of strength pull (pu0).
When nothing else is driving a net stronger than the pulldown, the pulldown will
drive the net to 0.
Gate-Level Details 289

PULLUP

Figure A-14 Pullup

The pullup primitive has only one terminal. It outputs a 1 of strength pull (pul).
When nothing else is driving a net stronger than the pullup, the pullup will drive
the net to 1.

Switches

Verilog supports simulating transistors as switches. There are switch models of

unidirectional and bi-directional switches. There are model of both ideal and
resistive switches. Table A-21 details the signal strength reduction through the
switches.
290 Verilog Quickstart

NMOS and RNMOS

Figure A-15 NMOS or RNMOS Transistor

The nmos and rnmos primitives are abstractions of unidirectional switches. When
the gate input is 1, this input is passed to the output, otherwise the output is high
impedance. The difference between the nmos and rnmos is the nmos passes the
input to the output with the strength unchanged, but the rnmos passes the value to
the output with a decreased strength. The port order of the primitive is output,
input, gate.

The output strength from any of the transistor primitives is dependent on the
strength of the input. The input strength for the following tables is strong, unless
otherwise noted.

Table A-13 Logic Table for nmos Primitive

Data 0 1 x z
0 HiZ St0 StL StL
1 HiZ Stl StH StH
x HiZ StX StX StX
z HiZ HiZ HiZ HiZ

Table A-14 Logic Table for rnmos Primitive

Data 0 1 x z
0 HiZ Pu0 PuL PuL
1 HiZ Pul PuH PuH
x HiZ PuX PuX PuX
z HiZ HiZ HiZ HiZ
Gate-Level Details 291

PMOS and RPMOS

Figure A-16 PMOS or RPMOS Transistor

The pmos and rpmos primitives are abstractions of unidirectional switches. When
the gate input is 0, this input is passed to the output, otherwise the output is high
impedance. The difference between the pmos and rpmos is the pmos passes the
input to the output with the strength unchanged, but the rpmos passes the value to
the output with a decreased strength. The port order of the primitive is output,
input, gate.

Table A-15 Logic Table for pmos Primitive

Data 0 1 x z
0 St0 HiZ StL StL
1 St1 HiZ StH StH
X StX HiZ StX StX
Z HiZ HiZ HiZ HiZ

Data 0 1 x z
0 Pu0 HiZ PuL PuL
1 Pul HiZ PuH PuH
x PuX HiZ PuX PuX
z HiZ HiZ HiZ HiZ
292 Verilog Quickstart

CMOS and RCMOS

Figure A-17 CMOS or RCMOS transistor

The cmos and rcmos primitives are the equivalent or nmos and pmos (or rnmos and
rpmos) primitives connected back to back. The primitive has four terminals. The
port order is output, input, ngate, pgate.

Table A-17 Logic Table for cmos Primitive

ngate pgate 0 1 x z
0 0 St0 Stl StX HiZ
0 1 HiZ HiZ HiZ HiZ
0 x StL StH StX HiZ
0 z StL StH StX HiZ
1 0 St0 St1 StX HiZ
1 1 St0 St1 StX HiZ
1 x St0 St1 StX HiZ
1 Z St0 St1 StX HiZ
x 0 St0 St1 StX HiZ
x 1 StL StH StX HiZ
x x StL StH StX HiZ
x z StL StH StX HiZ
z 0 St0 Stl StX HiZ
zz 1 StL StH StX HiZ
z x StL StH StX HiZ
z z StL StH StX HiZ
Gate-Level Details 293

Table A-18 Loaic Table for rcmos Primitive

ngate pgate 0 1 x z
0 0 Pu0 Pul Pu0 HiZ
0 1 HiZ HiZ HiZ HiZ
0 x PuL PuH PuX HiZ
0 z PuL PuH PuX HiZ
1 0 Pu0 Pul PuX HiZ
1 1 Pu0 Pul PuX HiZ
1 x Pu0 Pul PuX HiZ
1 z Pu0 Pul PuX HiZ
x 0 Pu0 Pu1 PuX HiZ
x 1 PuL PuH PuX HiZ
x x PuL PuH PuX HiZ
x z PuL PuH PuX HiZ
z 0 Pu0 Pul PuX HiZ
z 1 PuL PuH PuX HiZ
z x PuL PuH PuX HiZ
z z PuL PuH PuX HiZ

TRAN and RTRAN

The tran and rtran primitives are bidirectional pass gates. They have only two
terminals that are the bidirectional data pins. Delay specifications are not allowed
on these primitives. The rtran primitive is resistive, and the strength is reduced as
the value passes through.

TRANIF0 and RTRANIF0

The tranif0 and rtranif0 primitives are bidirectional pass gates. They have three
terminals. The first two are the bidirectional data pins, the third is the control input.
When the control input is 0, data passes between the two bidirectional data pins.
Delay specifications on these primitives are only turn on and turn off delays. The
rtranif0 primitive is resistive, and the strength is reduced as the value passes
through.
294 Verilog Quickstart

TRANlF1 andRTRANlF1

The tranif1 and rtranif1 primitives are bi-directional pass gates. They have three
terminals. The first two are the bi-directional data pins, the third is the control
input. When the control input is 1, data passes between the two bi-directional data
pins. Delay specifications on these primitives are only turn on and turn off delays.
The rtranif1 primitive is resistive, and the strength is reduced as the value passes
through.

INSTANCE DETAILS

When you create an instance of one of the built-in primitives, the instance name is
optional as you learned in chapter 3. There are other optional arguments you may
specify when creating primitive instances: delays and strengths.

Delays

A primitive may have from zero to nine delay specifications. If a primitive instance
has no delay specification the primitive is zero delay. A primitive may have separate
delays for both rise (to 1) and fall (to 0) time. A primitive that can output high
impedance (such as bufif1, bufif0, and the switches) has an optional turn off (to z)
delay. The delay to x is always the least of the delays specified. If a single delay is
specified, it is used for both rise and fall (and turn off if applicable).

Delays are declared with the # delay operator. The order of the delays is rise, fall,
and turnoff.

Example A-1 Delays in Primitive Instances

module delays ;
and a1 (y, a, b), a2 (w, d, e, f); // zero delay and gates
and #1 a3 (x, a, c, e), a4 (z, e, f); // unit delay and gates
and #(3,2) a5(c, w, z); // rise delay of 3, fall delay of 2
bufifl #(3,2,4) b1(x, a,b); // turn off time is 4
bufif0 #(2:3:4,1:2:3,3:4:5) b2 (f, e, d); // min:typ:max
endmodule

Example A-1 shows primitive instances with between zero and nine delays
specified. Notice that similar to reg and wire declarations where the range in the
specification applies to each declaration, the delay(s) affect each of the instances in
the declaration. The instances a3 and a4 are both unit delay, and that delay of 1 is
used for both rise and fall time. Instance a5 illustrates specifying separate rise and
Gate-Level Details 295

fall delays. When multiple delays are specified they are enclosed in parentheses.
Instance b1 shows adding the third delay specification of turn off time.

Each of the delay specifications can be expanded to be a minimum, typical, and

maximum delay specification. When the min, typical, and max delays are specified
they are separated by colons as shown with instance b2.

Delay Units

All the delays throughout the book were unitless. In behavioral modeling a delay of
one could mean anything. In the phone example in chapter 1 a delay unit was
interpreted as one minute. In gate-level modeling you might want to use delays with
units such as 1 nanosecond or 1 picosecond.

Verilog allows both the specification of a delay unit and a delay precision on a per-
module basis. The delay unit and precision are declared with the `timescale
compiler directive.

The main drawback to using delay units is that if you use them on one module you
must use them on all modules. When you declare a delay unit and precision, that
declaration applies to all following modules. You can declare the unit and precision
for just one module and have that declaration carry forward to all your other
modules: Just make sure that the file with the delay unit and precision declaration is
the first one compiled. If you compile a module before a `timescale directive and a
`timescale directive appears later in the source, Verilog will issue an error message
and abort compiling your files.

Table A-19 Delay and Precision Units

Code Definition
fs femtoseconds
ps picoseconds
ns nanoseconds
us microseconds
ms milliseconds
s seconds

Table A-19 lists the units that can be used in a timescale declaration. The timescale
declaration goes outside a module, just before the module. The delay unit and
precision are a combination of 1, 10, or 100, and one of the unit codes in Table A-
19.
296 Verilog Quickstart

Example A-2 Time Scales

‘timescale Ins / 100ps

module modl;
// #1.1 in this module = 1.1 ns
endmodule

‘timescale 100ps / 1 ps
module mod2;
// #2 in this module = 200 ps
endmodule

Example A-2 shows two modules with their timescales. With the addition of the
time unit and precision, decimal delays are possible. Timescales and decimal delays
are usable for both behavioral and gate-level modeling, but most delays in
behavioral modeling are unitless. Behavioral modeling tends to be more abstract
and delays less important than delays in gate-level models.

Printing Out Time and the Timescale

The format code %t will print out the value of $time or $realtime including the
units.

Strengths

As mentioned in chapter 2, Verilog supports seven levels of strength. A behavioral

statement such as a register or continuous assignment always drives with a strength
of strong. By default all gate instances drive with strength strong, with the
exception of the pullup, pulldown, and resistive transistors which are pull, or are
decreased by one strength level.

A primitive instance may optionally include the drive strengths from the drive0 and
drive1 columns of Table A-20 to indicate the drive strength of the gate.
Gate-Level Details 297

Table A-20 strengths

value %v drive0 drive1 Description
0 Hi highz0 highzl High impedance
1 Sm - - Small capacitor
2 Me - - Medium capacitor
3 We weak0 weak1 Weak drive
4 La - - Large capacitor
5 Pu pull0 pull1 Pull drive
6 St strong0 strong1 Strong drive
7 Su supply0 supply1 Supply drive

The drive strength of an instance is specified before the delay and the order of
strength declarations may be either strength1 or strength0 first. Example A-3 shows
declarations including strengths and delays.

Example A-3 Strength Declarations

module strength;
nand (strong0, highz1) oc1(z, a, b) oc2(w, d, e);
buf (weakl, weak0) #6 wimpo(out, in);
myudp (pull0, pull1) #(2:3:4,1:2:3) u1(q, c, d, r, s);
endmodule

Instances oc1 and oc2 in Example A-3 could be an example of a TTL open collector
NAND gate such as the 7401. As you may know, open collector drivers have strong
drive low, but no drive high, so they need a pullup resistor to achieve a value of 1.
The example buffer shows combining the syntax for specifying strengths with the
syntax of specifying a delay.

The final instance, u1, is an example of a user-defined primitive. The user-defined

primitive myudp is assumed to be declared elsewhere. UDP instances also allow the
specification of both strengths and delays.

Displaying Strengths with %v

The format code %v provides more information than %b. The output produced by
%v is three characters, which describe in more detail the value and strength of a net.
The first two characters describe the strength as described in Table A-20. The third
character describes the value. Two new value codes are added to the 0, 1, X, Z set.
The two new codes are H and L. The value H represents either a 1 or a Z. The value
L represents either a 0 or a Z.
298 Verilog Quickstart

Nets in Verilog may be one of 120 possible values. All of these values can be
printed out with %v. Some of the values do not print out as nicely as the codes from
Table A-20. These values print out the strength portion of the value with a two-digit
numeric code. Values such as 65X and 241 can be printed out by %v. If the third
character in the value is X, the first number represents the zero strength and the
second number represents the one strength. If the third character in the value is 0 or
1, then the first two numbers represent a possible range of strength for the value.

Strength Reduction of Switch Primitives

Table A-21 shows the output strength for the switch primitives. The nmos, pmos,
cmos, tran, tranif0, and tranif1 primitives are considered to be ideal devices since
the strength is not reduced through them, except that supply strength is reduced to
strong. The rnmos, rpmos, rcmos, rtran, rtranif0, and rtranif1 primitives are
considered to be resistive devices since the strength is reduced through them.

Table A-21 Switch Strength Reduction

Input Strength Ideal Device Output Resistive Device Output
Strength Strength
supply strong pull
strong strong pull
pull pull weak
weak weak medium
large large medium
medium medium small
small small small
high impedance high impedance high impedance

All this detail with strengths is important for switch-level modeling, but is not used
in behavioral modeling.
 Appendix B EXAMPLE SUMMARY

This appendix is simply a quick reference for all the examples.

All the examples that are complete modules are syntactically correct. The CM
column of the table indicates the examples that are complete modules.

The synthesizable column (marked by SY) indicates if the module conforms to

common synthesizable styles. Not all modules listed as synthesizable may be
synthesizable with every tool, since the guidelines vary from tool to tool and release
to release.

Examples that are not complete modules are marked synthesizable if the code in the
example is synthesizable in a complete module.

Examples are marked non-synthesizable either if the code violates a common

synthesis style or else if it would not generate any logic (like a $display statement).
300 Verilog Quickstart

Title Page CM SY Notes

1-1 Abstract Model of a Phone 5 y n Abstract system

1-2 Verilog for Gate-Level Mux 7 y y Netlist of primitives

2-1 Simple Hello Module 11 y n Simple module

2-2 Hello Module without White 11 y n Demonstration of

Space compacted code
2-3 Hello Module with Extra 11 y n Demonstration of white
White Space space
2-4 Illegal Use of White Space 11 n n

2-5 Comments 12 n y Just comments

2-6 Numbers 13 n y Just numbers

2-7 Specifying a Text Macro 13 n y

2-8 Using a Text Macro 13 n y

2-9 Gate-Level Mux Verilog 14 y y Netlist of primitives

Code
3-1 Verilog Code for the 2-Input 21 n y Gate instances
and 4-Input AND Gates
3-2 Verilog for Gate-Level Mux 22 y y Netlist of primitives

3-3 Hierarchical 2-Bit Mux 23 y y Netlist of modules

3-4 Hierarchical 4-Bit Mux 24 y y Netlist of modules

3-5 Hierarchical Names 26 n n Justexamplesof names

3-6 Mux Connected by Name 26 y y Connect by name Syntax

3-7 Hello Verilog 28 n n Simple module to test

installation
3-8 Adder Test Module 31 y n Test bench for exercise

4-1 An initial Block 34 n n Explanation of initial

Example Summary 301

Title Page CM SY Notes

4-2 An always Block 35 n n Explanation of always

4-3 Three initial Statements 35 y n Zero-delay races

4-4 Three initial Statements with 36 y n Timing between initial

Delay blocks
4-5 Simple begin-end Block 36 y n Explanation of begin-end

4-6 begin-end Block with Delay 37 y n Explanation of delays

4-7 Multiple begin-end Blocks 37 y n Interaction of delays

4-8 fork-join Blocks 39 y n Explanation of fork-join

4-9 Combining begin-end and 41 y n Complex example of

fork-join Blocks timing between blocks
4-10 Displaying a String 47 n n Explanation of $display

4-11 Displaying a Single Value 47 n n Explanation of $display

4-12 Displaying Multiple Values 48 n n Explanation of $display

4-13 Using Format Specifiers with 48 n n Explanation of $display

$display
4-14 Two $display Statements 49 y n Explanation of $display

4-15 Combining $write and 49 y n Explanation of $write

$display
4-16 Writing to a File 50 y n Explanation of $fopen and
$fdisplay
4-17 Writing to Multiple Files 51 y n Explanation of $fopen and
$fdisplay
4-1 8 $display with $time 54 n n Field sizes

4-19 Leading Spaces in $monitor 55 n n Field sizes

with $time
4-20 Spaces Used To Print an 8- 55 n n Field sizes
Bit Value
4-21 Suppressing Leading Spaces 56 n n Overriding default field
and Zeroes size
302 Verilog Quickstart

Title Page CM SY Notes

4-22 Net Declarations 59 n y Various net declarations

4-23 Incorrect Net Declaration 59 n n Common error

4-24 Setting Default Net Type 60 n n

4-25 Register Declarations 60 n y

4-26 Selecting Bits and Parts of a 60 n y

Register
4-27 Memory and Register 61 n y
Declarations
4-28 Selecting Bits in Registers 61 n y
and Words in Memories
4-29 Reg Declaration with 61 n n Newin IEEE 1364-1999
Initialization
4-30 Declaring Integers and Reals 62 n n

4-31 Declaring Variables of Type 63 n n

time
4-32 Parameters 63 n y

4-33 Events 64 n n

4-34 Strings 64 y n Storage of strings

4-35 Multi-Dimensional Arrays of 64 n y New in IEEE1364-1999

Nets
4-36 Multi-Dimensional Arrays of 65 n y New in IEEE1364-1999
Regs
4-37 Accessing Multi-Dimensional 65 n y New in IEEE1364-1999
Arrays
4-38 Simple Procedural 66 y n
Assignments
4-39 Procedural Assignments with 66 y n
fork-join
4-40 fork-join with Intra- 67 y n
assignment Delays
4-41 fork-join with Multiple Delays 67 y n
Example Summary 303

Title Page CM SY Notes

4-42 fork-join with Simplified 68 y n
Delays
4-43 Effect of Intra-assignment 68 y n
Delays on Time Flow
4-44 Nonblocking Assignments 69 y n

4-45 Output as a Register 70 y y Simple flip-flop

5-1 Using Operators 73 n y

5-2 Distinguishing between Bit- 74 y n

wise and Logical Operators
5-3 Using Reduction Operators 75 y n

5-4 Ternary Operator 75 n y result = a ? b: c

5-5 Using the Ternary Operator 76 y y out = enable ? in : 16'bz

for a Three-State Buffer
5-6 Module To Test an Operator 79 y n

5-7 Concatenations 80 n y

5-8 Bit-wise and Logical 81 n n Not Verilog, just equations

Operations
5-9 Operators and Strings 82 y n Storage of strings

5-1 0 Combinations of Operators 83 n y Combining operators and

for Exclusive-NOR sizing expressions
5-1 1 Signed Declarations 84 n y NewinIEEE1364-1999

5-1 2 Signed Constants 84 n y NewinIEEE1364-1999

5-13 Effect of Signed Constants 85 n y New in IEEE1364-1999

6-1 Three-State Buffer Using a 88 y y 16-bit buffer

Continuous Assignment
6-2 A 128-Bit Adder in a 88 y y
Continuous Assignment
6-3 Continuous Assignment 89 y y
Multiplier
304 Verilog Quickstart

Title PageCM SY Notes

6-4 Connecting Four Registers to 90 y n
a Wire
6-5 Alternate Form of Continuous 90 y y Net declaration
Assignment
6-6 Many Formsof Continuous 90 y y
Assignments
6-7 Waiting for an Event 91 y y Simple flip-flop

6-8 Mux Using Continuous 92 y y

Assignment
6-9 Mux Using always Block 92 y y

6-10 Always Block Using Comma 93 n y New in IEEE1364-1999

6-11 Combinatorial Always Block 93 n y New in IEEE1364-1999

6-12 Incorrect Mux 93 y y May synthesize into a rnux

differing from simulated
results
6-13 Using the event Data Type 94 y n

6-14 Using Events To Simplify 95 n n Style to model an abstract

Modeling processor
6-15 always Explained 96 y n Potential error

6-16 Using wait 96 y n

6-17 Using wait To Detect an 97 n n Good for a test bench

Unknown
6-18 Using alwaysTo Detect an 97 n n
Unknown
6-19 Simple if 98 n n

6-20 if with else 98 n n

6-21 Nested if with else 98 n n

6-22 The case Statement 99 y y 4-to-1 mux

Example Summary 305

Title Page CM SY Notes

6-23 case Matching x and z 100 y y 4-to-1 mux

6-24 Using casez 100 y y Loadablecounter

6-25 Test Bench for the ALU 105 y n task and external data file

6-26 Oscillator Using always 108 y n

6-27 Oscillator Using forever 108 y n

6-28 Repeating "Hello Verilog" 109 y n repeat loop

6-29 Using repeat in a State 109 y y Shifter, implicit state

Machine machine style
6-30 A while Loop 110 y y Counts bits set

6-31 A Simple for loop 111 y n

6-32 A for Loop with Expressions 111 y n

Not Referencing the Same
Variable
6-33 A Simple Flip-Flop 112 y y

6-34 A Flip-Flop with a Bad Reset 112 y n

6-35 A Flip-Flop with Reset 113 y y

6-36 A Flip-Flop with Incorrect Set 113 y n

and Reset
6-37 A Flip-Flop with Correct Set 114 y y
and Reset
6-38 Incorrect Mux 115 y n May synthesize into a mux
and not match simulation
6-39 Mux with PCA 115 y n Synthesis does not support
this use of PCA
6-40 Hello Verilog Tasks 117 y n

6-41 task with Inputs, Outputs, 118 y n

and External References
306 Verilog Quickstart

Title Page CM SY Notes

6-42 Effect of task Port Size 119 y n

6-43 Accessing a task Local 119 y n

Variable from Outside the
task
6-44 task Local and Module Items 120 y n
with the Same Name
6-45 Read Cycle task 121 y n

6-46 Re-Entrant Task 122 y n Collision on local variables

6-47 Count Bits Function 123 y n

6-48 Mux with Function and 124 y y 4-to-1 mux

Continuous Assignment
6-48 Divide Function Returning 125 y n
Two 8-Bit Values
6-50 inout Port Connected to a 127 y n
Register
6-51 Register with Controllable 127 y n
Connection to inout Port
6-52 Named Blocks 128 y n

6-53 The disable Statement 128 y n

6-54 disable Used To Model Reset 129 y n Partial CPU example

6-55 Controlling When a 131 n n

Simulation Finishes
7-1 Optimistic Mux UDP 134 y n UDPs are not in synthesis
source
7-2 Pessimistic Mux UDP 135 y n

7-3 One-Line UDP 136 y n

7-4 Level-Sensitive D Latch 136 y n

7-5 Edge-Sensitive D Flip-Flop 137 y n

Example Summary 307

Title Page CM SY Notes

7-6 Flip-Flop Using Explicit Edge 138 y n
Definitions
7-7 initial Block in a UDP 139 y n

8-1 parameter Statements 144 n n Syntax examples

8-2 n-Bit Wide 4-to-1 Mux 144 y y

8-3 Parameterized Width Adder 145 y y

8-4 Mux with Parameterized 145 y n

Width and Number of Inputs
8-5 Parameterized RAM 146 y n

8-6 The defparam Statement 147 n n Syntax example

8-7 Using Parameterized 147 y n

Modules
8-8 Parameter Passing by Order 148 y y Prefered by Synopsys

8-9 Parameter Passing by 149 y y NewinIEEE1364-1999

Named List
9-1 Style 1 Moore State Machine 155 y y

9-2 Style 1 Mealy State Machine 156 y y

9-3 Style 2 Moore Machine 156 y y

9-4 Style 2 Mealy Machine 157 y y

9-5 Style 3 Mealy Machine 158 y y

9-6 Style 4 Mealy Machine 159 y y

9-7 Style 5 Moore Machine 160 y y

9-8 Implicit State Machine Style 164 y y

9-9 Combinatorial Outputs 165 n y Just output section of

previous examples
308 Verilog Quickstart

Title Page CM SY Notes

9-1 0 Registered Outputs 165 n y Just output section of
previous examples
10-1 A 2-to-1 Mux Using 168 y y
Continuous Assignment
10-2 A 4-to-1 Mux Using 168 y y
Continuous Assignment
10-3 Alternate 4-to-1 Mux Using 169 y y
Continuous Assignment
10-4 An 8-Bit Adder Using 169 y y
Continuous Assignment
10-5 Latch Using Continuous 169 y n Feedbackviolates
Assignment synthesis style
10-6 The 2-to-1 Mux Using always 170 y y

10-7 The 4-to-1 Mux Using always 171 y y

10-8 The 8-Bit Adder Using 171 y y The loop is unrolled in

always synthesis
10-9 Simplified 8-Bit Adder Using 172 y y
always
10-10 Mux with Continuous 172 y y
Assignment and function
10-11 Simple Counter 173 y y

10-12 A Counter without always 174 y n

10-13 Sequential Stimulus Block 174 y n

10-14 Clock Source 174 y n

10-15 Memory Exerciser 175 y n

10-16 Tasks for Sequential Code 176 y n

10-17 Basic One-Shot 178 y n

10-18 Retriggerable One-Shot 179 y n

10-19 Behavioral Description of the 180 y n

Alarm
Example Summary 309

Title PageCM SY Notes

10-20 Alarm Test Bench 182 y n

10-21 Partial Implementation of 184 y n

Alarm
10-22 Two -Dimensional Array 186 y n

10-23 Behavioral Z-Detector 186 y n

10-24 Structural Z-Detector 187 y n

10-25 An 8-by-8 Booth Multiplier 187 y y

10-26 Wallace 8-by-8 Multiplier 189 y y

10-27 A 16-by-16 Multiplier 191 y y

10-28 A 16-by-16 Wallace Multiplier 194 y y

for Signed Numbers
11-1 Normal D Flip-Flop 201 y y

11-2 Modified D Flip-Flop 201 y n Speed-up trick

11-3 Bad Register 204 y n Bad style

11-4 Improved Register 205 y y

11-5 Tweaked Register 206 y n

11-6 Bad Adder 206 y n Common novice error

11-7 Improved Adder 207 y y

11-8 Adder Reduced to a 207 y y

Continuous Assignment
11-9 Bad Mux 208 y n Common novice error

11-10 Improved Mux 208 y y

11-11 Bad Barrel Shifter 209 y n

310 Verilog Quickstart

Title Page CM SY Notes

11-12 Improved Barrel Shifter 210 y n

11-13 Blocking vs. Non Blocking 211 y

Assignments
12-1 Adder Test Module Repeated 216 y n Simple test bench

12-2 Using Verilog To Calculate 217 y n Improved test bench

Responses
12-3 Simplifying the Test Bench 218 y n More improved test bench
with a task
12-4 Using a Second Module To 219 y n
Check the Results
12-5 Generating x's for 220 y n
Miscom pare
12-6 Printer Abstraction 222 y n

12-7 Printer Test Bench with 223 y n

Guessed Timing
12-8 Response-Driven Printer 224 y n
Test Bench
12-9 Test Bench for a RAM 225 y n

12-10 Memory Declaration 226 n n Declaration reminder

12-11 Reversed Memory 226 n n Declaration reminder

Declaration
12-12 Memory File adder8.vec 227 n n File for $reabmemb

12-13 Adder Test Bench Reading 227 y n

from a File
12-14 PROM Data File prom.dat 228 n n File for $readmemh

12-15 Simple PROM 228 y n PROM loads memory file

12-16 Test Bench with No Vectors 229 y n

12-17 LFSR 231 y n Testan LFSR

12-18 Testing the ALU with a LFSR 232 y n Abstraction of BIST

and MlSR
Example Summary 311

Title Page CM SY Notes

12-19 ALU Modified Capture of 234 n n
Inputs and Outputs
12-20 ALU Test Bench Repeated 234 y n

13-1 Missing Initialization 242 y n Common error

13-2 Negative Setup Time 244 y y Common error

13-3 Corrected Register 244 y y

14-1 Initial Block To Create VCD 251 n n Generate wave database

Wave File
14-2 Initial Block To Create SHM 251 n n Generate wave database
Wave File
14-3 Interactive Verilog Module 253 y n Demonstrate interactive
simulation
14-4 Single-Stepping 255 y n

14-5 always Loop Module 259 y n Interactively setting and

displaying values
14-6 my.key Command File 267 n n Keystroke file

14-7 Hierarchical 8-Bit Adder 270 y y

A-1 Delays in Primitive Instances 296

A-2 Time Scales 298

A-3 Strength Declarations 299

 INDEX

$cleartrace, 275
- $display, 47, 214
- subtraction, 72 for debug, 249
- no change, 137 specifying format, 48
See Command line option supressing spaces, 54
$dumpfile, 25 1
! $dumpvars, 251
!, 73 $fclose, 50
!=, 76, 77 $fdisplay, 51, 233
!==, 76,77 $finish, 131
$fmonitor, 51
" $fopen, 50
" and white space, 11 $fstrobe, 233
$fwrite, 51
$incpattern, 236
# $input, 266
#, 36 $key, 267
$list, 272
$ $monitor, 50, 214
$, 47 $monitoroff, 50
314 Verilog Quickstart

$monitoron, 50 *
$nokey, 267 *, 72
$random **, 72
example, 5
$readmemb, 226
$readmemh, 226 ’
$realtime, 62, 296 ,, 260
$restart, 275
$save, 275 .
$scope, 269 ., 260
$settrace, 275
$shmopen, 25 1 /
$shmprobe, 25 1 /, 72
$showscopes, 269 /*, 12
$showvars, 273 //, 12
$stop, 252
$strobe, 49,50 ?
$strobe_compare, 236 ?
$time, 62, 296 in case statement, 101
$write, 49 in udp table, 135
?:, 75, 168
% in testbench, 224
%, 72
%%, 54 @
%0b,54 @, 91
%0d, 54 memory address, 228
%0h,54
%0o, 54 ^
%b, 54 ^, 72
%c, 54
%d, 54 `
%e, 54
`defaultnettype, 59
%f, 54
`define, 13
%h, 54
`timescale, 62, 295
%m, 54
%o, 54
%s, 54 {
%t, 54,296 {{ }}, 79
%v, 54,297 { },79

& /
&, 72 |, 72
&&, 72 ||, 72
Index 315
~ address in file, 228
~, 73 alarm, 180
always, 34
+ combinatorial for synthesis, 170
+, 72 explained, 96
++, 110 sensitivity list, 92
sequential, 173
< synthesis, 173
<<, 72 synthesizable combinatorial logic,
<<<, 72 92
<= zero delay, 130
less than or equal to, 77 and
non blocking assignment, 69 bitwise, 72
synthesis, 211 built in gate, 20
when to use non blocking, 211 built in primitve, 282
logical, 73
= reduction, 74
= arithmetic operators, 72
arrays
synthesis, 21 1
of regs, 60
==, 77 two-dimensional, 185
===, 77 ascending range, 58
assign, 113
> improper use, 241
->, 94 assignement
> =, 77 conditional, 75
>>, 72 assignment
>>>, 72 blocking vs non blocking, 211
conditional, 88
0 continuous, 87
0 nonblocking, 69
value, 15 procedural, 65
quasi-continuous. See procedural
1 continuous assignment
1 with delays, 67
value, 15 assignments
procedural continuous, 111
A procedural for combinatorial
abstraction logic, 211
levels, 4 procedural for sequential logic,
active low signals, 10 211
adder, 171 asynchronous, 179
schematic, 28 asynchronous circuits, 178
simulation, 28
316 Verilog Quickstart

B casez, 100, 101

base, 12 cleartrace, 275
default, 13 clock, 174
default for printing, 52 clock-to-q delay, 2 12
printing, 48 cmos, 292
begin-end, 36 built in primitive, 20
disabling, 128 combinatorial, 88, 92
named, 128 udp, 134
nesting, 41 combinatorial logic, 168
with delay, 37 functions, 172
behavioral model pay off, 198 combinatorial logic synthesis, 167
bi-directional switches, 289 command history, 260
binary, 13 command line option
binary operators, 71 -i, 264
BIST, 230 -k, 267
bit range, 58 -r, 275
bit selection, 60 -s, 252
bit width comments, 12
of declarations, 58 nesting, 12
of expressions, 73 comp.cad.cadence, 8
of logical expressions, 72 comp.cad.synthesis, 8
of reduction expressions, 73 comp.lang.verilog, 7
of unary expressions, 73 compiler directive
bit width of expressions, 83 `defaultnettype, 59
blocking assignment, 211 `define, 13
Booth multiplier, 187 `timescale, 62
breakpoint, 252 complement operators, 73
buf, 285 concatenations, 79
built in gate, 20 concurrent, 5
buffer conditional assignment, 88
three-state, 76, 88 condtional assignement, 75
bufif0, 286 connect by name, 26
built in gate, 20 connect by order, 26
bufif1, 286 connecting, 19
built in gate, 20 continuous assignement
building block, 14 in net declaration, 90
built in primitive instance, 294 synthesis, 168
bus, 58 continuous assignment, 87, 168
and function, 124
C continuous assignment buffer, 88
case, 98, 101 continuous simulation, 4
case equality. See literal equivalence control-c, 259
case sensitive names, 9
casex, 98, 101
Index 317

D display, 214
deassign, 113 for debug, 249
debug, 214 suppressing spaces, 54
decimal, 13 documentation, 3
declaration dump file, 251
array of reg, 60 dump task
bit index, 58 for memory, 146
bus, 58 dumpfile, 251
event, 63 dumpvars, 251
implicit net, 59
integer, 62 E
memory, 60 edge sensative
net, 58 udp, 136
edge sensitive
90 always, 91
parameter, 63 else, 98
range, 58 endcase, 99
real, 62 endfunction, 123
realtime, 62 endmodule, 14
reg, 60 endprimitive, 135
time, 62 endtable, 135
vector, 58 endtask, 116
declarations equal, 76
missing width, 239 equivalence, 77
declatation escaped identifiers, 10
string, 64 event, 91, 94
decompile, 272 example, 5
default net type, 59 using, 94
default value event list, 92
parameter override, 147 event-driven simulation, 4
define, 13 events, 63
defparam, 147 example, 5
delay, 36 expression
in primitive instance, 294 bit width of, 83
max, 295 truncation, 83
min, 295
proper use for synthesis, 212 F
turn off, 294 fall time, 294
typical, 295 fanin, 273
units, 295 fclose, 50
descending range, 58 fdisplay, 51, 233
design unit, 14 file
dff, 91 closing, 50
disable, 128 numbers, 51
318 Verilog Quickstart

opening, 50 H
printing to, 50 hexadecimal, 13
reading, 228 hierarchical names, 25
test vector, 234 hierarchy, 22
writing, 233 traversing interactively, 269
files high impedance
multiple, 51 continuous assignment buffer, 88
finish, 131 Highest level modules, 27
finishing simulation, 131 history, 260
flip-flop, 91
modified for speed, 201
I
with reset, 113
-i, 264
fmonitor, 51
Identifiers, 9
fopen, 50
escaped, 10
for, 110
IEEE standard, 8
for loop, 110
IEEE1364-1999, 65, 84, 92
force, 274
if, 97
forever, 107
illegal left hand side assignment, 238
forever loop, 108
illegal part select, 240
fork-join, 39
implicit net declaration, 59
disabling, 128
implicit state machine, 164
named, 128
incpattern, 236
nesting, 41
inferred latches, 243
frequently asked questions, 8
inferred registers, 243
fs, 295
initial, 34
fstrobe, 233
in UDP, 138
function, 123
inout, 21
and continuous assignment, 124
in testbench, 224
synthesis, 172
test bench, 225
with continuous assignment, 172
inout port
Functional Testing, 215
and task, 118
fwrite, 51
modeling with, 126
input, 21,266
G input port
gate and task, 118
instance, 22 instance, 21, 22
gate instance, 294 built in primitive, 294
with strength, 297 gate, 22
gate level modeling, 22 of module, 24
gates, 19, 20 primitive, 22
Gateway Design Automation, 2 user defined primitive, 139
Gray code, 161, 162 integer, 62
interactive simulation prompt, 253
internet
Index 319

newsgroups, 7 max delay, 295

interrupt, 252 me, 297
invert operators, 73 Mealy, 151
inverter, 285 medium, 15
medium capacitor, 297
K memory
-k, 267 dump task, 146
key, 267 reg declaration, 60
keys in interactive simulation, 255 memory address
keystroke file, 264 specifying in file, 228
replaying, 264 min delay, 295
MISR, 230
L modeling
la, 297 structural, 19
language modeling style, 200
loosely typed, 4 module, 14
strongly typed, 4 module instance, 24
large, 15 monitor, 50,214
large capacitor, 297 monitoroff, 50
latches monitoron, 50
inferred, 243 Moore, 151
length ms, 295
for identifiers, 9 mult-bit wire, 58
level sensitive, 96 multiplier
lexical conventions, 9 Booth, 187
LFSR, 230 Wallace, 189
list, 272 mux
literal equivalence, 77 2-bit, 22
log file, 47, 250 2-to-1, 168
logical expression, 81 4-bit, 23
logical operators, 72 4-to-1, 168
loop Schematic, 22
always, 34, 107 structural explained, 14
for, 110 synthesizable, 170
forever, 108 with always, 92
repeat, 108 with continuous assignment, 91
while, 109 with PCA, 115
zero delay, 24 1
loosely typed language, 4 N
low active n, 54
signals, 10 named
begin-end, 128
M fork-join, 128
macro text, 13 Named Blocks, 128
320 Verilog Quickstart
names number format, 12
hierarchical, 25 numbers, 12, 17
legal charaters, 9 default radix, 13
length, 9
rules for, 9 O
nand octal, 13
built in gate, 20 one hot, 163
built in primitive, 282 one-shot, 178
negated operations
signals, 10 signed, 84
Negation, 73 operators
Negative setup time, 244 !, 73
negedge, 91 !=, 77
nested !==,77
if, 98 %, 72
nesting &, 72
begin-end, 41 &&, 72
comments, 12 *, 72
fork-join, 41 **, 72
net, 57 /, 72
declaration, 58 ?:, 75
default type, 58,59 ^, 72
implicit, 59 ||, 72
range, 58 |||, 72
types, 57 ~, 73
net declaration +, 72
with continuous assignement, 90 ++, 110
netlist, 19, 24
<<, 72
nmos, 290 <<<, 72
built in primitive, 20 <=, 77
nokey, 267 ==, 77
non blocking assignment, 211
nor == =, 77
>=, 77
built in gate, 20 >>, 72
built in primitive, 283 >>>, 72
not, 285 arithmetic, 72
built in gate, 20 binary, 71
not equal, 76 bit-wise, 72
notif0, 287 bitwise, 81
built in gate, 20 concatenation,79
notif1, 288 equality, 76
built in gate, 20 logical, 72, 81
ns, 295 precedence, 80
number reals, 82
unknown, 16
Index 321
reduction, 73 primitive, 135
repeat, 79 instance, 22
strings, 82 primitive instance, 294
ternary, 75 with strength, 297
testing, 79 primitives, 19
unary, 73 print on change, 50
or printing
bitwise, 72 log file, 47
built in gate, 20 signed values, 84
built in primitve, 283 printing results, 47
for events, 92 procedural assignment, 65
logical, 73 procedural continuous assignment,
reduction, 74 111, 240
oscillation programmable array logic, 2
zero delay in simulation, 211 progressive refinement, 197
oscillator, 108 prompt, 253
output, 21 ps, 295
output port pu, 297
and task, 118 pull, 15, 297
OVI, 8 pull0, 297
pull1, 297
P pulldown, 288
PAL, 2 built in primitive, 20
PALASM, 2 net with, 57
parameter, 63, 143 pullup, 289
default value, 63 built in primitive, 20
overriding default value, 147 net with, 57
range, 143
part selection, 60 Q
pass gate, 289 qualified expression, 75
PCA, 111 quasi-continuous assignment. See
phone, 5 procedural continuous assignment
pmos, 291 questions
built in primitive, 20 frequently asked, 8
polynomial, 230 quitting simulation, 13 1, 252
port, 20
ports, 21 R
and registers, 69, 126 -r, 275
and tasks, 116 race conditions, 21 1
mismatch, 237 eliminating, 212
module, 21 radix, 12
primitive, 20 default, 13
posedge, 91 default for printing, 52
precedence of operators, 80
printing, 48
322 VeriIog Quickstart

Radix Specifiers, 13 S
RAM -s, 252
test bench, 225 s, 295
ram model, 146
save, 275
random
schematic, 19
example, 5 schematics, 19
range, 58
scope, 269
reverscd, 240 Self-Checking Test Benches, 215
remos, 292 semicolon, 14, 254
built in primitive, 20 sensitivity list, 92
readmemb, 226
sequential, 5
readmemh, 226
udp, 136
real, 62
sequential logic, 173
operators with, 82 settrace, 275
realtime, 296 shift operators, 72
reduction of strength, 298 shm, 251
reg, 60 shmopen, 251
and port declarations, 69 shmprobe, 251
initial value, 61
showscopes, 269
parameterized declaration, 144 showvars, 273
registers sign extension, 16
inferred, 243 signaling an event ->, 94
Regression Testing, 215 signed operations, 84
release, 274 signed constant, 84
repeat, 108, 171 signed values
repeat loop, 108 printing, 84
synthesis, 171 simulation, 2
repeat operator, 79 simulation performance, 199
response driven stimulus, 221 Simulation types
restart, 275
continuous, 4
results discrete, 4
log file, 47 single step, 255
print on change, 50 Sizing Expressions, 83
rise time, 294 sm, 297
rnmos, 290 small, 15
built in primitive, 20
small capacitor, 297
rpmos, 291 space
built in primitive, 20 suppressing, 54
rtran, 293 SPICE, 4
built in primitive, 20
st, 297
rtranif0, 293 start here at time 0, 34
rtranif1, 294 state, 15
built in primitive, 20 state machines
and synthesis, 160
Index 323
best style, 160 system tasks, 47
choosing a style, 166 system test, 221
default state, 163
encoding, 161 T
explicit, 155 table, 135
implicit, 164 talkverilog, 8
Mealy, 151 task, 116
Moore, 151 and sequential models, 176
stimulus in test bench, 218
response driven, 221 terminal, 21
stop, 252
ternary operator, 168
storage node, 57 test
strength, 15, 296 functional, 215
in primitive instance, 297
test vector
reduction, 290 capture, 236
strength reduction, 298
test vectors, 234
string
text macro, 13
printing, 47 then, 97
strings, 64, 82
three-state buffer, 76, 88, 286
operators with, 82 three-state inverter, 287, 288
strobe, 50 time, 62,296
strobe_compare, 236
timescale, 62, 295
strong, 15, 297 top level module, 27
strong0, 297
tracing, 39, 275
strong1, 297 tran, 293
Structural modeling, 19, 24
built in primitive, 20
su, 297
tranif0, 293
supply, 15, 297 built in primitive, 20
supply0, 57,297 tranif1 , 294
supply 1, 57, 297
built in primitive, 20
switches, 19, 289 traversing hierarchy, 269
syntax error, 241
tri, 57
synthesis, 3, 201 tri0, 57
<=, 211 tri1, 57
=, 211 triand, 57
asynchronous, 179 trior, 57
combinatorial always, 170
trireg, 57
combinatorial logic, 167
truncation, 83
continuous assignement, 168
truth table, 133
delays, 2 12
typical delay, 295
flowchart for checking, 203
functions, 172
repeat loop, 171
U
state machines, 160 UDP, 133
synthesizable, 202 combinatorial, 134
324 Verilog Quickstart

instances, 139 implicit declaration, 59

sequential, 136 mult-bit, 58
symbols, 140 wire declaration
When to use, 210 with continuous assignement, 90
with initial, 138 wires, 57
unit delay, 2 12
unit test, 221 X
unknown in simulation, 242 x
unknown value, 16 in case statement 98, 101
unknowns in debug, 220
detecting, 97 value, 15
us, 295 x in simulation, 242
usenet, 7, 8 XL algorithm, 2
user defined primitive, 133 xnor
built in gate, 20
V built in primitive, 284
value set, 15 xor
values, 15 bitwise, 72
VCD built in gate, 20
file, 251 built in primitive, 284
format, 251 reduction, 74
vector, 58
range, 58 Z
width, 58 Z
value, 15
W Z-Detector, 186
wait, 96 zero delay, 212
wait for event, 91 zero delay loop, 241
Wallace multiplier, 189 zero delay oscillation, 211
wave zero delay races, 244
file, 251 zero time, 244
wave display, 250
wave file, 250
wave form, 212
we, 297
weak, 15, 297
weak0, 297
weak1, 297
while, 109
while loop, 109
white-space, 11
and qoutes, 11
wire, 57
default type, 58