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Digital Electronics Exam

This document contains an examination for a Bachelor of Science degree in Electrical and Electronics Engineering. It has 4 questions covering various topics in digital electronics including binary conversions, Boolean algebra, combinational logic, flip-flops, counters, and shift registers. Students are asked to solve problems involving decoding Gray code, magnitude comparators, state diagrams, and analyzing digital circuits. They are provided with diagrams and asked to derive optimal logic implementations.

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Peter Jumre
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271 views

Digital Electronics Exam

This document contains an examination for a Bachelor of Science degree in Electrical and Electronics Engineering. It has 4 questions covering various topics in digital electronics including binary conversions, Boolean algebra, combinational logic, flip-flops, counters, and shift registers. Students are asked to solve problems involving decoding Gray code, magnitude comparators, state diagrams, and analyzing digital circuits. They are provided with diagrams and asked to derive optimal logic implementations.

Uploaded by

Peter Jumre
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIVERSITY OF NAIROBI

FIRST SEMESTER EXAMINATIONS 2020/2021


DEGREE OFBACHELOR OF SCIENCE
THIRD YEAR EXAMINATIONS FOR THE ENGINEERING
IN ELECTRICAL AND ELECTRONICS
FEE331: DIGITAL ELECTRONICS
TIME: 10.30 A.M.-12.30 P.M.L
DATE:25 FEBRUARY2021

nstructions to candiadates: THREE Do NOT give multiple solutions


This examination paper has FOUR questions. Answer only questions.
to a question and start each answer on a fresh page.

QUESTION 1.
(a).
Give the decimal number -71 in 8-bit format in the following schemes (6 Marks)

) Sign-magnitude scheme
(i) 1's complement scheme
(ii) 2's complement scheme

(b).
Convert the octal number 365 into BCD form. (2 Marks)

(c) the
Using deMorgan's theorem and other axioms of Boolean algebra, simplify
following expression and implement Ywitha minimum number of logic gates. (6 Marks)

Y= (A +B)(A+ C)(ABC + AB)


(d). C and D in the usual
A combinational logic circuit has an output Y and four inputs A, B,
order of significance. The behaviour of the circuit is given by the mintem equation

Y = 2m(1,3,4,6,12,14)

Using the Kamaugh map method obtain an optimal NOR gate implementation.
(6 Marks)

QUESTION 2:
A(a).
combinational logic circuit accepts the 3-bit Gray code: G2G1Go Design a decoder
based circuit that can give a binary code output B2B1Bo on a 3-bit bus. Assume that
the input sequence is available on a 3-bit wide bus (6 Marks)

(b).
It is required to determine whether a 4-bit binary sequence dad2dido has a magnitude
less than 1001 but greater than 0111. Use 4-bit magnitude comparators to implement
a suitable circuit that a gives a logic 1 on an output line Y if the binary sequence is

within this range. (6 Marks)

(c).
A combinational logic circuit is given in Fig Q2(c). The logic inputs are A, B and C and
the output is Y. Analyse the circuit and show how it could be implemented using an
INV-AND-OR configuration. Assume that A is the MSB and C the LSB. The 0'
optimal
bit line is also the ground. (8 Marks)

C O 8x1
MUX

S2S1 So

A B

Fig Q2(c)

2
QUESTION 3:
(a). Give the Excitation table and the State equation of an SR flip-flop. (4 Marks)

(b). A modulo-5 Ripple counter is to be implemented with T flip-lops. Give a suitable


circuit.( 6 Marks)

(c).AD flip-flop circuit is shown in Figa3(c). Determine the period of the output voltage
at Q if the clock speed is 100Hz.(2 MarksS).

D a

ck

Fig Q3(c)
(d).
A digital system is illustrated in Fig Q3(d). It consists of T flip-flops with a master clock
ck and other logic components. The input x controls the process as an external input.
All components can be assumed to be ideal. Obtain the state diagram of the circuit (8
Marks)
X

TT Q1

T-FF

A B

FA Cin

Cout
Qo

Ck T-FF

Fig Q3(d)

3
QUESTION 4: The output
as shown in Fig Q4(a).
of two 4-bit counters
consists usual order of
(a). A digital system the subscripts represent the
Q7QsQsQ4Q3Q2Q1Qo where
sequence is
significance.

Q Q Q1 Qo
Qs Qs Q

CTR DIV 16 ck
CTR DIV 16

Fig Q4(a)
of a clock pulse is 3A Hex. If the clock frequency
The initial count before the application overflow. Give your
counter take to register the first
is 256Hz, how long does the entire
answer in msec ( 8 Marks)

show how a 3-bit Johnson counter could


be implemented.
(b). Using only JK flip-flops,
Give the state diagram.(6 Marks)

data in a feedback
(c).Two 4-bit serial input/serial output shift registers accepts
BHex in Reg A and
network as shown in Fig Q4(c). The initial data in the registers are:
Y for 7 clock pulses.
CHex in Reg B. Analyse the circuit and give the output sequence
(6 Marks)

SI SO
Reg A

INV Y
ck
SI Reg B
XNOR
SO

Fig Q4(c)

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