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Module Instantiation and Test Benches: - Professor

This document discusses module instantiation and test benches in Verilog. It defines a module as the fundamental descriptive unit, with a port list specifying its interface. A test bench provides stimulus to a design for simulation, instantiating the model and declaring its inputs and outputs. The document provides examples of a module declaration for a sample circuit and a test bench to simulate it, applying inputs over time and monitoring the output waveform.

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Kayecilyn Malabanan
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115 views

Module Instantiation and Test Benches: - Professor

This document discusses module instantiation and test benches in Verilog. It defines a module as the fundamental descriptive unit, with a port list specifying its interface. A test bench provides stimulus to a design for simulation, instantiating the model and declaring its inputs and outputs. The document provides examples of a module declaration for a sample circuit and a test bench to simulate it, applying inputs over time and monitoring the output waveform.

Uploaded by

Kayecilyn Malabanan
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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MODULE INSTANTIATION AND

TEST BENCHES

NAME:
STUDENT NUMBER:
DATE OF SUBMISSION:

__________________
PROFESSOR

I. DISCUSSION
A hardware description language (HDL) is a computer-based language that
describes the hardware of digital systems in a textual form. It resembles an
ordinary computer programming language, such as C, but is specifically oriented
to describing hardware structures and behaviour of logic circuits.

HDLs are used in several major steps in the design flow of an integrated
circuit:
 design entry,
 functional simulation or verification,
 logic synthesis,
 timing verification,
 fault simulation.

Companies that design integrated circuits use proprietary and public HDLs.
In the public domain, there are two standard HDLs that are supported by the IEEE:
VHDL and Verilog.

VHDL
 stands for VHSIC (very high speed integrated circuit) HDL
 a Department of Defense mandated language

Verilog
 began as a proprietary of companies and universities known as Open
Verilog International (OVI) as a step leading to its adoption as an IEEE
standard.
 It was initially approved as a standard HDL in 1995; revised and enhanced
versions of the language were approved in 2001 and 2005.

Throughout this course, the Verilog HDL descriptions will be listed to


introduce a design methodology based on the concept of computer-aided
modelling of digital systems.

Module Declaration

In particular, a Verilog model is composed of text using keywords, of which


there are about 100. Keywords are predefined lowercase identifiers that define
the language constructs. Any text following the two forward slashes is interpreted
as a comment and will have no effect on a simulation using the model. Multiline
comments begin with /* and terminate with */. Blank spaces are ignored, but
they may not appear within the text of a keyword, an identifier, an operator, or
the representation of a number. Verilog is case-sensitive, which means that the
uppercase and lowercase letters are distinguishable.

A module is the fundamental descriptive unit in the Verilog language. It is


declared by the keyword module and must always be terminated by the keyword
endmodule.

module module_name (port list);


//Verilog statements
endmodule

The port list of a module is the interface between the module and its
environment. This list is enclosed in parentheses, and commas are used to
separate elements of the list. The statement is terminated with a semicolon (;).
The keywords input and output specify which of the ports are inputs and which
are outputs. Internal connections are declared as wires. This connection is
declared with the keyword wire.
input in1;
output out1, out2;
wire x, y, z;

Test Benches
In order to simulate a circuit with an HDL, it is necessary to apply inputs to
the circuit so that the simulator will generate an output response. An HDL
description that provides the stimulus to a design is called a test bench. In its
simplest form, a test bench is a module containing a single generator and an
instantiation of the model that is to be verified. Note that it has no input or
output ports, because it does not interact with its environment. Within the test
bench, the inputs to the circuit are declared with keyword reg and the outputs
are declared with the keyword wire. Note that using a test bench is similar to
testing actual hardware by attaching signal generators to the inputs of a circuit
and attaching probes (wires) to the outputs of the circuit).
reg a, b, c;
wire w1, w2;
The initial keyword is used with a set of statements that begin executing
when the simulation is initialized, and terminates execution when the last
statement has finished executing. The set of statements to be executed is called a
block statement and consists of several statements enclosed by keywords begin
and end. The action specified by the statements begins when the simulation is
launched, and the statements are executed in sequence.

The response to the stimulus generated by the initial and always blocks will
appear in text format as standard output and as waveforms (timing diagrams) in
simulators having graphical output capability. Numerical outputs are displayed by
using Verilog system tasks. These are built-in system functions that are recognized
by keywords that begin with the symbol $. Some of the system tasks that are
useful for display are:

$display – display a one-time value of variables or strings with an end-of-


line return,
$write – same as $display, but without going to next line,
$monitor – display variables whenever a value changes during a simulation
run,
$time – display the simulation time,
$finish – terminate the simulation.

The syntax is of the form:

Task_name(format specification, argument list);

The format specification uses the symbol % to specify radix of numbers that
are to be displayed and may have a string enclosed in quotes. The base may be
binary (%b), decimal (%d), and hexadecimal (%h).

II. Drill Exercises

A. Module Declaration

The HDL description of the circuit of the Fig 1.1 is shown in the example below.
Open your ModelSim and place the code inside. Save the file as Drill1_1.v.
A B C

wire1

EOR2 wire3

AND2
X
NOR2
wire2

NOT
Fig 1.1

//Verilog model of circuit of Fig 1.1


module circuit1_1(A, B, C, X);

input A, B, C;
output X;
wire wire1, wire2, wire3;

not NOT(wire2, A);


xor EOR2(wire1, B, C);
and AND2(wire3, wire1, A);
nor NOR2(X, wire3, wire2);

endmodule

B. Test Bench
Edit the saved file Drill1_1 by placing the following code below the previous code.
//Test bench for the Verilog model of Fig 1.1
module testbench1_1;

reg A, B, C;
wire Z;
circuit1_1 tb1(A, B, C, Z);
initial
begin
A=1’b0; B=1’b0; C=1’b0;
$display(“Simulating output for circuit1_1”);
$monitor($time,,,”A=%b B=%b C=%b Z=%b”,A,B,C,Z);
#2 A=1’b0; B=1’b0; C=1’b1;
#1 A=1’b0; B=1’b1; C=1’b0;
#1 A=1’b0; B=1’b1; C=1’b1;
#1 A=1’b1; B=1’b0; C=1’b0;
#1 A=1’b1; B=1’b0; C=1’b1;
#1 A=1’b1; B=1’b1; C=1’b0;
#1 A=1’b1; B=1’b1; C=1’b1;
#2 $finish;
end
endmodule

Compile your code and then run.

Display the waveform.


Output Waveform of Drill1_1:

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