dsPICQEI 033005
dsPICQEI 033005
DS
Digital Signal Controller
© 2005 Microchip Technology Incorporated. All Rights Reserved. dsPIC30F Quadrature Encoder Interface Module 1
Session Agenda
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These are the main topics we will address during this seminar.
First of all, we will see the purpose of the QEI module is. Then we will go
through all the main functional blocks, the digital noise filters, the decoder, and
the position counter. Finally we will see that this peripheral, if not used as an
encoder, can behave as an up/down counter/timer.
light source
slotted wheel
sensing device
logic
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The quadrature decoder, which is part of the interface circuitry, will read these
signals and converts them into a numeric count of the position pulses. The
count will increment when the shaft is rotating in one direction and will
decrement when the rotation is reversed.
O QEI Features
O QEI decodes signals and accumulates count
O Logically swap A and B inputs
O Programmable noise filters on inputs
O x2 and x4 counting modes
O 16-bit Position count register
O Reset on index pulse (if enabled)
O Reset on rollover/underflow
The QEI will perform all the operations needed to effectively use the information
coming from the encoder.
Since these signals are heavily affected by noise, a digital filter is available on
each input. The filtered phase edges are counted by a dedicated 16 bit up/down
counter, also referred to as the Position Counter. To establish a reference point
for position and speed measurements, the counter can be reset either by the
index signal or by a counter period match. The hardware can also perform
some error checking on on the accumulated count.
Block Diagram
Clock Tcy
Divider
INDEX Digital Filter
Logic
TQCS
Max. Count
UPDN
Register
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This block diagram depicts the internal architecture of the QEI modules. We
can see the input pins and the associated digital filters. There is also an
up/down input pin that is mainly used when the unit operates as a counter. The
quadratrute decoder logic is responsible for analysing which edge comes first
and the counter accumulates the edge count and is compared with the internal
Max Count Register.
Digital Filters
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The digital filters are responsible for rejecting noise from the three inputs. The
instruction cycle clock can be divided down by 2 , 4, 16, 32, 64, 128, 256 before
being used in the filter. The lower the clock frequency the lower frequencies are
rejected by the filter.
The prescaled clock is used to sample the input signal: if and only if three
consecutive samples have the same value the input is considered stable and
the value is output from the filter. One of the effects of this sampling is an
added latency, because there is a “propagation delay” of the input signal
through the filter.
Digital Filters
TCY
QEA/B
Filter
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Here we can see that the input signal at the QEA or QEB pin is sampled using
the selected clock, in this case the instruction cycle period Tcy. If at least three
samples having the same value are detected the output is updated, otherwise
the input signal changes are disregarded. Glitches and spikes can be efficiently
filtered out by the digital filters.
Quadrature Decoder
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As we have already seen, the quadrature decoder must determine the direction
of rotation looking at the two incoming phase signals, and generate the clock
that will be used by the position counter.
We can select between two modes: in the first one (x2) the decoder only
generates a clock impulse at the rising and falling edges of Phase A signal; in
the other mode (x4), the clock pulses are generate at each edge of phase A
and Phase B. The position counter can be reset either by the index pulse
coming from the encoder or by the matching of the current position counter
value with the number in the Maximum Count Register.
Timing Diagram
PHASE A
PHASE B
COUNT +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
UPDN
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This is an example of how the decoder works. We are using the x4 mode,
where the clock pulse is at each edge of both phases. In the first part of the
timing diagram Phase A leads Phase B, so that the counter is counting up.
Then, in the second half, the rotation of the rotor is reversed, Phase B now
leads Phase A and the counter is counting down. This is why an up/down
counter is required in this application.
The count direction can be determined by reading the UPDN bit in the QEI
control register, but the UPDN pin can also be used to indicate the count
direction status.
With the x4 mode we can get a very high angular resolution, but we also get a
relatively high output clock frequency. With the x2 mode, the resolution is twice
as fine, but the frequncy is lower.
The maximum allowed quadrature frequency is one-third of the instruction cycle
frequency Fcy.
Position Counter
O Up/down counter
O Counts pulses generated by the decoder
O Count is accumulated in POSCNT register
O POSCNT can be accessed, both for read
and write
O Its value can be compared to MAXCNT
register
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The position counter can be used either for position or speed measurement.
To measure motor position, we must know the relationship between the
displacement and the number of phase pulses we get from the encoder. This
relation can be known in advance, or can be measured during initialization by
accumulating the total count for the maximum allowed displacement. We can
set a constant value in the Maximum Count register, which is typically the
number of pulse edges generated by one encoder revolution. As soon as we
have a match between the Position Count and the Maximum Count, an interrupt
is generated. In the Interrupt Service Routine, the user software can increment
or decrerment a software counter containing the most significant bits of the
position count.
For speed measurement application, the time interval between two index pulses
or count match events gives a measure of the angular velocity.
© 2005 Microchip Technology Incorporated. All Rights Reserved. dsPIC30F Quadrature Encoder Interface Module 12
If the quadrature decoder functionality is not needed, the QEI peripheral module
can be configured as an additional 16 bit counter/timer.
In this mode, the Position Counter register has the same functionality as the
Timer registers in general-purpose timers, while the Maximum Count register
serves as a period register. An additional feature compared to the general-
purpose timers is that the QEI counter is able to both increment and decrement
its count, thus providing up-down counter functionality.
The timer clock can be either internal or external; in the latter case the input pin
is the QEA pin and the input clock, after digital filtering, will be synchronized
with the instruction cycle. As in the general-purpose timers, gated time
accumulation is also possible.
The counting direction can be selected either with the UPDN bit in register
QEICON, or with the QEB pin.
An interrupt is generated when the value in the Position Counter register
maches the value in the Maximum Count register.
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For more information, here are references to some important documents that
contain a lot of information about the dsPIC30F family of devices.
The Family Reference Manual contains detailed information about the
architecture and peripherals, whereas the Programmer’s Reference Manual
contains a thorough description of the instruction set.
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Related Material
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We also have some application notes on motor control, in which the peripheral
is used.
All these documents can be obtained from the Microchip web site, by clicking
on the “dsPIC® Digital Signal Controllers” or “Technical Documentation” link.
This wraps up the seminar on dsPIC30F QEI. Thank you for your interest in the
dsPIC30F Family of Digital Signal Controllers.