PH 401
PH 401
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Why does no engineering below nm scale?
14nm technology was first introduced by Intel as a successor to their earlier 22nm
technology. This technology further advances the scaling of transistors in
accordance with Moore's Law. The value 14nm does not actually represent the size
of the transistor but the fabrication technology used to manufacture them. Eariler the
gate pitch of the transistor was same as its fabrication value but this has changed
now. The 14nm technolgy has 42nm pitch size and more transistor density. The fin
sizes of the FinFET tranistors fins are thinner taller and fewer in number (per
transistor) as compared to the earlier 22nm technology. Hence, 14nm technology is
more advanced as it accomodates more transistors in a smaller space, thus
increasing the performance and power efficiency.
What are the challenges the industries face to handle the 14nm technology?
1. Additional design constraints and new sources of variability associated with the
non-planar transistor structure.
2. Computational lithography and the need for double patterning at the 14nm node
will drive up the complexity and difficulty of the physical design implementation,
pushing designs towards more uniform and regular structures instead of customized
ones.
3. The tradeoff for that is that wafer costs continue to rise from generation to
generation, as double patterning requires additional time and ever-finer tools that
drive up the cost of production. The end result is that while Intel’s cost per transistor
is not decreasing as quickly as the area per transistor, the cost is still decreasing and
significantly so.
We can, but the extent to which we can is very less and gets saturated very soon.
This is because: -
1. Complex machinery and high costs are involed in manufacturing and patterning.
Also, the scope for error is very less, making the production very difficult.
2. The technology may not be cost-effective for the customers and hence they may
not buy it.
Moore's law has saturated today's world and is no longer very meaningful. This is
because the industry has reached its zenith of scaling down "nodes"/ transistors to
upto 5nm level. Going beyond this means that we will near the size of a single Silicon
atom which cannot server as a transistor. Since, beyond a point we cannot scale
down transistors, Moore's law fails.
2.)
What will be the thickness of MgF2 on spectacle glass for appearing it as yellow
(λ=5893 Å)?
If constructive interference occurs at the wavelength 5893 Å, then the spectacle
glass will appear as yellow in colour.
nair = 1, nf = 1.4 and nglass = 1.5
As nair < nf < nglass, constructive interference will occur if, 2nfd = mλ (d is thickness of
the film)
Where m = 1,2,3,....
So, possible thicknesses for the film are 0.21 µm, 0.42 µm, 0.63 µm, 0.84 µm....
Explain the principle of the pulse laser deposition (PLD)/thermal evaporation system.
Thermal Evaporation:
Thermal Evaporation consists of evaporating solid metal or other material samples
under high vacuum (10–6 torr or 1.3 × 10-4 Pa) and condensing them to form thin
films. It is also called vacuum deposition. Heat is produced by electrical resistance.
If nanoclusters are formed during the evaporation process, it is top down. If atoms or
molecules are formed during the evaporation process that recombine to form a thin
layer without any chemical reaction, it is a crossover technique.
Which technique will be better to get a high-quality view (explain and justify your
answer).
Pulse Layer Deposition (PLD) technique will be better to get a high-quality view
because:
● The laser induced expulsion in PLD produces a film with the same
stoichiometry as the target, especially in the case of multi-element materials.
But in Thermal Evaporation, the stoichiometry is greatly influenced by the
vapour pressures of elements in the target material.
● We have control over the film growth rate. It is a versatile method.
● It has a fast deposition rate and is cost effective, clean, scalable. It is
compatible with oxygen and other inert gases.
3.)
Macro grain: The grain size or shape is visible to an naked eye
Micro grain : The grain size is very small and only visible using a microscope after
etching
What is/are the differences between Macro and Micro grains? What is the
importance of micro-grain in nanoscience and technology?
Differences:
• To view micro grains several process like polishing, etching has to be carried out
Importance of microstructure:
. With the help of microstructure of various metals we can find the change the
physical properties like strength, hardness, ductility, etc..
Hot press will have more strength because after the milling the hot press will make
the grains smaller and strain hardening will occur due to which it can carry more
stress. Whereas in casting the grains formed will be larger and hence the strength
will also be less.
5)
Surface area to volume ratio in nanoparticles have a significant effect on their properties. We observe
that nanomaterials have a relatively larger surface area when compared to the volume of the same
material. Within nanomaterials we can see that lesser the size, the higher is the surface to volume
ratio. For a single shell nanomaterial 92% of the atoms are surface atoms. This has a huge impact on
the different properties of the nanomaterials. Due to the presence of more atoms on the surface,
nanomaterials are more chemically active as they have more surface electrons. This phenomenon is
particularly useful in applications of nanomaterials in chemical catalytic reactions where surface area
of contact is very important.
Group A: We can see 4 atoms of type A in this figure. We have 6 such sides in a cube and each atom
of type A is shared by 3 edges. Hence, we will have a total of (4/3)*6 = 8 atoms.
Group B: There are 8 atoms of group B in this figure. These 8 atoms are shared among two faces and
there are 6 faces in a cube. So we have total number of atom count = (8/2)*6 = 24. We have these
atoms at the intersection of the middle lines with the edges. Each edge has n-1 middle lines.
Multiplying by the number of edges we have 12(n-1)
Group C: In case of 3 layers, we can see that we will have 4*6=24 Group C atoms (since there are 4 on
every face and there are 6 faces). Generalizing this concept, we see that C atoms occur (n-1)^2 times
i.e. the number of times of intersection of the middle lines. Considering 6 faces we have total C atoms
= 6(n-1)^2
Hence, total surface atoms = 8+12(n-1)+6(n-1)^2 = 6n^2+2
We will have only atoms of type A in the bulk atoms. We see that there are 4 atoms for n=3 case.
Generalizing we will have (n-1)^2 atoms as these atoms are on the intersection of the middle lines
(which are (n-1) in number). Since, (n-1) such layers are possible, the total number of atoms of this
type is (n-1)^3.
Hence, the magic number for SCC = surface atoms + bulk atoms = 6n^2+2 + (n-1)^3.
Surface to volume ratio = 6n^2+2/(n-1)^3
<graph here>
6.)
Explain the steps of the Lithography (visible/Ultraviolate/X-ray/Electron)
method for making nanodevices.
Nanolithography is the branch of nanotechnology concerned with the study and application of the
nanofabrication of nanometer-scale structures, meaning nanopatterning with at least one lateral
dimension between the size of an individual atom and approximately 100 nm. The term
nanolithography is derived from the Greek words “nanos”, meaning dwarf; “lithos”, meaning rock or
stone; and “graphein” meaning to write. Therefore the literal translation is "tiny writing on stone",
however nowadays one understands something different whenever this term is associated with
nanotechnology. Nanolithography is used e.g. during the nanofabrication of leading-edge
semiconductor integrated circuits (nanocircuitry), for nanoelectromechanical systems (NEMS) or for
almost any other fundamental application across various scientific disciplines in nanoresearch.
There are many techniques through which micro/nanopatterning could be possible. They are:
● Photolithography
● X-ray lithography
● Electron beam lithography
● Ultra violate lithography
Steps involved:
For lithography processing, a hard copy of the pattern has to be first generated. This is called a reticle
or mask. The design on the mask has to be transferred to the wafer, as shown in figure 1. The transfer
can be 1:1 (i.e. with no reduction in size) but usually the size is reduced so that the pattern is
transferred to a smaller region on the wafer. This is done by using suitable lens to demagnify the
pattern. Lithography can be broadly divided into two stages, each of which consists of several steps.
1. First, the pattern is transferred to a photoresist layer on the wafer. Photoresist is a light sensitive
material whose properties change on exposure to light of specified wavelength. This process is called
developing. The pattern formed in this step is temporary and can be removed easily. This is especially
important if the pattern is not properly alignment with the wafer or with any existing patterns on the
wafer, improper registry. 2. The transfer of the pattern takes place from the photoresist to the wafer.
Exposed wafer surfaces can be etched (removal of material) or layers deposited on it. Dopant
materials can also be added to sections of the wafer through the pattern. This stage is final and it is
very hard to remove the formed patterns without causing damage to the underlying wafer. The overall
lithography process is summarized in figure 2. After the pattern is formed on the photoresist and the
wafer surface is exposed (developing process) the exposed wafer surface is etched. It is also possible
to deposit material on the exposed surface.
How does it differ from the nanoimprint method?
Disadvantages:
Not an efficient process for industrial processing
Takes multiple hours to pattern the entire wafer
Machines are costly
Greater than 5 million dollars
The system is more complex than a photolithography system
Scattering and overexposure result in the minimum feature being larger
Slow throughput