19-0196; Rev 0; 10/93

NUAL
KIT MA
ATION SHEET
EVALU D A T A
WS
FOLLO +5V, Low-Power, 12-Bit Serial ADCs

__________________General Description ________________________________Features

MAX187/MAX189
The MAX187/MAX189 serial 12-bit analog-to-digital ♦ 12-Bit Resolution
converters (ADCs) operate from a single +5V supply ♦ ±1⁄2 LSB Integral Nonlinearity (MAX187A/MAX189A)
and accept a 0V to 5V analog input. Both parts feature
♦ Internal Track/Hold, 75kHz Sampling Rate
an 8.5µs successive-approximation ADC, a fast
track/hold (1.5µs), an on-chip clock, and a high-speed ♦ Single +5V Operation
3-wire serial interface. ♦ Low Power: 2µA Shutdown Current
The MAX187/MAX189 digitize signals at a 75ksps 1.5mA Operating Current
throughput rate. An external clock accesses data from ♦ Internal 4.096V Buffered Reference (MAX187)
the interface, which communicates without external ♦ 3-Wire Serial Interface, Compatible with SPI,
hardware to most digital signal processors and micro- QSPI, and Microwire
controllers. The interface is compatible with SPI™,
♦ Small-Footprint 8-Pin DIP and 16-Pin SO
QSPI™, and Microwire™.
The MAX187 has an on-chip buffered reference, and _________________Ordering Information
the MAX189 requires an external reference. Both the
MAX187 and MAX189 save space with 8-pin DIP and PART TEMP. RANGE PIN-PACKAGE ERROR
(LSB)
16-pin SO packages. Power consumption is 7.5mW
MAX187ACPA 0°C to +70°C 8 Plastic DIP ±1⁄2
and reduces to only 10µW in shutdown.
MAX187BCPA 0°C to +70°C 8 Plastic DIP ±1
Excellent AC characteristics and very low power con-
sumption combined with ease of use and small pack- MAX187CCPA 0°C to +70°C 8 Plastic DIP ±2
age size make these converters ideal for remote DSP MAX187ACWE 0°C to +70°C 16 Wide SO ±1⁄2
and sensor applications, or for circuits where power MAX187BCWE 0°C to +70°C 16 Wide SO ±1
consumption and space are crucial.
MAX187CCWE 0°C to +70°C 16 Wide SO ±2
___________________________Applications MAX187BC/D 0°C to +70°C Dice* ±1
Portable Data Logging Ordering Information continued on last page.
Remote Digital Signal Processing * Dice are specified at TA = +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
Isolated Data Acquisition
High-Accuracy Process Control
________________Functional Diagram _________________Pin Configurations

6 TOP VIEW
OUTPUT DOUT
5 SHIFT 8
GND REF- SCLK
REGISTER
AV = 1.638 DAC
10k (4.096V)
+2.5V V DD 1 8 SCLK
REF+
BANDGAP
REFERENCE AIN 2 7 CS
(MAX187 ONLY) 12-BIT
SHDN 3 MAX187
4 SAR MAX189 6 DOUT
REF
REF 4 5 GND
2
AIN T/H
COMPARATOR
7 DIP
MAX187 CS
MAX189 BUFFER ENABLE/DISABLE CONTROL
AND
1 TIMING 3
VDD SHDN

NOTE: PIN NUMBERS SHOWN ARE FOR 8-PIN DIPs ONLY. Pin Configurations continued on last page.

™ SPI and QSPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor.

________________________________________________________________ Maxim Integrated Products 1

Call toll free 1-800-998-8800 for free samples or literature.

 +5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189

ABSOLUTE MAXIMUM RATINGS

VDD to GND .............................................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C)
AIN to GND................................................-0.3V to (VDD + 0.3V) 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ..500mW
REF to GND ...............................................-0.3V to (VDD + 0.3V) 16-Pin Wide SO (derate 8.70mW/°C above +70°C) ...478mW
Digital Inputs to GND.................................-0.3V to (VDD + 0.3V) 8-Pin CERDIP (derate 8.00mW/°C above +70°C) ......440mW
Digital Outputs to GND..............................-0.3V to (VDD + 0.3V) Operating Temperature Ranges:
SHDN to GND.............................................-0.3V to (VDD + 0.3V) MAX187_C_ _/MAX189_C_ _.............................0°C to +70°C
REF Load Current (MAX187) .........................4.0mA Continuous MAX187_E_ _/MAX189_E_ _ ..........................-40°C to +85°C
REF Short-Circuit Duration (MAX187)................................20sec MAX187_MJA/MAX189_MJA .......................-55°C to +125°C
DOUT Current ..................................................................±20mA Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec) ............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal
reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF
capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 1)
Resolution 12 Bits
MAX18_A ±1⁄2
Relative Accuracy (Note 2) MAX18_B ±1 LSB
MAX18_C ±2
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB

Offset Error
MAX18_A ±1
1
⁄2 LSB
MAX18_B/C ±3
MAX187 ±3
Gain Error (Note 3) MAX189A ±1 LSB
MAX189B/C ±3
Gain Temperature Coefficient External reference, 4.096V ±0.8 ppm/°C
DYNAMIC SPECIFICATIONS (10kHz sine wave input, 0V to 4.096Vp-p, 75ksps)
Signal-to-Noise plus
Distortion Ratio SINAD 70 dB

Total Harmonic Distortion

(up to the 5th harmonic) THD -80 dB

Spurious-Free Dynamic Range SFDR 80 dB

Small-Signal Bandwidth Rolloff -3dB 4.5 MHz
Full-Power Bandwidth 0.8 MHz

2 _______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

ELECTRICAL CHARACTERISTICS (continued)

MAX187/MAX189
(VDD = +5V ±5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal
reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF
capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CONVERSION RATE
Conversion Time tCONV 5.5 8.5 µs
Track/Hold Acquisition Time tACQ 1.5 µs
Throughput Rate External clock, 4MHz, 13 clocks 75 ksps
Aperture Delay tAPR 10 ns
Aperture Jitter <50 ps
ANALOG INPUT
Input Voltage Range 0 to VREF V
Input Capacitance (Note 4) 16 pF
INTERNAL REFERENCE (MAX187 only, reference buffer enabled)
TA = +25°C 4.076 4.096 4.116

REF Output Voltage VREF MAX187_C 4.060 4.132

V
TA = TMIN to TMAX MAX187_E 4.050 4.140
MAX187_M 4.040 4.150
REF Short-Circuit Current 30 mA
MAX187AC/BC ±30 ±50
MAX187AE/BE ±30 ±60
REF Tempco ppm/°C
MAX187AM/BM ±30 ±80
MAX187C ±30
Load Regulation (Note 5) 0mA to 0.6mA output load 1 mV
EXTERNAL REFERENCE AT REF (Buffer disabled, VREF = 4.096V)
Input Voltage Range 2.50 VDD + 50mV V
Input Current 200 350 µA
Input Resistance 12 20 kΩ
Shutdown REF Input Current 1.5 10 µA

_______________________________________________________________________________________ 3
 +5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +5V ±5%; GND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal
reference: VREF = 4.096V, 4.7µF capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7µF
capacitor at REF pin; TA = TMIN to TMAX; unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS (SCLK, CS, SHDN)
SCLK, CS Input High Voltage VINH 2.4 V
SCLK, CS Input Low Voltage VINL 0.8 V
SCLK, CS Input Hysteresis VHYST 0.15 V
SCLK, CS Input Leakage IIN VIN = 0V or VDD ±1 µA
SCLK, CS Input Capacitance CIN (Note 4) 15 pF
SHDN Input High Voltage VINSH VDD - 0.5 V
SHDN Input Low Voltage VINSL 0.5 V
SHDN Input Current IINS SHDN = VDD or 0V ±4.0 µA
SHDN Input Mid Voltage VIM 1.5 VDD -1.5 V
SHDN Voltage, Floating VFLT SHDN = open 2.75 V
SHDN Maximum Allowed
Leakage, Mid Input SHDN = open -100 100 nA

DIGITAL OUTPUT (DOUT)

ISINK = 5mA 0.4
Output Voltage Low VOL V
ISINK = 16mA 0.3
Output Voltage High VOH ISOURCE = 1mA 4 V
Three-State Leakage Current IL CS = 5V ±10 µA
Three-State Output
Capacitance COUT CS = 5V (Note 4) 15 pF

POWER REQUIREMENTS
Supply Voltage VDD 4.75 5.25 V
MAX187 1.5 2.5
Operating mode mA
Supply Current IDD MAX189 1.0 2.0
Power-down mode 2 10 µA

VDD = +5V, ±5%; external reference, 4.096V;

Power-Supply Rejection PSR ±0.06 ±0.5 mV
full-scale input (Note 6)

4 _______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

MAX187/MAX189
TIMING CHARACTERISTICS
(VDD = +5.0V ±5%, TA = TMIN to TMAX, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Track/Hold Acquisition Time tACQ CS = high (Note 7) 1.5 µs
MAX18_ _C/E 20 150
SCLK Fall to Output Data Valid tDO CLOAD = 100pF ns
MAX18_ _M 20 200
CS Fall to Output Enable tDV CLOAD = 100pF 100 ns
CS Rise to Output Disable tTR CLOAD = 100pF 100 ns
SCLK Clock Frequency fSCLK 5 MHz
SCLK Pulse Width High tCH 100 ns
SCLK Pulse Width Low tCL 100 ns
SCLK Low to CS Fall tCSO 50 ns
Setup Time
CS Pulse Width tCS 500 ns

Note 1: Tested at VDD = +5V.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.

_______________________________________________________________________________________ 5
 +5V, Low-Power, 12-Bit Serial ADCs

________________________________________________Typical Operating Characteristics

MAX187/MAX189

POWER-SUPPLY REJECTION vs.

TEMPERATURE VREF vs. TEMPERATURE
0.16 4.090
4.089
0.14

INTERNAL REFERENCE VOLTAGE (V)

POWER-SUPPLY REJECTION (mV)

4.088
0.12 4.087
0.10 4.086

0.08 4.085
4.084
0.06
4.083
0.04
4.082
0.02 4.081
0 4.080

-60 -20 20 60 100 140 -60 -20 20 60 100 140

TEMPERATURE (°C) TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT vs.

SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE
7

2.2 6
SHUTDOWN SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)

1.8 5
MAX187
1.4 4

MAX189 3
1.0
2
0.6
1
0.2
0
-60 -20 20 60 100 140 -60 -20 20 60 100 140

TEMPERATURE (°C) TEMPERATURE (°C)

6 _______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

_______________________________________________________________________Pin Description

MAX187/MAX189
PIN
NAME FUNCTION
DIP WIDE SO
1 1 VDD Supply voltage, +5V ±5%
2 3 AIN Sampling analog input, 0V to VREF range
Three-level shutdown input. Pulling SHDN low shuts the MAX187/MAX189
down to 10µA (max) supply current. Both MAX187 and MAX189 are fully opera-
3 6 SHDN tional with either SHDN high or floating. For the MAX187, pulling SHDN high
enables the internal reference, and letting SHDN float disables the internal
reference and allows for the use of an external reference.
Reference voltage—sets analog voltage range and functions as a 4.096V output
for the MAX187 with enabled internal reference. REF also serves as a +2.5V to
4 8 REF VDD input for a precision reference for both MAX187 (disabled internal reference)
and MAX189. Bypass with 4.7µF if internal reference is used, and with 0.1µF if an
external reference is applied.
5 — GND Analog and digital ground
— 10 AGND Analog ground
— 11 DGND Digital ground
6 12 DOUT Serial data output. Data changes state at SCLK’s falling edge.
Active-low chip select initiates conversions on the falling edge. When CS is high,
7 15 CS
DOUT is high impedance.
8 16 SCLK Serial clock input. Clocks data out with rates up to 5MHz.
— 2,4,5,7,9,13,14 N.C. Not internally connected. Connect to AGND for best noise performance.

_______________Detailed Description unipolar serial format. A high bit, signaling the end of
conversion (EOC), followed by the data bits (MSB first),
Converter Operation make up the serial data stream.
The MAX187/MAX189 use input track/hold (T/H) and The MAX187 operates in one of two states: (1) internal
successive approximation register (SAR) circuitry to reference and (2) external reference. Select internal
convert an analog input signal to a digital 12-bit output. reference operation by forcing SHDN high, and external
No external hold capacitor is needed for the T/H. reference operation by floating SHDN.
Figures 3a and 3b show the MAX187/MAX189 in their
simplest configuration. The MAX187/MAX189 convert Analog Input
input signals in the 0V to VREF range in 10µs, including Figure 4 illustrates the sampling architecture of the
T/H acquisition time. The MAX187’s internal reference ADC’s analog comparator. The full-scale input voltage
is trimmed to 4.096V, while the MAX189 requires an depends on the voltage at REF.
external reference. Both devices accept external refer-
ence voltages from +2.5V to VDD. The serial interface ZERO FULL
REFERENCE
requires only three digital lines, SCLK, CS, and DOUT, SCALE SCALE
and provides easy interface to microprocessors (µPs). Internal Reference
0V +4.096V
Both converters have two modes: normal and shut- (MAX187 only)
down. Pulling SHDN low shuts the device down and External Reference 0V VREF
reduces supply current to below 10µA, while pulling
SHDN high or leaving it floating puts the device into the For specified accuracy, the external reference voltage
operational mode. A conversion is initiated by CS range spans from +2.5V to VDD.
falling. The conversion result is available at DOUT in

_______________________________________________________________________________________ 7
 +5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189

+5V

3k

DOUT DOUT

3k CLOAD = 100pF CLOAD = 100pF

DGND DGND

a. High-Z to VOH and VOL to VOH b. High-Z to VOL and VOH to VOL

Figure 1. Load Circuits for DOUT Enable Time

+5V

3k

DOUT DOUT

3k CLOAD = 100pF CLOAD = 100pF

DGND DGND

a. VOH to High-Z b. VOLto High-Z

Figure 2. Load Circuits for DOUT Disable Time

8 _______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

MAX187/MAX189
4.7µF 4.7µF

0.1µF 0.1µF

1 8 1 8
+5V VDD SCLK +5V VDD SCLK

2 7 SERIAL 2 7
ANALOG INPUT AIN MAX187 CS ANALOG INPUT AIN MAX189 CS
SERIAL
0V TO +5V INTERFACE 0V TO +5V INTERFACE
SHUTDOWN 3 6 SHUTDOWN 3 6
SHDN DOUT SHDN DOUT
INPUT INPUT
ON ON
OFF 4 5 OFF 4 5
REF GND REFERENCE REF GND
4.7µF INPUT
0.1µF

Figure 3a. MAX187 Operational Diagram Figure 3b. MAX189 Operational Diagram

interval. At this instant, the T/H switches the input side

of CHOLD to GND. The retained charge on CHOLD rep-
resents a sample of the input, unbalancing the node
12-BIT CAPACITIVE DAC ZERO at the comparator’s input.
REF In hold mode, the capacitive DAC adjusts during the
COMPARATOR remainder of the conversion cycle to restore node
AIN TRACK INPUT CHOLD ZERO ZERO to 0V within the limits of a 12-bit resolution. This
- + action is equivalent to transferring a charge from
16pF CHOLD to the binary-weighted capacitive DAC, which in
HOLD 5k
RIN
turn forms a digital representation of the analog input
CSWITCH
CPACKAGE signal. At the conversion’s end, the input side of CHOLD
HOLD
TRACK switches back to AIN, and CHOLD charges to the input
AT THE SAMPLING INSTANT, signal again.
THE INPUT SWITCHES FROM
AIN TO GND. The time required for the T/H to acquire an input signal
GND is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. Acquisition time
Figure 4. Equivalent Input Circuit is calculated by:
tACQ = 9 (RS + RIN) 16pF,
where RIN = 5kΩ, RS = the source impedance of the
Track/Hold
input signal, and tACQ is never less than 1.5µs. Source
In track mode, the analog signal is acquired and stored
impedances below 5kΩ do not significantly affect the
in the internal hold capacitor. In hold mode, the T/H
AC performance of the ADC.
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor CHOLD. Bringing CS low ends the acquisition

_______________________________________________________________________________________ 9
 +5V, Low-Power, 12-Bit Serial ADCs

Input Bandwidth ed by the 75ksps sample rate of the MAX187/MAX189.

MAX187/MAX189

The ADCs’ input tracking circuitry has a 4.5MHz small- Therefore, the maximum sinusoidal input frequency
signal bandwidth, and an 8V/µs slew rate. It is possible allowed is 37.5kHz. Higher-frequency signals cause
to digitize high-speed transient events and measure aliasing problems unless undersampling techniques
periodic signals with bandwidths exceeding the ADC's are used.
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into Reference
the frequency band of interest, an anti-alias filter is rec- The MAX187 can be used with an internal or external ref-
ommended. See the MAX274/MAX275 continuous-time erence, while the MAX189 requires an external reference.
filters data sheet. Internal Reference
Input Protection The MAX187 has an on-chip reference with a buffered
Internal protection diodes that clamp the analog input temperature-compensated bandgap diode, laser-
allow the input to swing from GND - 0.3V to VDD + 0.3V trimmed to +4.096V ±0.5%. Its output is connected to
without damage. However, for accurate conversions REF and also drives the internal DAC. The output can
near full scale, the input must not exceed VDD by more be used as a reference voltage source for other com-
than 50mV, or be lower than GND by 50mV. ponents and can source up to 0.6mA. Decouple REF
with a 4.7µF capacitor. The internal reference is
If the analog input exceeds the supplies by more than enabled by pulling the SHDN pin high. Letting SHDN
50mV beyond the supplies, limit the input current to float disables the internal reference, which allows the
2mA, since larger currents degrade conversion use of an external reference, as described in the
accuracy. External Reference section.
Driving the Analog Input External Reference
The input lines to AIN and GND should be kept as short The MAX189 operates with an external reference at the
as possible to minimize noise pickup. Shield longer REF pin. To use the MAX187 with an external reference,
leads. Also see the Input Protection section. disable the internal reference by letting SHDN float. Stay
Because the MAX187/MAX189 incorporate a T/H, the within the voltage range +2.5V to VDD to achieve speci-
drive requirements of the op amp driving AIN are less fied accuracy. The minimum input impedance is 12kΩ
stringent than those for a successive-approximation for DC currents. During conversion, the external refer-
ADC without a T/H. The typical input capacitance is ence must be able to deliver up to 350µA DC load cur-
16pF. The amplifier bandwidth should be sufficient to rent and have an output impedance of 10Ω or less. The
handle the frequency of the input signal. The MAX400 recommended minimum value for the bypass capacitor
and OP07 work well at lower frequencies. For higher- is 0.1µF. If the reference has higher output impedance
frequency operation, the MAX427 and OP27 are practi- or is noisy, bypass it close to the REF pin with a 4.7µF
cal choices. The allowed input frequency range is limit- capacitor.

COMPLETE CONVERSION SEQUENCE

CS

tWAKE
SHDN

DOUT

CONVERSION 0 CONVERSION 1

POWERED UP POWERED DOWN POWERED UP

Figure 5. MAX187/MAX189 Shutdown Sequence

10 ______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

MAX187/MAX189
10000 3.0

2.5
1000
SUPPLY CURRENT (µA)

MAX187 2.0

tWAKE (ms)
100 1.5

MAX189* 1.0
10
0.5

*REF CONNECTED TO VDD

1 0
0.1 1 10 100 1000 10000 100000 0.0001 0.001 0.01 0.1 1 10

CONVERSIONS PER SECOND TIME IN SHUTDOWN (sec)

Figure 6. Average Supply Current vs. Conversion Rate Figure 7. tWAKE vs. Time in Shutdown (MAX187 only)

____________________Serial Interface External Clock

The actual conversion does not require the external
Initialization After Power-Up and clock. This frees the µP from the burden of running the
Starting a Conversion SAR conversion clock, and allows the conversion result
When power is first applied, it takes the fully dis- to be read back at the µP’s convenience at any clock
charged 4.7µF reference bypass capacitor up to 20ms rate from 0MHz to 5MHz. The clock duty cycle is unre-
to provide adequate charge for specified accuracy. stricted if each clock phase is at least 100ns. Do not
With SHDN not pulled low, the MAX187/MAX189 are run the clock while a conversion is in progress.
now ready to convert.
Timing and Control
To start a conversion, pull CS low. At CS’s falling edge,
Conversion-start and data-read operations are con-
the T/H enters its hold mode and a conversion is initiat-
trolled by the CS and SCLK digital inputs. The timing
ed. After an internally timed 8.5µs conversion period,
diagrams of Figures 8 and 9 outline the operation of the
the end of conversion is signaled by DOUT pulling
serial interface.
high. Data can then be shifted out serially with the
external clock. A CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to con-
Using SHDN to Reduce Supply Current vert, and DOUT changes from high impedance to logic
Power consumption can be reduced significantly by low. SCLK must be kept inactive during the conversion.
shutting down the MAX187/MAX189 between conver- An internal register stores the data when the conversion
sions. This is shown in Figure 6, a plot of average sup- is in progress.
ply current vs. conversion rate. Because the MAX189 End of conversion (EOC) is signaled by DOUT going
uses an external reference voltage (assumed to be pre- high. DOUT’s rising edge can be used as a framing
sent continuously), it "wakes up" from shutdown more signal. SCLK shifts the data out of this register any time
quickly, and therefore provides lower average supply after the conversion is complete. DOUT transitions on
currents. The wakeup-time, tWAKE, is the time from SCLK’s falling edge. The next falling clock edge pro-
SHDN deasserted to the time when a conversion may duces the MSB of the conversion at DOUT, followed by
be initiated. For the MAX187, this time is 2µs. For the the remaining bits. Since there are 12 data bits and one
MAX189, this time depends on the time in shutdown leading high bit, at least 13 falling clock edges are
(see Figure 7) because the external 4.7µF reference needed to shift out these bits. Extra clock pulses occur-
bypass capacitor loses charge slowly during shutdown ring after the conversion result has been clocked out,
(see the specifications for shutdown, REF Input Current and prior to a rising edge of CS, produce trailing 0s at
= 10µA max). DOUT and have no effect on converter operation.

______________________________________________________________________________________ 11
 +5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189

CS

1 4 8 12
SCLK

DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

EOC
CONVERSION TRAILING
INTERFACE IDLE EOC CLOCK OUTPUT DATA IDLE
IN PROGRESS ZEROS

CONVERSION
A/D TRACK TRACK CONV. 1
0
STATE

0.5µs
8.5µs (tCONV) 0µs 12 × 0.250µs = 3.25µs 0µs
MINIMUM (tCS)
CYCLE TIME
TOTAL = 12.25µs

Figure 8. MAX187/MAX189 Interface Timing Sequence

tCS
CS

…
tCS0
tCH

…
SCLK
tDO
tCL
tTR
tCONV
tDV

DOUT … B2 B1 B0

tAPR

INTERNAL (TRACK) (HOLD)

… (TRACK)
T/H

Figure 9. MAX187/MAX189 Detailed Serial-Interface Timing

12 ______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

MAX187/MAX189
20

OUTPUT CODE fS = 75ksps

FULL-SCALE 0
fT = 10kHz
TRANSITION TA = +25°C
11…111
11…110 -20

11…101

AMPLITUDE (dB)
-40

FS = +4.096V -60

1LSB = FS
4096
-80

00…011
-100
00…010
00…001
-120
00…000
0 1 2 3 FS
-140
INPUT VOLTAGE (LSBs) FS - 3/2LSB 0 18.75 37.5
FREQUENCY (kHz)

Figure 10. MAX187/MAX189 Unipolar Transfer Function, Figure 11. MAX187/MAX189 FFT plot
4.096V = Full Scale
Minimum cycle time is accomplished by using DOUT’s input frequency. ADCs have traditionally been evaluat-
rising edge as the EOC signal. Clock out the data with ed by specifications such as Zero and Full-Scale Error,
13 clock cycles at full speed. Raise CS after the conver- Integral Nonlinearity (INL), and Differential Nonlinearity
sion’s LSB has been read. After the specified minimum (DNL). Such parameters are widely accepted for speci-
time, tACQ, CS can be pulled low again to initiate the fying performance with DC and slowly varying signals,
next conversion. but are less useful in signal-processing applications,
where the ADC’s impact on the system transfer function
Output Coding and Transfer Function is the main concern. The significance of various DC
The data output from the MAX187/MAX189 is binary, errors does not translate well to the dynamic case, so
and Figure 10 depicts the nominal transfer function. different tests are required.
Code transitions occur halfway between successive
integer LSB values. If V REF = +4.096V, then Signal-to-Noise Ratio and
1 LSB = 1.00mV or 4.096V/4096. Effective Number of Bits
Signal-to-noise plus distortion (SINAD) is the ratio of the
_____________Dynamic Performance fundamental input frequency’s RMS amplitude to the
High-speed sampling capability and a 75ksps through- RMS amplitude of all other ADC output signals. The
put make the MAX187/MAX189 ideal for wideband sig- input bandwidth is limited to frequencies above DC and
nal processing. To support these and other related below one-half the ADC sample (conversion) rate.
applications, Fast Fourier Transform (FFT) test tech- The theoretical minimum ADC noise is caused by quan-
niques are used to guarantee the ADC’s dynamic fre- tization error and is a direct result of the ADC’s resolu-
quency response, distortion, and noise at the rated tion: SINAD = (6.02N + 1.76)dB, where N is the number
throughput. Specifically, this involves applying a low- of bits of resolution. An ideal 12-bit ADC can, therefore,
distortion sine wave to the ADC input and recording the do no better than 74dB. An FFT plot of the output
digital conversion results for a specified time. The data shows the output level in various spectral bands. Figure
is then analyzed using an FFT algorithm that deter- 11 shows the result of sampling a pure 10kHz sine
mines its spectral content. Conversion errors are then wave at a 75ksps rate with the MAX187/MAX189.
seen as spectral elements outside of the fundamental

______________________________________________________________________________________ 13
 +5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189

12.2
12.0
11.8 I/O CS

11.6 SCK SCLK

11.4
MISO DOUT
EFFECTIVE BITS

11.2
+5V
11.0
10.8 MAX187
MAX189
10.6 SS
10.4
(UNDERSAMPLED)
10.2
a. SPI
1 10 100 1000

INPUT FREQUENCY (kHz) CS CS

SCK SCLK
Figure 12. Effective Bits vs. Input Frequency
MISO DOUT
+5V

MAX187
The effective resolution (effective number of bits) the
MAX189
ADC provides can be determined by transposing the SS
above equation and substituting in the measured
SINAD: N = (SINAD - 1.76)/6.02. Figure 12 shows the
effective number of bits as a function of the input fre- b. QSPI
quency for the MAX187/MAX189.
Total Harmonic Distortion I/O CS
If a pure sine wave is sampled by an ADC at greater SK SCLK
than the Nyquist frequency, the nonlinearities in the
ADC’s transfer function create harmonics of the input SI DOUT
frequency present in the sampled output data.
Total Harmonic Distortion (THD) is the ratio of the RMS
MAX187
sum of all the harmonics (in the frequency band above
MAX189
DC and below one-half the sample rate, but not includ-
ing the DC component) to the RMS amplitude of the
fundamental frequency. This is expressed as follows:
c. MICROWIRE
√ V22 + V32 + V42 + … VN2
THD = 20log
V1
Figure 13. Common Serial-Interface Connections to the
where V1 is the fundamental RMS amplitude, and V2
MAX187/MAX189
through VN are the amplitudes of the 2nd through Nth
harmonics. The THD specification in the Electrical
Characteristics includes the 2nd through 5th
harmonics.

14 ______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

MAX187/MAX189
____________Applications Information SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK to DOUT valid timing charac-
Connection to Standard Interfaces teristic. Data can be clocked into the µP on SCLK’s
The MAX187/MAX189 serial interface is fully compatible rising edge.
with SPI, QSPI, and Microwire standard serial 4. Pull CS high at or after the 13th falling clock edge. If
interfaces. CS remains low, trailing zeros are clocked out after
If a serial interface is available, set the CPU’s serial the LSB.
interface in master mode so the CPU generates the ser- 5. With CS = high, wait the minimum specified time, tCS,
ial clock. Choose a clock frequency up to 2.5MHz. before launching a new conversion by pulling CS
1. Use a general-purpose I/O line on the CPU to pull CS low. If a conversion is aborted by pulling CS high
low. Keep SCLK low. before the conversions end, wait for the minimum
2. Wait the for the maximum conversion time specified acquisition time, t ACQ , before starting a new
before activating SCLK. Alternatively, look for a conversion.
DOUT rising edge to determine the end of
Data can be output in 1-byte chunks or continuously, as
conversion.
shown in Figure 8. The bytes will contain the result of
3. Activate SCLK for a minimum of 13 clock cycles. The the conversion padded with one leading 1, and trailing
first falling clock edge will produce the MSB of the 0s if SCLK is still active with CS kept low.
DOUT conversion. DOUT output data transitions on

1ST BYTE READ 2ND BYTE READ

SCLK
CS
tCONV
HI-Z HI-Z
DOUT MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB

EOC

Figure 14. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)

SCLK
CS
tCONV
HI-Z HI-Z
DOUT MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB

EOC

Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)

______________________________________________________________________________________ 15
 +5V, Low-Power, 12-Bit Serial ADCs

SPI and Microwire 12 bits of data with no trailing 0s (Figure 15). The maxi-
MAX187/MAX189

When using SPI or QSPI, set CPOL = 0 and CPHA = 0. mum clock frequency to ensure compatibility with QSPI
Conversion begins with a CS falling edge. DOUT goes is 2.77MHz.
low, indicating a conversion in progress. Wait until
DOUT goes high or the maximum specified 8.5µs con- Opto-Isolated Interface,
version time. Two consecutive 1-byte reads are Serial-to-Parallel Conversion
required to get the full 12 bits from the ADC. DOUT out- Many industrial applications require electrical isolation
put data transitions on SCLK’s falling edge and is to separate the control electronics from hazardous
clocked into the µP on SCLK’s rising edge. electrical conditions, provide noise immunity, or pre-
vent excessive current flow where ground disparities
The first byte contains a leading 1 and 7 bits of conver- exist between the ADC and the rest of the system.
sion result. The second byte contains the remaining 5 Isolation amplifiers typically used to accomplish these
bits and 3 trailing 0s. See Figure 13 for connections tasks are expensive. In cases where the signal is even-
and Figure 14 for timing. tually converted to a digital form, it is cost effective to
QSPI isolate the input using opto-couplers in a serial link.
Set CPOL = CPHA = 0. Unlike SPI, which requires two The MAX187 is ideal in this application because it
1-byte reads to acquire the 12 bits of data from the includes both T/H amplifier and voltage reference,
ADC, QSPI allows the minimum number of clock cycles operates from a single supply, and consumes very little
necessary to clock in the data. The MAX187/MAX189 power (Figure 16).
require 13 clock cycles from the µP to clock out the

+5V ON THIS SIDE OF CS/START

BARRIER MUST BE ISOLATED POWER SCLK/INPUT CLOCK
6N136 +5V
+5V
8 1 7
200Ω QH
7 2 14 6
3k SER QG
6 3 74HC595 QF 5
11 4
5 4 SCK QE
10µF 3
QD D11 (MSB)
12 QC 2
MAX187 74HC04 RCK D10
6N136 1
QB D9
0.1µF 1 3 8 1 10 15
VDD SHDN SCLR QA D8
200Ω 16
2 7 7 2 74HC04 +5V
AIN CS 3k
4 8 6 3 13 8
REF SCLK 0.1µF
ANALOG 4.7µF 5 6 5 4
INPUT GND DOUT
470Ω 9
6N136 QH′ 7
QH D7
1 8 14 SER 6
QG D6
2 7 74HC595 QF 5
D5
SIGNAL 8.2k 11 4
SCK QE D4
GROUND 3 6 3
QD D3
4 5 12 2
RCK QC D2
QB 1
D1
10 QA 15
+5V SCLR D0(LSB)
16
+5V
13 8
0.1µF

Figure 16. 12-Bit Isolated ADC

16 ______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

The ADC results are transmitted across a 1500V isola-

MAX187/MAX189
tion barrier provided by three 6N136 opto-isolators.
Isolated power must be supplied to the converter and
the isolated side of the opto-couplers. 74HC595 three-
state shift registers are used to construct a 12-bit paral-
lel data output. The timing sequence is identical to the SUPPLIES
timing shown in Figure 8. Conversion speed is limited
by the delay through the opto-isolators. With a 140kHz +5V GND
clock, conversion time is 100µs.
The universal 12-bit parallel data output can also be
used without the isolation stage when a parallel inter-
face is required. Clock frequencies up to 2.9MHz are R* = 10Ω
4.7µF
possible without violating the 20ns shift-register setup
time. Delay or invert the clock signal to the shift regis-
ters beyond 2.9MHz.
0.01µF
Layout, Grounding, Bypassing VDD AGND DGND +5V DGND
For best performance, use printed circuit boards. Wire-
wrap boards are not recommended. Board layout DIGITAL
MAX187 CIRCUITRY
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi- MAX189
tal (especially clock) lines parallel to one another, or
*OPTIONAL
digital lines underneath the ADC package.
Figure 17 shows the recommended system ground
connections. A single-point analog ground (“star” Figure 17. Power-Supply Grounding Condition
ground point) should be established at GND, separate
from the logic ground. All other analog grounds should
be connected to this ground. The 16-pin versions also
have a dedicated DGND pin available. Connect DGND
to this star ground point for further noise reduction. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low imped-
ance and as short as possible for noise-free operation.
High-frequency noise in the V DD power supply may
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 4.7µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection. If the +5V
power supply is very noisy, a 10Ω resistor can be con-
nected as a lowpass filter to attenuate supply noise
(Figure 17).

______________________________________________________________________________________ 17
 +5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189

__Ordering Information (continued) ____Pin Configurations (continued)

PART TEMP. RANGE PIN-PACKAGE ERROR

(LSB)
MAX187AEPA -40°C to +85°C 8 Plastic DIP ±1⁄2
MAX187BEPA -40°C to +85°C 8 Plastic DIP ±1 V DD 1 16 SCLK
MAX187CEPA -40°C to +85°C 8 Plastic DIP ±2 N.C. 2 15 CS
MAX187AEWE -40°C to +85°C 16 Wide SO ±1⁄2 AIN 3 14 N.C.
MAX187BEWE -40°C to +85°C 16 Wide SO ±1 N.C. 4 MAX187 13 N.C.
MAX187CEWE -40°C to +85°C 16 Wide SO ±2 MAX189
N.C. 5 12 DOUT
MAX187AMJA -55°C to +125°C 8 CERDIP** ±1⁄2
SHDN 6 11 DGND
MAX187BMJA -55°C to +125°C 8 CERDIP** ±1
N.C. 7 10 AGND
MAX189ACPA 0°C to +70°C 8 Plastic DIP ±1⁄2
REF 8 9 N.C.
MAX189BCPA 0°C to +70°C 8 Plastic DIP ±1
MAX189CCPA 0°C to +70°C 8 Plastic DIP ±2 Wide SO
MAX189ACWE 0°C to +70°C 16 Wide SO ±1⁄2
MAX189BCWE 0°C to +70°C 16 Wide SO ±1
MAX189CCWE 0°C to +70°C 16 Wide SO ±2
MAX189BC/D 0°C to +70°C Dice* ±1
MAX189AEPA -40°C to +85°C 8 Plastic DIP ±1⁄2
MAX189BEPA -40°C to +85°C 8 Plastic DIP ±1
MAX189CEPA -40°C to +85°C 8 Plastic DIP ±2
MAX189AEWE -40°C to +85°C 16 Wide SO ±1⁄2
MAX189BEWE -40°C to +85°C 16 Wide SO ±1
MAX189CEWE -40°C to +85°C 16 Wide SO ±2
MAX189AMJA -55°C to +125°C 8 CERDIP** ±1⁄2
MAX189BMJA -55°C to +125°C 8 CERDIP** ±1
* Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.

18 ______________________________________________________________________________________
 +5V, Low-Power, 12-Bit Serial ADCs

___________________Chip Topography

MAX187/MAX189
MAX187/MAX189

V DD SCLK

CS
AIN

0.151"
(3.84mm)

DOUT

DGND
SHDN

REF AGND
0.117" AGND
(2.97mm)

TRANSISTOR COUNT: 2278;

SUBSTRATE CONNECTED TO VDD.

______________________________________________________________________________________ 19
 +5V, Low-Power, 12-Bit Serial ADCs
MAX187/MAX189

________________________________________________________________Package Information
INCHES MILLIMETERS
DIM
E MIN MAX MIN MAX
A2 A3 A – 0.200 – 5.08
D E1 A1 0.015 – 0.38 –
A A2 0.125 0.175 3.18 4.45
A3 0.055 0.080 1.40 2.03
B 0.016 0.020 0.41 0.51
0°-15° B1 0.045 0.065 1.14 1.65
A1 C 0.008 0.012 0.20 0.30
e C D1 0.050 0.090 1.27 2.29
L eA E 0.600 0.625 15.24 15.88
B1
E1 0.525 0.575 13.34 14.61
B eB
e 0.100 – 2.54 –
eA 0.600 – 15.24 –
D1 eB – 0.700 – 17.78
L 0.120 0.150 3.05 3.81
P PACKAGE
PLASTIC INCHES MILLIMETERS
DIM PINS
MIN MAX MIN MAX
DUAL-IN-LINE D 24 1.230 1.270 31.24 32.26
D 28 1.430 1.470 36.32 37.34
D 40 2.025 2.075 51.44 52.71

INCHES MILLIMETERS
DIM
MIN MAX MIN MAX
D A 0.093 0.104 2.35 2.65
A1 0.004 0.012 0.10 0.30
0°- 8° B 0.014 0.019 0.35 0.49
A C 0.009 0.013 0.23 0.32
0.101mm E 0.291 0.299 7.40 7.60
0.005in.
e B e 0.050 1.27
A1 H 0.394 0.419 10.00 10.65
C L
L 0.016 0.050 0.40 1.27

INCHES MILLIMETERS
DIM PINS
MIN MAX MIN MAX
E H W PACKAGE D 16 0.398 0.413 10.10 10.50
SMALL D 18 0.447 0.463 11.35 11.75
D 20 0.496 0.512 12.60 13.00
OUTLINE
D 24 0.598 0.614 15.20 15.60
D 28 0.697 0.713 17.70 18.10
21-0042A

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600

© 1993 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.