with Data Protect and Sequential Read

NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM

February 2000

NM93CS66
(MICROWIRE™ Bus Interface) 4096-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description Features
NM93CS66 is a 4096-bit CMOS non-volatile EEPROM organized ■ Wide VCC 2.7V - 5.5V
as 256 x 16-bit array. This device features MICROWIRE interface
■ Programmable write protection
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat- ■ Sequential register read
ible to many of standard Microcontrollers and Microprocessors. ■ Typical active current of 200µA
NM93CS66 offers programmable write protection to the memory 10µA standby current typical
array using a special register called Protect Register. Selected 1µA standby current typical (L)
memory locations can be protected against write by programming 0.1µA standby current typical (LZ)
this Protect Register with the address of the first memory location
■ No Erase instruction required before Write instruction
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this ■ Self timed write cycle
address can be “permanently locked” into the device, making all ■ Device status during programming cycles
future attempts to change data impossible. In addition this device ■ 40 year data retention
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are ■ Endurance: 1,000,000 data changes
10 instructions implemented on the NM93CS66, 5 of which are for ■ Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconduc-
tor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
“LZ” and “L” versions of NM93CS66 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.

Functional Diagram
VCC
CS
INSTRUCTION PRE
SK DECODER
CONTROL LOGIC PE
INSTRUCTION AND CLOCK
DI GENERATORS
REGISTER

COMPARATOR
HIGH VOLTAGE
AND
ADDRESS PROTECT GENERATOR
WRITE ENABLE
REGISTER REGISTER AND
PROGRAM
TIMER

DECODER EEPROM ARRAY

16

READ/WRITE AMPS
16 VSS

DATA IN/OUT REGISTER

16 BITS

DO DATA OUT BUFFER

© 1999 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)

CS 1 8 VCC
SK 2 7 PRE
DI 3 6 PE

DO 4 5 GND

Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
PE Program Enable
PRE Protect Register Enable
VCC Power Supply

Ordering Information
NM 93 CS XX LZ E XXX Letter Description
Package N 8-pin DIP
M8 8-pin SO
MT8 8-pin TSSOP
Temp. Range None 0 to 70°C
V -40 to +125°C
E -40 to +85°C
Voltage Operating Range Blank 4.5V to 5.5V
L 2.7V to 5.5V
LZ 2.7V to 5.5V and
<1µA Standby Current
Density 66 4096 bits
C CMOS
CS Data protect and sequential
read
Interface 93 MICROWIRE
Fairchild Memory Prefix

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Absolute Maximum Ratings (Note 1) Operating Conditions
Ambient Storage Temperature -65°C to +150°C Ambient Operating Temperature
All Input or Output Voltages +6.5V to -0.3V NM93CS66 0°C to +70°C
with Respect to Ground NM93CS66E -40°C to +85°C
NM93CS66V -40°C to +125°C
Lead Temperature
(Soldering, 10 sec.) +300°C Power Supply (VCC) 4.5V to 5.5V
ESD rating 2000V

DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified

Symbol Parameter Conditions Min Max Units
ICCA Operating Current CS = VIH, SK=1.0 MHz 1 mA
ICCS Standby Current CS = VIL 50 µA
IIL Input Leakage VIN = 0V to VCC ±-1 µA
IOL Output Leakage (Note 2)
VIL Input Low Voltage -0.1 0.8 V
VIH Input High Voltage 2 VCC +1
VOL1 Output Low Voltage IOL = 2.1 mA 0.4 V
VOH1 Output High Voltage IOH = -400 µA 2.4
VOL2 Output Low Voltage IOL = 10 µA 0.2 V
VOH2 Output High Voltage IOH = -10 µA VCC - 0.2
fSK SK Clock Frequency (Note 3) 1 MHz
tSKH SK High Time 0°C to +70°C 250 ns
-40°C to +125°C 300
tSKL SK Low Time 250 ns
tSKS SK Setup Time 50 ns
tCS Minimum CS Low Time (Note 4) 250 ns
tCSS CS Setup Time 100 ns
tPRES PRE Setup Time 50 ns
tDH DO Hold Time 70 ns
tPES PE Setup Time 50 ns
tDIS DI Setup Time 100 ns
tCSH CS Hold Time 0 ns
tPEH PE Hold Time 250 ns
tPREH PRE Hold Time 50 ns
tDIH DI Hold Time 20 ns
tPD Output Delay 500 ns
tSV CS to Status Valid 500 ns
tDF CS to DO in Hi-Z CS = VIL 100 ns
tWP Write Cycle Time 10 ms

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Absolute Maximum Ratings (Note 1) Operating Conditions
Ambient Storage Temperature -65°C to +150°C Ambient Operating Temperature
All Input or Output Voltages +6.5V to -0.3V NM93CS66L/LZ 0°C to +70°C
with Respect to Ground NM93CS66LE/LZE -40°C to +85°C
NM93CS66LV/LZV -40°C to +125°C
Lead Temperature
(Soldering, 10 sec.) +300°C Power Supply (VCC) 2.7V to 5.5V
ESD rating 2000V

DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified

Symbol Parameter Conditions Min Max Units
ICCA Operating Current CS = VIH, SK=1.0 MHz 1 mA
ICCS Standby Current CS = VIL
L 10 µA
LZ (2.7V to 4.5V) 1 µA
IIL Input Leakage VIN = 0V to VCC ±1 µA
IOL Output Leakage (Note 2)
VIL Input Low Voltage -0.1 0.15VCC V
VIH Input High Voltage 0.8VCC VCC +1
VOL Output Low Voltage IOL = 10µA 0.1VCC V
VOH Output High Voltage IOH = -10µA 0.9VCC
fSK SK Clock Frequency (Note 3) 0 250 KHz
tSKH SK High Time 1 µs
tSKL SK Low Time 1 µs
tSKS SK Setup Time 0.2 µs
tCS Minimum CS Low Time (Note 4) 1 µs
tCSS CS Setup Time 0.2 µs
tPRES PRE Setup Time 50 ns
tDH DO Hold Time 70 ns
tPES PE Setup Time 50 ns
tDIS DI Setup Time 0.4 µs
tCSH CS Hold Time 0 ns
tPEH PE Hold Time 250 ns
tPREH PRE Hold Time 50 ns
tDIH DI Hold Time 0.4 µs
tPD Output Delay 2 µs
tSV CS to Status Valid 1 µs
tDF CS to DO in Hi-Z CS = VIL 0.4 µs
tWP Write Cycle Time 15 ms

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
Capacitance TA = 25°C, f = 1 MHz (Note 5) to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Symbol Test Typ Max Units Note 2: Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
COUT Output Capacitance 5 pF SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
CIN Input Capacitance 5 pF allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5: This parameter is periodically sampled and not 100% tested.
AC Test Conditions
VCC Range VIL/VIH VIL/VIH VOL/VOH IOL/IOH
Input Levels Timing Level Timing Level
2.7V ≤ VCC ≤ 5.5V 0.3V/1.8V 1.0V 0.8V/1.5V ±10µA
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V 0.4V/2.4V 1.0V/2.0V 0.4V/2.4V 2.1mA/-0.4mA
(TTL Levels)
Output Load: 1 TTL Gate (CL = 100 pF)

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Pin Description Program Enable (PE)
This is an active high input pin to the device and is used to enable
Chip Select (CS)
operations, that are write in nature, to the memory array and to the
This is an active high input pin to NM93CS66 EEPROM (the device) Protect register. When this pin is held high, operations that are
and is generated by a master that is controlling the device. A high “write” in nature are enabled. When this pin is held low, operations
level on this pin selects the device and a low level deselects the that are “write” in nature are disabled. This pin operates in
device. All serial communications with the device is enabled only conjunction with PRE pin. Refer Table1 for functional matrix of this
when this pin is held high. However this pin cannot be permanently pin for various operations.
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to Microwire Interface
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low. A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Serial Clock (SK) Memory array and on the Protect Register, a set of 10 instructions
are implemented on NM93CS66. The format of each instruction is
This is an input pin to the device and is generated by the master that
listed in Table 1.
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa- Instruction
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge Each of the above 10 instructions is explained under individual
of this clock input. This pin is gated by CS signal. instruction descriptions.

Serial Input (DI) Start Bit

This is an input pin to the device and is generated by the master This is a 1-bit field and is the first bit that is clocked into the device
that is controlling the device. The master transfers Input informa- when a Microwire cycle starts. This bit has to be “1” for a valid cycle
tion (Start bit, Opcode bits, Array addresses and Data) serially via to begin. Any number of preceding “0” can be clocked into the
this pin into the device. This Input information is latched on the device before clocking a “1”.
rising edge of the SCK. This pin is gated by CS signal. Opcode
Serial Output (DO) This is a 2-bit field and should immediately follow the start bit.
This is an output pin from the device and is used to transfer Output These two bits (along with PRE, PE signals and 2 MSB of address
data via this pin to the controlling master. Output data is serially field) select a particular instruction to be executed.
shifted out on this pin from the rising edge of the SCK. This pin is Address Field
active only when the device is selected.
This is a 8-bit field and should immediately follow the Opcode bits.
Protect Register Enable (PRE) In NM93CS66, all 8 bits are used for address decoding during
This is an active high input pin to the device and is used to READ, WRITE and PRWRITE instructions.During all other in-
distinguish operations to memory array and operations to Protect structions (with the exception of PRREAD), the MSB 2 bits are
Register. When this pin is held low, operations to the memory used to decode instruction (along with Opcode bits, PRE and PE
array are enabled. When this pin is held high, operations to the signals).
Protect Register are enabled. This pin operates in conjunction Data Field
with PE pin. Refer Table1 for functional matrix of this pin for
various operations. This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
TABLE 1. Instruction set
Instruction Start Bit Opcode Field Address Field Data Field PRE Pin PE Pin
READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 0 X
WEN 1 00 1 1 X X X X X X 0 1
WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 0 1
WRALL 1 00 0 1 X X X X X X D15-D0 0 1
WDS 1 00 0 0 X X X X X X 0 X
PRREAD 1 10 X X X X X X X X 1 X
PREN 1 00 1 1 X X X X X X 1 1
PRCLEAR 1 11 1 1 1 1 1 1 1 1 1 1
PRWRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 1 1
PRDS 1 00 0 0 0 0 0 0 0 0 1 1

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Functional Description the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
A typical Microwire cycle starts by first selecting the device device becomes write-enabled at the end of this cycle when the
(bringing the CS signal high). Once the device is selected, a valid CS signal is brought low. The PRE pin should be held low during
Start bit (“1”) should be issued to properly recognize the cycle. this cycle. Execution of a READ instruction is independent of WEN
Following this, the 2-bit opcode of appropriate instruction should instruction. Refer Write Enable cycle diagram.
be issued. After the opcode bits, the 8-bit address information
should be issued. For certain instructions, some (or all) of these 3) Write (WRITE)
8 bits are don’t care values (can be “0” or “1”), but they should still WRITE instruction allows write operation to a specified location in
be issued. Following the address information, depending on the the memory with a specified data. This instruction is valid only
instruction (WRITE and WRALL), 16-Bit data is issued. Other- when the following are true:
wise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other ■ Device is write-enabled (Refer WEN instruction)
instructions perform certain control functions and do not deal with ■ Address of the write location is not write-protected
data bits. The Microwire cycle ends when the CS signal is brought
■ PE pin is held high during this cycle
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device ■ PRE pin should be held low during this cycle
remains busy till the completion of the internal cycle. Each of the Input information (Start bit, Opcode, Address and Data) for this
10 instructions is explained in detail in the following sections. WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
Memory Instructions before the next rising edge of the SK clock. This falling edge of the
Following five instructions, READ, WEN, WRITE, WRALL and CS initiates the self-timed programming cycle. It takes tWP time
WDS are specific to operations intended for memory array. The (Refer appropriate DC and AC Electrical Characteristics table) for
PRE pin should be held low during these instructions. the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
1) Read and Sequential Read (READ)
The status of the internal programming cycle can be polled at any
READ instruction allows data to be read from a selected location time by bringing the CS signal high again, after tCS interval. When
in the memory array. Input information (Start bit, Opcode and CS signal is high, the DO pin indicates the READY/BUSY status
Address) for this instruction should be issued as listed under of the chip. DO = logical 0 indicates that the programming is still
Table1. Upon receiving a valid input information, decoding of the in progress. DO = logical 1 indicates that the programming is
opcode and the address is made, followed by data transfer from finished and the device is ready for another instruction. It is not
the selected memory location into a 16-bit serial-out shift register. required to provide the SK clock during this status polling. While
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB) the device is busy, it is recommended that no new instruction be
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit issued. Refer Write cycle diagram.
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After It is also recommended to follow this instruction (after the device
reading the 16-bit data, the CS signal can be brought low to end becomes READY) with a Write Disable (WDS) instruction to
the Read cycle. The PRE pin should be held low during this cycle. safeguard data against corruption due to spurious noise, inadvert-
Refer Read cycle diagram. ent writes etc.

This device also offers “sequential memory read” operation to 4) Write All (WRALL)
allow reading of data from the additional memory locations instead Write all (WRALL) instruction is similar to the Write instruction
of just one location. It is started in the same manner as normal read except that WRALL instruction will simultaneously program all
but the cycle is continued to read further data (instead of terminat- memory locations with the data pattern specified in the instruction.
ing after reading the first 16-bit data). After providing 16-bit data, This instruction is valid only when the following are true:
the device automatically increments the address pointer to the
next location and continues to provide the data from that location. ■ Protect Register has been cleared (Refer PRCLEAR
Any number of locations can be read out in this manner, however, instruction)
after reading out from the last location, the address pointer points ■ Device is write-enabled (Refer WEN instruction)
back to the first location. If the cycle is continued further, data will
■ PE pin is held high during this cycle
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like ■ PRE pin should be held low during this cycle
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequen- Input information (Start bit, Opcode, Address and Data) for this
tial Read cycle diagram. WRALL instruction should be issued as listed under Table1. After
2) Write Enable (WEN) inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
When VCC is applied to the part, it “powers up” in the Write Disable CS initiates the self-timed programming cycle. It takes tWP time
(WDS) state. Therefore, all programming operations (for both (Refer appropriate DC and AC Electrical Characteristics table) for
memory array and Protect Register) must be preceded by a Write the internal programming cycle to finish. During this time, the
Enable (WEN) instruction. Once a Write Enable instruction is device remains busy and is not ready for another instruction.
executed, programming remains enabled until a Write Disable Status of the internal programming can be polled as described
(WDS) instruction is executed or VCC is completely removed from under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Write All
cycle diagram.

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
5) Write Disable (WDS) ■ PREN instruction was executed immediately prior to
PRCLEAR instruction
Write Disable (WDS) instruction disables all programming opera-
tions and is recommended to follow all programming operations. ■ PE pin is held high during this cycle
Executing this instruction after a valid write instruction would ■ PRE pin is held high during this cycle
protect against accidental data disturb due to spurious noise, Input information (Start bit, Opcode and Address) for this PRCLEAR
glitches, inadvertent writes etc. Input information (Start bit, Opcode instruction should be issued as listed under Table1. After inputting
and Address) for this WDS instruction should be issued as listed the last bit of address (A0 bit), CS signal must be brought low
under Table1. The device becomes write-disabled at the end of before the next rising edge of the SK clock. This falling edge of the
this cycle when the CS signal is brought low. Execution of a READ CS initiates the self-timed clear cycle. It takes tWP time (Refer
instruction is independent of WDS instruction. Refer Write Disable appropriate DC and AC Electrical Characteristics table) for the
cycle diagram. internal clear cycle to finish. During this time, the device remains
busy and is not ready for another instruction. Status of the internal
Protect Register Instructions
programming can be polled as described under WRITE instruction
Following five instructions, PRREAD, PREN, PRCLEAR, description. While the device is busy, it is recommended that no
PRWRITE and PRDS are specific to operations intended for new instruction be issued. Refer Protect Register Clear cycle
Protect Register. The PRE pin should be held high during these diagram.
instructions.
4) Protect Register Write (PRWRITE)
1) Protect Register Read (PRREAD)
This instruction is used to write the starting address of the memory
This instruction reads the content of the internal Protect Register. section to be write-protected into the Protect register. After the
Content of this register is 8-bit wide and is the starting address of execution of PRWRITE instruction, all memory locations greater
the “write-protected” section of the memory array. All memory than or equal to this address are write-protected. PRWRITE
locations greater than or equal to this address are write-protected. instruction is enabled (valid) only the following are true:
Input information (Start bit, Opcode and Address) for this PRREAD
instruction should be issued as listed under Table 1. Upon ■ PRCLEAR instruction was executed first (to clear the Protect
Register)
receiving a valid input information, decoding of the opcode and the
address is made, followed by data transfer (address information) ■ PREN instruction was executed immediately prior to
from the Protect Register. This 8-bit data is then shifted out on the PRWRITE instruction
DO pin with the MSB first and the LSB last. Like the READ ■ PE pin is held high during this cycle
instruction a dummy-bit (logical 0) precedes this 8-bit data output
■ PRE pin is held high during this cycle
string. Output data changes are initiated on the rising edge of the
SK clock. After reading the 8-bit data, the CS signal can be brought Input information (Start bit, Opcode and Address) for this PRWRITE
low to end the PRREAD cycle. The PRE pin should be held high instruction should be issued as listed under Table1. After inputting
during this cycle. Refer Protect Register Read cycle diagram. the last bit of address (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
2) Protect Register Enable (PREN) CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
This instruction is required to enable PRCLEAR, PRWRITE and
the internal programming cycle to finish. During this time, the
PRDS instructions and should be executed prior to executing
device remains busy and is not ready for another instruction.
PRCLEAR, PRWRITE and PRDS instructions. However, this
Status of the internal programming can be polled as described
PREN instruction is enabled (valid) only the following are true
under WRITE instruction description. While the device is busy, it
■ Device is write-enabled (Refer WEN instruction) is recommended that no new instruction be issued. Refer Protect
■ PE pin is held high during this cycle Register Write cycle diagram.
■ PRE pin is held high during this cycle 5) Protect Register Disable (PRDS)
Input information (Start bit, Opcode and Address) for this PREN Unlike all other instructions, this instruction is a one-time-only
instruction should be issued as listed under Table1. The Protect instruction which when executed permanently write-protects
Register becomes enabled for PRCLEAR, PRWRITE and PRDS the Protect Register and renders it unalterable in the future. This
instructions at the end of this cycle when the CS signal is brought instruction is useful to safeguard vital data (typically read only
low. Note that this PREN instruction must immediately precede data) in the memory against any possible corruption. PRDS
a PRCLEAR, PRWRITE or PRDS instruction. In other words, no instruction is enabled (valid) only the following are true:
other instruction should be executed between a PREN instruction
and a PRCLEAR, PRWRITE or PRDS instruction. Refer Protect ■ PREN instruction was executed immediately prior to PRDS
Register Enable cycle diagram. instruction
■ PE pin is held high during this cycle
3) Protect Register Clear (PRCLEAR)
■ PRE pin is held high during this cycle
This instruction clears the content of the Protect register and
therefore enables write operations (WRITE or WRALL) to all
memory locations. Executing this instruction will program the
content of the Protect Register with a pattern of all 1s. However,
in this case, WRITE operation to the last memory address
(0x11111111) is still enabled. PRCLEAR instruction is enabled
(valid) only when the following are true:

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Input information (Start bit, Opcode and Address) for this PRDS Clearing of Ready/Busy status
instruction should be issued as listed under Table1. After inputting
the last bit of address (A0 bit), CS signal must be brought low When programming is in progress, the Data-Out pin will display
before the next rising edge of the SK clock. This falling edge of the the programming status as either BUSY (low) or READY (high)
CS initiates the self-timed programming cycle. It takes tWP time when CS is brought high (DO output will be tri-stated when CS is
(Refer appropriate DC and AC Electrical Characteristics table) for low). To restate, during programming, the CS pin may be brought
the internal programming cycle to finish. During this time, the high and low any number of times to view the programming status
device remains busy and is not ready for another instruction. without affecting the programming operation. Once programming
Status of the internal programming can be polled as described is completed (Output in READY state), the output is ‘cleared’
under WRITE instruction description. While the device is busy, it (returned to normal tri-state condition) by clocking in a Start Bit.
is recommended that no new instruction be issued. The Protect After the Start Bit is clocked in, the output will return to a tri-stated
Register is permanently write-protected at the end of this cycle. condition. When clocked in, this Start Bit can be the first bit in a
Refer Protect Register Disable cycle diagram. command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.

Related Document
Application Note: AN758 - Using Fairchild’s MICROWIRE™ EE-
PROM.

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Timing Diagrams
;
SYNCHRONOUS DATA TIMING ;
CS ;; ;
;;; ;; ;; ; ; ;
tSKS tCSS tSKH tSKL tCSH

SK ;;; ;; ;; ; ; ;
;;; ;;
tPRES
; ; ; ; ; tPREH

PRE ;;;;;; ;; ; ; ;;;

;;;;;; ;;
tPES
; ; ;;; tPEH

PE ;;;; ; ;; ; ; ;;;
;;; ;;;;; tDIS tDIH
; ; ;;
DI ;; ;;;;;;;;;
;;;;;; Valid
Input
Valid
Input ;
; ;;;;;;;;;;;;;;;;;;;
; ;;;;;;;;
;;;;;; ; tPD
;;;;;;;;;;;;;;;;;;;;;
tDH
; ; ;
tPD tDF

; ;;;;;;;
;;;;;;;;
DO (Data Read) ; Valid
Output ; ;;;;;;;; ;
;;;;;;; Valid
Output

; ;;;;;;; ;;;;;; ;;;;;;;; ;

tDF
tSV

;;;;;;;;;
; ;
DO (Status Read) ;
Valid Status

NORMAL READ CYCLE (READ)

;;;;
;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE

PE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; tCS
CS

SK

DI
1 1 0 A7 A6 A1 A0
;;;;;;;;;;;;;;
Star t
Bit
Opcode
Bits(2)
Address
Bits(8) ;;;;;;;;;;;;;;
;;;
High - Z
DO 0 D15 D1 D0

93CS66:
D u m my
Bit ;;;
Address bits pattern -> User defined

SEQUENTIAL READ CYCLE (PRE = 0; PE = X)

;;;;
;;;;
PRE

tCS
CS

SK

DI
1 1 0 A7 A0
;;;;;;;;;;;;;;;;;;;;;;;;
Star t
Bit
Opcode
Bits(2)
Address
Bits(8) ;;;;;;;;;;;;;;;;;;;;;;;;
DO
High - Z
0 D15
;;; D0 D15 D0 D15 D0

93CS66:
Dummy
Bit ;;;
Data(n) Data(n+1) Data(n+2)

Address bits patter n -> User defined

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NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)

PRE

PE
tCS
CS

SK

1 0 0 A7 A6 A1 A0
DI
Star t Opcode Address
Bit Bits(2) Bits(8)
High - Z
DO
93CS66:
A d d r e s s b i t s p a t t e r n - > 1 - 1 - x - x - x - x - x - x ; ( x - > D o n ' t C a r e, c a n b e 0 o r 1 )

WRITE DISABLE CYCLE (WDS)

;;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE

PE
;;;;;;;;;;;;;;;;;;;;;;;;;;; tCS
CS

SK

1 0 0 A7 A6 A1 A0
DI
Star t Opcode Address
Bit Bits(2) Bits(8)
High - Z
DO
93CS66:
Address bits patter n -> 0-0-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

WRITE CYCLE (WRITE)

PRE

PE
tCS
CS

SK

1 0 1 A7 A6 A1 A0 D15 D14 D1 D0
DI
Star t Opcode Address Data tWP
Bit Bits(2) Bits(8) Bits(16)
High - Z Ready
DO Busy
93CS66:
Address bits pattern -> User defined
Data bits pattern -> User defined

10 www.fairchildsemi.com
NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Timing Diagrams (Continued)
WRITE ALL CYCLE (WRALL)

PRE

PE
tCS
CS

SK

1 0 0 A7 A6 A1 A0 D15 D14 D1 D0
DI
Star t Opcode Address Data tWP
Bit Bits(2) Bits(8) Bits(16)
High - Z Ready
DO Busy
93CS66:
Address bits patter n -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)
Data bits patter n -> User defined

PROTECT REGISTER READ CYCLE (PRREAD)

;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;
PRE

PE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; tCS
CS

SK

DI
1 1 0 A7 A6 A1 A0
;;;;;;;;;;;;;;
Star t
Bit
Opcode
Bits(2)
Address
Bits(8) ;;;;;;;;;;;;;;
DO
High - Z
0
;;;
D7 D1 D0

;;;
Dummy
Bit
93CS66:
Address bits patter n -> x-x-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

PROTECT REGISTER ENABLE CYCLE (PREN)

;;;;;;;;;
;;;;;;;;;
PRE

PE
;;;;;;;;;
tCS
CS

SK

1 0 0 A7 A6 A1 A0
DI
Star t Opcode Address
Bit Bits(2) Bits(8)
High - Z
DO
93CS66:
Address bits patter n -> 1-1-x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

11 www.fairchildsemi.com
NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Timing Diagrams (Continued)
PROTECT REGISTER CLEAR CYCLE (PRCLEAR)

;;;;;;;;;
;;;;;;;;;
PRE

PE
;;;;;;;;;
tCS
CS

SK

1 1 1 A7 A6 A1 A0
DI
tWP
Star t Opcode Address
Bit Bits(2) Bits(8)
High - Z Ready
DO Busy
93CS66:
Address bits patter n -> 1-1-1-1-1-1-1-1

PROTECT REGISTER WRITE CYCLE (PRWRITE)

;;;;;;;;;
;;;;;;;;;
PRE

PE
;;;;;;;;;
tCS
CS

SK

1 0 1 A7 A6 A1 A0
DI
tWP
Star t Opcode Address
Bit Bits(2) Bits(8)
High - Z Ready
DO Busy
93CS66:
Address bits patter n -> User defined

PROTECT REGISTER DISABLE CYCLE (PRDS)

;;;;;;;;;
;;;;;;;;;
PRE

PE
;;;;;;;;;
tCS
CS

SK

1 0 0 A7 A6 A1 A0
DI
tWP
Star t Opcode Address
Bit Bits(2) Bits(8)
High - Z Ready
DO Busy
93CS66:
Address bits patter n -> 0-0-0-0-0-0-0-0

12 www.fairchildsemi.com
NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Timing Diagrams (Continued)
CLEARING READY STATUS

;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;
PRE

PE
;;;;;;;;;;;;;;;;;;;;;;;;;;
CS

SK

DI
Star t
Bit
High - Z Ready High - Z
DO Busy

Note: This Star t bit can also be par t of a next instr uction. Hence the cycle
can be continued(instead of getting ter minated, as shown) as if a new
instr uction is being issued.

13 www.fairchildsemi.com
NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)

8 7 6 5

0.228 - 0.244
(5.791 - 6.198)

1 2 3 4
Lead #1
IDENT

0.150 - 0.157
(3.810 - 3.988) 0.053 - 0.069
0.010 - 0.020 (1.346 - 1.753) 0.004 - 0.010
x 45° 8° Max, Typ.
(0.254 - 0.508) (0.102 - 0.254)
All leads
Seating
0.04 Plane
0.0075 - 0.0098 (0.102) 0.014
(0.190 - 0.249) All lead tips 0.016 - 0.050 (0.356)
Typ. All Leads (0.406 - 1.270) 0.050 0.014 - 0.020 Typ.
Typ. All Leads (1.270) (0.356 - 0.508)
Typ

Molded Package, Small Outline, 0.15 Wide, 8-Lead (M8)

Package Number M08A

14 www.fairchildsemi.com
NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)

8 5

(4.16) Typ (7.72) Typ

0.169 - 0.177
0.246 - 0.256
(4.30 - 4.50)
(6.25 - 6.5)
(1.78) Typ

0.123 - 0.128 (0.42) Typ

(3.13 - 3.30) (0.65) Typ

1 4 Land pattern recommendation

Pin #1 IDENT

0.0433
Max
(1.1)

See detail A 0.0035 - 0.0079

0.002 - 0.006
(0.05 - 0.15)

0.0256 (0.65)
Typ. Gage
0.0075 - 0.0098
(0.19 - 0.30) plane
0°-8°

DETAIL A
Typ. Scale: 40X 0.0075 - 0.0098
0.020 - 0.028 Seating (0.19 - 0.25)
(0.50 - 0.70) plane

Notes: Unless otherwise specified

1. Reference JEDEC registration MO153. Variation AA. Dated 7/93

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

15 www.fairchildsemi.com
NM93CS66 Rev. F.2
 with Data Protect and Sequential Read
NM93CS66 (MICROWIRE Bus Interface) 4096-Bit Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)

0.090
(2.286) 0.032 ± 0.005 8 7
8 7 6 5 (0.813 ± 0.127)
0.092 RAD
DIA
(2.337)
0.250 - 0.005 Pin #1
Pin #1 IDENT + IDENT
(6.35 ± 0.127)
Option 1 1
1 2 3 4
0.280 MIN Option 2
0.040 Typ.
(7.112)
0.030 (1.016) 0.039 0.145 - 0.200
MAX
0.300 - 0.320 (0.762)
20° ± 1° (0.991) (3.683 - 5.080)
(7.62 - 8.128)

0.130 ± 0.005
(3.302 ± 0.127)

0.125 - 0.140
95° ± 5°
0.065 (3.175 - 3.556)
0.125 0.020
0.009 - 0.015 (1.651) 90° ± 4°
(3.175) Typ (0.508)
(0.229 - 0.381) DIA
NOM 0.018 ± 0.003 Min
+0.040
0.325 -0.015 (0.457 ± 0.076)
+1.016 0.100 ± 0.010
8.255 -0.381
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381) 0.060
(1.524)
0.050
(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, 2. A critical component is any component of a life support device
(a) are intended for surgical implant into the body, or (b) support or system whose failure to perform can be reasonably ex-
or sustain life, and whose failure to perform, when properly pected to cause the failure of the life support device or system,
used in accordance with instructions for use provided in the or to affect its safety or effectiveness.
labeling, can be reasonably expected to result in a significant
injury to the user.

Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor

Americas Europe Hong Kong Japan Ltd.
Customer Response Center Fax: +44 (0) 1793-856858 8/F, Room 808, Empire Centre 4F, Natsume Bldg.
Tel. 1-888-522-5372 Deutsch Tel: +49 (0) 8141-6102-0 68 Mody Road, Tsimshatsui East 2-18-6, Yushima, Bunkyo-ku
English Tel: +44 (0) 1793-856856 Kowloon. Hong Kong Tokyo, 113-0034 Japan
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Italiano Tel: +39 (0) 2-249111-1 Fax: +852-2722-8383 Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

16 www.fairchildsemi.com
NM93CS66 Rev. F.2