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Experiment No: Aim: Apparatus: Theory:: Potential Divider Biasing

This experiment aims to study voltage divider biasing using a JFET. The key points are: 1) Voltage divider biasing uses two resistors (Rg1 and Rg2) connected in series as a potential divider to provide bias voltage (Vg) to the gate of the JFET. 2) The theoretical gate voltage (Vg), drain current (Id), and drain-source voltage (Vds) were calculated and compared to measured practical values, showing good agreement. 3) The conclusion is that voltage divider biasing was successfully implemented for this JFET, as verified by the quiescent operating point values matching theoretical calculations.

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503 views

Experiment No: Aim: Apparatus: Theory:: Potential Divider Biasing

This experiment aims to study voltage divider biasing using a JFET. The key points are: 1) Voltage divider biasing uses two resistors (Rg1 and Rg2) connected in series as a potential divider to provide bias voltage (Vg) to the gate of the JFET. 2) The theoretical gate voltage (Vg), drain current (Id), and drain-source voltage (Vds) were calculated and compared to measured practical values, showing good agreement. 3) The conclusion is that voltage divider biasing was successfully implemented for this JFET, as verified by the quiescent operating point values matching theoretical calculations.

Uploaded by

dipa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment No:

Aim: To study Voltage Divider biasing using JFET.


Apparatus: Resistors, JFET(BFW10), Power supply, Multisim
Theory:
Different types of techniques are used to bias the JFET in a proper manner. From various techniques,
below three are widely used:

▪ Fixed DC Biasing Technique


▪ Self-Biasing Technique
▪ Voltage (Potential) Divider Biasing

Potential Divider Biasing:

A slightly modified form of dc bias is provided by the circuit shown in figure. The resistors RGl and
RG2 form a potential divider across drain supply VDD. The voltage V2 across RG2 provides the necessary
bias. The additional gate resistor RGl from gate to supply voltage facilitates in larger adjustment of the dc
bias point and permits use of larger valued RS.

The gate is reverse biased so that IG = 0 and gate voltage

VG =V2 = (VDD/R G1 + R G2) *RG2

And

VGS = VG – VS= VG – ID Rs

The circuit is so designed that ID Rs is greater than VG so that VGS is negative. This provides correct bias
voltage.

The operating point can be determined as

ID = (V2 – VGS)/ RS

And VDS = VDD – ID (RD + RS)

1
Circuit Diagram:
VDD
16V

R1 RD
2.1MΩ 2.4kΩ XMM2

Q1
BFW10
XMM3
XMM1

R2 RS
270kΩ 1.5kΩ

Observations:

Sr. Parameters Theoretical Practical


No.
1. VG VG=1.82 V VG=1.822 V
2. ID ID= 2.1 mA ID= 1.932 mA
3. VDS VDS=6.64 V VDS=8.464 V

Calculations:
𝑅2 𝑉𝐷𝐷 ID =1.82 V*1.5 kΩ VDS = VDD - ID(RD + RS)
𝑉𝐺 =
𝑅1 + 𝑅2 = 1.932 mA
= 16 V - (1.932 mA)(2.4 k + 1.5 k)
(270𝑘Ω)(16 𝑉)
= = 8.464 V
(2.1𝑀Ω + 0.27𝑀Ω)

= 1.822 V

2
Conclusion:
We have successfully implemented Voltage Divider biasing using JFET and verified
quiescent (operating) point values with theoretical values.

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