TLC27M2, TLC27M2A, TLC27M2B, TLC27M7 Lincmos Precision Dual Operational Amplifiers
TLC27M2, TLC27M2A, TLC27M2B, TLC27M7 Lincmos Precision Dual Operational Amplifiers
ÎÎÎÎÎÎÎÎÎÎÎ
(TOP VIEW) (TOP VIEW) INPUT OFFSET VOLTAGE
30
340 Units Tested From 2 Wafer Lots
1OUT
VDD
NC
NC
25
1IN – 2 7 2OUT TA = 25°C
Percentage of Units – %
1IN + 3 6 2IN – P Package
3 2 1 20 19 20
GND 4 5 2IN + NC 4 18 NC
1IN – 5 17 2OUT
NC 16 NC 15
6
1IN + 7 15 2IN –
NC 14 NC 10
8
9 10 11 12 13
5
2IN +
NC
NC
NC
GND
0
NC – No internal connection – 800 – 400 0 400 800
VIO – Input Offset Voltage – µV
AVAILABLE OPTIONS
PACKAGE
VIOmax
TA SMALL OUTLINE CHIP CARRIER CERAMIC DIP PLASTIC DIP TSSOP
AT 25°C
(D) (FK) (JG) (P) (PW)
500 µV TLC27M7CD — — TLC27M7CP —
2 mV TLC27M2BCD — — TLC27M2BCP —
0°C to 70°C
5 mV TLC27M2ACD — — TLC27M2ACP —
10 mV TLC27M2CD — — TLC27M2CP TLC27M2CPW
500 µV TLC27M7ID — — TLC27M7IP —
2 mV TLC27M2BID — — TLC27M2BIP —
– 40°C to 85°C
5 mV TLC27M2AID — — TLC27M2AIP —
10 mV TLC27M2ID — — TLC27M2IP TLC27M2IPW
500 µV TLC27M7MD TLC27M7MFK TLC27M7MJG TLC27M7MP —
– 55°C to 125°C
10 mV TLC27M2MD TLC27M2MFK TLC27M2MJG TLC27M2MP —
The D and PW package is available taped and reeled. Add R suffix to the device type (e.g.,TLC27M7CDR).
description
The TLC27M2 and TLC27M7 dual operational amplifiers combine a wide range of input offset voltage grades
with low offset voltage drift, high input impedance, low noise, and speeds approaching that of general-purpose
bipolar devices.These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset
voltage stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and high slew rates make these cost-effective devices
ideal for applications which have previously been reserved for general-purpose bipolar products,but with only
a fraction of the power consumption. Four offset voltage grades are available (C-suffix and I-suffix types),
ranging from the low-cost TLC27M2 (10 mV) to the high-precision TLC27M7 (500 µV). These advantages, in
combination with good common-mode rejection and supply voltage rejection, make these devices a good
choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available on LinCMOS operational
amplifiers, without the power penalties of bipolar technology. General applications such as transducer
interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the
TLC27M2 and TLC27M7. The devices also exhibit low voltage single-supply operation, making them ideally
suited for remote and inaccessible battery-powered applications. The common-mode input voltage range
includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up.
The TLC27M2 and TLC27M7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from – 40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of –55°C to 125°C.
P3 P4
R6
R1 R2 N5
IN –
P5 P6
P1 P2
IN + C1
R5
OUT
N3
N1 N2 N4 N6 N7
R3 D1 R4 D2 R7
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V DD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
VDD VDD +
– –
VO VO
+ +
VI VI
CL RL CL RL
VDD –
2 kΩ 2 kΩ
VDD VDD +
20 Ω – –
1/2 VDD VO VO
20 Ω + +
20 Ω 20 Ω
VDD –
10 kΩ 10 kΩ
VDD VDD +
100 Ω 100 Ω
–
VI
– VI
VO VO
+ +
1/2 VDD
CL CL
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
One word of caution—many automatic testers as well as some bench-top operational amplifier testers
use the servo-loop technique with a resistor in series with the device input to measure the input bias
current (the voltage drop across the series resistor is measured and the bias current is calculated). This
method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an
open-socket reading is not feasible using this method.
5
8
8 5
V = VIC
1 4
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 1 kHz (b) BOM > f > 1 kHz (c) f = BOM (d) f > BOM
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6, 7
αVIO Temperature coefficient Distribution 8, 9
vs High-level
g output current 10,, 11
VOH High-level
g output voltage
g vs Supply voltage
g 12
vs Free-air temperature 13
vs Common-mode
Common mode input in ut voltage 14, 15
vs Differential input voltage
g 16
VOL Low level output voltage
Low-level
vs Free-air temperature 17
vs Low-level output current 18, 19
vs Supply
y voltage
g 20
AVD Differential voltage
g amplification vs Free-air temperature 21
vs Frequency 32, 33
IIB / IIO Input bias and input offset current vs Free-air temperature 22
VIC Common-mode input voltage vs Supply voltage 23
vs Supply
y voltage
g 24
IDD Supply current
vs Free-air temperature 25
vs Supply
y voltage
g 26
SR Slew rate
vs Free-air temperature 27
Normalized slew rate vs Free-air temperature 28
VO(PP) Maximum peak-to-peak output voltage vs Frequency 29
vs Free-air temperature 30
B1 Unity gain bandwidth
Unity-gain
vs Supply voltage 31
vs Supply
y voltage
g 34
φm Phase margin
g vs Free-air temperature 35
vs Capacitive loads 36
Vn Equivalent input noise voltage vs Frequency 37
φ Phase shift vs Frequency 32, 33
TYPICAL CHARACTERISTICS
ÎÎÎÎÎÎÎÎÎÎÎÎ
60 60
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
612 Amplifiers Tested From 4 Wafer Lots 612 Amplifiers Tested From 4 Wafer Lots
VDD = 5 V VDD = 10 V
50 TA = 25°C 50 TA = 25°C
P Package P Package
Percentage of Units – %
Percentage of Units – %
40 40
30 30
20 20
10 10
0 0
–5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5
VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – mV
Figure 6 Figure 7
ÎÎÎÎÎÎÎÎÎÎÎÎ
60 60
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
224 Amplifiers Tested From 6 Wafer Lots 224 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V VDD = 10 V
50 TA = 25°C to 125°C 50 TA = 25°C to 125°C
P Package P Package
Outliers:
Percentage of Units – %
Outliers:
Percentage of Units – %
30 30
20 20
10 10
0 0
– 10 – 8 – 6 – 4 – 2 0 2 4 6 8 10 – 10 – 8 – 6 – 4 – 2 0 2 4 6 8 10
α VIO – Temperature Coefficient – µV/°C α VIO – Temperature Coefficient – µV/°C
Figure 8 Figure 9
TYPICAL CHARACTERISTICS†
ÁÁÁÁÁ
5 16
ÎÎÎÎÎÎ
ÁÁÁÁÁ
VID = 100 mV VID= 100 mV
TA = 25°C 14
VOH – High-Level Output Voltage – V
ÎÎÎÎ
12
ÎÎÎÎÎÎÎÎ
VDD = 5 V
10
ÎÎÎÎ ÎÎÎÎ
3
VDD = 4 V
ÎÎÎÎ
8
VDD = 10 V
2 VDD = 3 V
6
ÁÁ ÁÁ
ÁÁ ÁÁ
4
VOH
VOH
1
ÁÁ 0
ÁÁ 2
0
0 –2 –4 –6 –8 – 10 0 – 10 – 20 – 30 – 40
IOH – High-Level Output Current – mA IOH – High-Level Output Current – mA
Figure 10 Figure 11
ÁÁÁÁ
SUPPLY VOLTAGE
16 VDD – 1.6
ÁÁÁÁ
VID = 100 mV
ÎÎÎÎ
IOH = – 5 mA
ÁÁÁÁ
14 RL = 100 kΩ VDD – 1.7
VOH – High-Level Output Voltage – V
VID = 100 mA
VOH – High-Level Output Voltage – V
TA = 25°C VDD = 5 V
12 VDD – 1.8
10 VDD – 1.9
ÎÎÎÎ
ÎÎÎÎ
8 VDD – 2
VDD = 10 V
6 VDD – 2.1
ÁÁ ÁÁ
ÁÁ ÁÁ
4 VDD – 2.2
VOH
VOH
ÁÁ 2
0
ÁÁ VDD – 2.3
VDD – 2.4
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 12 Figure 13
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
550
400
VID = – 100 mV
500 VID = – 100 mV
VID = – 1 V
350
450 VID = – 2.5 V
ÁÁ ÁÁ
400
ÁÁ ÁÁ
300
VOL
VOL
VID = – 1 V
350
300 250
0 1 2 3 4 0 1 2 3 4 5 6 7 8 7 10
VIC – Common-Mode Input Voltage – V VIC – Common-Mode Input Voltage – V
Figure 14 Figure 15
VID = – 1 V
VOL – Low-Level Output Voltage – mV
ÁÁ ÁÁ
300
VDD = 10 V
ÁÁ ÁÁ
200
200
VOL
VOL
ÁÁ 100
0
ÁÁ 100
0
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10 – 75 – 50 – 25 0 25 50 75 100 125
VID – Differential Input Voltage – V TA – Free-Air Temperature – °C
Figure 16 Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
ÁÁÁÁÁ
LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
ÁÁÁÁÁ
1 3
VID = – 1 V
ÁÁÁÁÁ ÎÎÎÎ
0.9 VIC = 0.5 V VID = – 1 V
ÁÁÁÁÁ ÎÎÎÎ
ÎÎÎÎ
VDD = 4 V 2
ÎÎÎÎ
0.6 VDD = 10 V
VDD = 3 V
0.5 1.5
0.4
ÁÁ ÁÁ
1
0.3
ÁÁ ÁÁ
VOL
VOL
ÁÁ ÁÁ
0.2
0.5
0.1
0 0
0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30
IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA
Figure 18 Figure 19
LARGE-SIGNAL LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION DIFFERENTIAL VOLTAGE AMPLIFICATION
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
500 500
ÎÎÎÎ
ÎÎÎÎ
TA = – 55°C
450 RL = 100 kΩ 450 RL = 100 kΩ
– 40°C
ÎÎÎÎ
VD – Large-Signal Differential
VD – Large-Signal Differential
400
Voltage Amplification – V/mV
Voltage Amplification – V/mV
400
0°C
ÎÎÎÎ
350 350
25°C VDD = 10 V
300 300
70°C
250 250
85°C
ÁÁ ÁÁ ÎÎÎÎ
200 125°C 200
ÁÁ ÁÁ ÎÎÎÎ
150 150
AVD
AVD
VDD = 5 V
ÁÁ ÁÁ
A
A
100 100
50 50
0 0
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 20 Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
VDD = 10 V TA = 25°C
VIC = 5 V
ÎÎ
1000
12
100
ÎÎ ÎÎ
IIB
10
10
ÎÎ IIO 8
ÁÁ
ÁÁ
4
I IB and IIO
ÁÁ
VIC
2
IIB
0.1 0
45 65 85 105 25
125 0 2 4 6 8 10 12 14 16
TA – Free-Air Temperature – °C VDD – Supply Voltage – V
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 22 Figure 23
600
DD – Supply Current – µ
DD – Supply Current – µ
ÎÎÎÎ
350
– 40°C
ÎÎÎÎ
500 300
VDD = 10 V
0°C 250
400
ÁÁ ÁÁ 200
ÎÎÎÎÎ
ÁÁ ÎÎÎÎÎ
25°C
300 VDD = 5 V
IIDD
ÁÁ ÁÁ
IIDD
70°C 150
200
125°C 100
100 50
0 0
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 24 Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
ÁÁÁÁÁ
VIPP = 1 V AV = 1
RL = 100 kΩ
ÁÁÁÁÁ
RL = 100 kΩ 0.8
0.8 VDD = 10 V
CL = 20 pF CL = 20 pF
VI(PP) = 5.5 V
ÎÎÎÎÎ
See Figure 1
SR – Slew Rate – V/ µ s
SR – Slew Rate – V/ µ s
TA = 25°C
0.7
ÁÁÁÁÁ
ÎÎÎÎÎ
See Figure 1
0.7
ÁÁÁÁÁ
ÎÎÎÎÎ
0.6 VDD = 10 V
VI(PP) = 1 V
0.6
0.5
0.5
ÁÁÁÁÁ
0.4
ÁÁÁÁÁ
ÁÁÁÁÁ
VDD = 5 V
0.4 VI(PP) = 1 V
0.3
ÁÁÁÁÁ
VDD = 5 V
VI(PP) = 2.5 V
0.3 0.2
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 26 Figure 27
1.4 10
ÎÎÎÎ
AV = 1
1.3 VI(PP) = 1 V 9
ÎÎÎÎ
VDD = 10 V RL = 100 kΩ
1.2 8 VDD = 10 V
CL = 20 pF
VDD = 5 V TA = 125°C
Normalized Slew Rate
7
1.1 TA = 25°C
TA = – 55°C
6
1
5
ÎÎÎÎ
ÎÎÎÎ
0.9 VDD = 5 V
4
0.8
ÎÎÎÎÎ
3
ÎÎÎÎÎ
0.7 RL = 100 kΩ
2
See Figure 1
0.6 1
0.5 0
–75 –50 –25 0 25 50 75 100 125 1 10 100 1000
TA – Free-Air Temperature – °C f – Frequency – kHz
Figure 28 Figure 29
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
ÁÁÁÁÁ ÁÁÁÁÁ
FREE-AIR TEMPERATURE SUPPLY VOLTAGE
ÁÁÁÁÁ ÁÁÁÁÁ
900 800
ÁÁÁÁÁ ÁÁÁÁÁ
VDD = 5 V VI = 10 mV
VI = 10 mV 750 CL = 20 pF
ÁÁÁÁÁ ÁÁÁÁÁ
800 CL = 20 pF TA = 25°C
B1 – Unity-Gain Bandwidth – kHz
600 600
550
500
500
B1
400 B1
450
300 400
– 75 – 50 – 25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
TA – Free-Air Temperature – C VDD – Supply Voltage – V
Figure 30 Figure 31
LARGE-SCALE DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 5 V
10 6 RL = 100 kΩ
VD – Large-Signal Differential
TA = 25°C
10 5 0°
Voltage Amplification
10 4
ÎÎÎ 30°
ÎÎÎ
Phase Shift
AVD
10 3 60°
10 2 90°
ÁÁ Phase Shift
ÁÁ
AVD
10 120°
A
1 150°
0.1 180°
0 10 100 1k 10 k 100 k 1M
f – Frequency – Hz
Figure 32
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
LARGE-SCALE DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
10 6 RL = 100 kΩ
TA = 25°C
AVD – Large-Signal Differential
10 5 0°
Voltage Amplification
ÎÎÎ
ÎÎÎ
10 4 30°
Phase Shift
AVD
10 3 60°
ÁÁ
10 2 90°
ÁÁ
Phase Shift
AVD
10 120°
ÁÁ 1 150°
0.1 180°
0 10 100 1k 10 k 100 k 1M
f – Frequency – Hz
Figure 33
VI = 10 mV VDD = 5 V
48° CL = 20 pF VI = 10 mV
TA = 25°C 43° CL = 20 pF
See Figure 3 See Figure 3
m – Phase Margin
m – Phase Margin
46°
41°
44°
ÁÁ ÁÁ 39°
ÁÁ ÁÁ
φm
φm
42°
37°
40°
38° 35°
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – C
Figure 34 Figure 35
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
CAPACITIVE LOAD
44°
VDD = 5 V
42° VI = 10 mV
TA = 25°C
40° See Figure 3
m – Phase Margin
38°
36°
ÁÁ
ÁÁ
34°
φm
32°
30°
28°
0 10 20 30 40 50 60 70 80 90 100
CL – Capacitive Load – pF
Figure 36
ÁÁ
FREQUENCY
ÁÁ
300
VDD = 5 V
nV/ Hz
ÁÁ
RS = 20 Ω
V n– Equivalent Input Noise Voltage – nV/Hz
ÁÁ
250 TA = 25°C
See Figure 2
200
150
100
50
Vn
0
1 10 100 1000
f –Frequency – Hz
Figure 37
APPLICATION INFORMATION
single-supply operation
While the TLC27M2 and TLC27M7 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27M2 and TLC27M7 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27M2 and TLC27M7 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
+
ǒ Ǔ
R3
VI
R1 R2
–
V
REF
V
DD R1 ) R3
+
VO V
O
+ V
REF
–V
R4
I R2
) V
REF
VREF
R3 C
0.01µF
–
Logic Logic Logic Power
Output + Supply
–
Power
Output + Logic Logic Logic Supply
APPLICATION INFORMATION
input characteristics
The TLC27M2 and TLC27M7 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at VDD – 1 V at TA = 25°C and at VDD – 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M2 and TLC27M7
very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M2 and
TLC27M7 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards
and sockets can easily exceed bias current requirements and cause a degradation in device performance. It
is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27M2 and TLC27M7 result in a very
low noise current, which is insignificant in most applications. This feature makes the devices especially
favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices
exhibit greater noise currents.
–
–
VO VI
VI
+ VO –
+
VO
+
VI
output characteristics
The output stage of the TLC27M2 and TLC27M7 is designed to sink and source relatively high amounts of
current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current
capability can cause device damage under certain conditions. Output current capability increases with supply
voltage.
All operating characteristics of the TLC27M2 and TLC27M7 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
APPLICATION INFORMATION
2.5 V
–
VO
+ TA = 25°C
VI
CL f = 1 kHz
VI(PP) = 1 V
– 2.5 V
APPLICATION INFORMATION
VDD
VI + RP
IP
– VO
IP C
R2
R1 IL RL
–
* VO
+
V VO
) L ) IP
R DD
P I I
+
F
IP = Pullup current required by
the operational amplifier
(typically 500 µA)
Figure 42. Resistive Pullup to Increase VOH Figure 43. Compensation for Input Capacitance
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic-discharge protection
The TLC27M2 and TLC27M7 incorporate an internal electrostatic-discharge (ESD) protection circuit that
prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care
should be exercised, however, when handling these devices as exposure to ESD may result in the degradation
of the device parametric performance. The protection circuit also causes the input bias currents to be
temperature dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27M2 and
TLC27M7 inputs and outputs were designed to withstand – 100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
APPLICATION INFORMATION
1N4148
470 kΩ
100 kΩ
5V
1/2
– TLC27M2
47 kΩ VO
100 kΩ +
R2
68 kΩ
1 µF 100 kΩ
C2
R1 C1 2.2 nF
68 kΩ 2.2 nF
NOTES: VO(PP) ≈ 2 V
f
O
+ 2p ǸR1R2C1C2
1
5V IS
1/2
VI + TLC27M7
– 2N3821
NOTES: VI = 0 V to 3 V
I
S
+
VI
R
APPLICATION INFORMATION
5V
Gain Control
1 MΩ
10 MΩ
VDD
–
1/2
1 kΩ TLC27M2
–
+
1/2 VO
TLC27M2 +
VREF
15 nF
100 kΩ
150 pF
NOTES: VDD = 4 V to 15 V
Vref = 0 V to VDD – 2 V
APPLICATION INFORMATION
1 MΩ
VDD
33 pF
–
VO
+ 1/2
TLC27M2
1N4148
100 kΩ
100 kΩ
NOTES: VDD = 8 V to 16 V
VO = 5 V, 10 mA
5V
1 MΩ
0.1 µ F
VI + 0.22 µF
VO
– 1/2
TLC27M2
1 MΩ
100 kΩ
100 kΩ
10 kΩ
0.1 µF
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