ECE 301 1

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1

TABLE OF CONTENTS

Experiment TITLE Page No.

No.

COURSE OUTLINE 2
INTRODUCTION AND SAFETY REMINDERS 4
1 Introduction to Semiconductor Devices
a. Semiconductor Component Identification 6
b. Control of a Semiconductor Switch

2 Diode DC Characteristics
 Diode DC Characteristics 14
3 Rectifiers
a. Half wave Rectification 24
b. Full Wave Diode Bridge Rectification

4 Power Supply Filtering and Voltage Doubler

a. Power Supply Filtering 39
b. Voltage Doubler

5 The Diode Limiter

 Diode Waveshaping 49
6 Zener Diode & Voltage Regulation 58
7 BJT Characteristics and Biasing

a. Testing the Junctions of a Transistor

b. PNP Transistor Current Control Circuit
c. Transistor Load lines and Gain 72
d. Collector Current vs. Base bias
e. Transistor DC Circuit Voltages
f. Transistor Load lines

8 COMMON BASE CIRCUIT (Small Signal Amplifier)

a. Circuit Location and Identification 108
b. Common Base Circuit DC Operation
c. Common Base Circuit AC Operation
9 COMMON EMITTER CIRCUIT (Small Signal Amplifier)
a. Common Emitter Circuit DC Operation 127
b. Common Emitter Circuit AC Operation
10 COMMON COLLECTOR CIRCUIT (Small Signal Amplifier)
a. Common Collector Circuit DC Operation 142
b. Common Collector AC Operation
11 JUNCTION FET (JFET) Fundamentals
a. Component Location and Identification 161
b. JFET Operating Characteristics
c. The Effect of Gate bias on pinch off
d. JFET Dynamic Characteristic Curves
12 JFET Amplifier
a. JFET Amplifier DC Operation 179
b. JFET AmplifierAC Operation
c. JFET Current Source DC Operation
13 Dual Gate MOSFET Fundamentals
a. Zero Bias Characteristic of MOSFET 193-204
b. MOSFET Mode of Operation
ECE 301 2

COLLEGE OF ENGINEERING AND ARCHITECTURE

ELECTRONICS AND COMMUNICATIONS ENGINEERING DEPARTMENT

ECE Course Outline / Guide:

Course Number: ECE 301
Course Title: ELECTRONICS 1, LAB
Experiments to investigate the ff. theories: Elementary semiconductor
theory, diode and transistor models; diode circuit analysis and applications;
Course Description transistor biasing; small signal analysis; large signal analysis; differential
amplifier, transistor amplifiers; transistor switch.

Credit Units 1units lab

Number of Contact Hours
per week 3 hours per week

Pre-requisite/s ECE 221

Co-requisite/s ECE 311
o Active involvement during Experiments
Course Requirements: o Practical Exam / Quizzes
o Major Exams

Textbook/ References: ECE 301 Lab. Manual

 MA = 60%LabE1 + 40%LabME
Grading System:  FA = 50%MA + 30%LabE2 + 20%LabFE

Course Outline:
DAY TOPICS/ACTIVITIES Assignment No.
1  Orientation: School Policies, Grading System and Course outline Read Expt. No. 1
distribution
 Orient the students with the operation and safety of equipments to
be used in the experiments.
2  Discuss the procedure and perform Experiment No. 1- Introduction Read Expt. No. 2
to Semiconductor Devices Make Expt No. 1
 Interpretation of the experiment results
3 Prelim Exam
 Deadline –Final Report for Experiment No. 1 Read Expt. No. 3
 Discuss the procedure and perform Experiment No. 2- Diode DC Make Expt No. 2
Characteristics
 Interpretation of the experiment results
4  Deadline –Final Report for Experiment No. 2 Read Expt. No. 4
 Discuss the procedure and perform Experiment No. 3- Rectifiers Make Expt No. 3
 Interpretation of the experiment results
5  Deadline –Final Report for Experiment No. 3 Read Expt. No. 5
 Discuss the procedure and perform Experiment No. 4- Power Make Expt No. 4
Supply Filtering and Voltage Doubler
 Interpretation of the experiment results
6  Deadline –Final Report for Experiment No. 4 Read Expt. No. 6
 Discuss the procedure and perform Experiment No. 5- The Diode Make Expt No. 5
Limiter Study for the
 Interpretation of the experiment results Midterm Exam
7 Midterm Exam
8  Deadline –Final Report for Experiment No. 5 Read Expt. No. 7
 Discuss the procedure and perform Experiment No. 6- Zener Diode Make Expt No. 6
and Voltage Regulation
 Interpretation of the experiment results
9  Deadline –Final Report for Experiment No. 6 Read Expt. No. 8
 Discuss the procedure and perform Experiment No. 7- BJT Make Expt No. 7
Characteristics and Biasing
 Interpretation of the experiment results
ECE 301 3

10  Deadline –Final Report for Experiment No. 7 Read Expt. No.9

 Discuss the procedure and perform Experiment No. 8- Small Signal Make Expt No. 8
Amplifier-Common Base Circuit
 Interpretation of the experiment results
11 Pre-final Exam Read Expt. No. 10
 Deadline –Final Report for Experiment No. 8 Make Expt No. 9
 Discuss the procedure and perform Experiment No. 9- Small Signal
Amplifier-Common Emitter Circuit
 Interpretation of the experiment results
12  Deadline –Final Report for Experiment No. 9 Read Expt. No. 11
 Discuss the procedure and perform Experiment No. 10- Small Make Expt No. 9
Signal Amplifier-Common Collector Circuit
 Interpretation of the experiment results
13  Deadline –Final Report for Experiment No. 10 Read Expt. No. 12
 Discuss the procedure and perform Experiment No. 11- Junction Make Expt No. 11
Field Effect Transistor Fundamentals
 Interpretation of the experiment results
14  Deadline –Final Report for Experiment No. 11 Read Expt. No. 13
 Discuss the procedure and perform Experiment No. 12- JFET Make Expt No. 12
Amplifier
 Interpretation of the experiment result
15  Deadline –Final Report for Experiment No. 12 Prepare for the
 Discuss the procedure and perform Experiment No. 13- Dual Gate Final Exam
MOSFET Fundamentals
 Interpretation of the experiment result
16  COMPILATION OF FINALREPORTS
Final Exam

NOTE:
1 Semester = 18 weeks
LESS Holidays = 2 weeks

Net Weeks for Classes/Major Exams = 16 weeks

16 weeks x 1 days per week = 16 days of classes with major exams

ECE 301 4

ELECTRONICS ENGINEERING DEPARTMENT

ANALOG ELECTRONICS LABORATORY

ECE 301
ELECTRONICS 1

INTRODUCTION AND SAFETY REMINDERS

You must be familiar with the information in this introduction in order to complete your
experiments successfully. Study these instructions before beginning your iab work. If you have
problems performing an experiment, review the following rules before calling your instructor.
CONNECTING THE CIRCUIT BOARD TO THE BASE UNIT
Set up the power sources before you insert a circuit board in the base unit ALWAYS check the
source voltages because someone else may have changed these values. NEVER insert or
remove a circuit board when power is applied to the base unit
A. Turn on the positive and negative power sources. Use your multimeter to measure
the voltages in the following steps even if your power sources have built-in
voltmeters. Your multimeter is more accurate than other meters.
B. Measure the positive voltage source at its output terminals and adjust to +15.0
Vdc if necessary. Measure the negative power source, and adjust its output to -
15.0 \(dc if necessary. The tolerances of acceptable answers are based on the
accuracy of these voltages to within ± 3 percent.
C. Turn off the power sources.
D. Open the connector in the base unit by turning the knob on the right side of the
base unit away from you. Do not use force; the knob should turn with reasonable
pressure.
E. Insert the trainer (circuit board) by sliding it along the grooves in the base unit. Be
sure the connector fits all the way into the slot at the back of the base unit.
F. Lock the base unit connector by turning the knob toward you about a quarter-turn.
G. Refer below to determine if you need the GENERATOR BUFFER. If it is required,
plug it into the area provided on the circuit board.
H. Turn on the power sources.
THE GENERATOR BUFFER:

Some of the exercises you perform with this board require the use of a waveform generator. If your
signal generator has a 50-ohm output impedance, the GENERATOR BUFFER is not required. Simply
connect the generator common lead (black) directly to the lower GEN (common)"terminal of the circuit
block you are studying. Also connect the signal output lead (red) to the upper GEN (signaI ) terminal.
These connections should be indicated in an illustration that accompanies the exercise.
If your generator does not have a 50-ohm output impedance, you need to use the GENERATOR
BUFFER, which is optionally supplied with the trainer. Before applying power, plug the GENERATOR
BUFFER into the area of the circuit board labeled FOR GENERA TOR BUFFER. Connect your signal
generator leads to the black (common) and blue (signal) terminals marked IN on the module. Use two of
the connecting wires supplied with the trainer to connect the black OUT terminal to the indicated
generator common point of the circuit block you are studying. Connect the blue (signal) OUT terminal to
the upper GEN terminal of the circuit block. When you have made these connections, you may ignore
the buffer and adjust the signal generator controls as directed in the exercise.

CIRCUIT MODIFICATION SWITCHES

The base unit of the training system is equipped with 20 circuit modification switches (called
CM switches in the manual). These switches change component values or introduce short or
open circuits into the circuit blocks on the trainer. The following rules apply when you use a
CM switch:
A. A CM switch is off when the switch hang Ie is toward you and on when it is away.
B. You should never have more than one CM switch on at anyone time.
C. The experiment procedures or review questions will tell you when to turn on a CM
switch. ALWAYS turn off the switch unless you are explicitly told to leave it on.
ECE 301 5

D. When a review question requires that you turn on a CM switch, be sure that the circuit
board is connected and power voltages are set as described previously. Make sure that
all other CM switches are off.

MEASUREMENTS AND MEASUREMENT TOLERANCES

Appendix C offers a review of measurement methods, and Appendix D

provides information about measurement tolerances. PLEASE REFER TO YOUR
INSTRUCTOR regarding this Appendices. You should read it if you have questions
about measurement procedures in this manual. Your results are acceptable if they
are within the tolerances.
Unless stated otherwise in a procedural step, all
measurements in this volume are acceptable if they are
within ±30 percent of nominal values.

MISCELLANEOUS INFORMATION

A. Circuit boards that require low level signals from the signal generator
usually have an ATTENUATOR circuit block. The ATTENUATOR divides
the signal generator output by 10 to ease adjustment of the generator
amplitude. If you use the ATTENUATOR, be sure to measure the signal
amplitude at the output of the ATTENUATOR, not at the output of the
generator or the GENERATOR BUFFER.

B. The base unit of the FACET. system has 12 fault switches under a locked
cover. During the troubleshooting unit, your instructor will use these
switches to introduce problems into the circuit blocks, and you will
troubleshoot these faults. If you measure unreasonable values in an
exercise, even after double checking your circuit, CM switches, and
power voltages, ask your instructor to verify that all fault switches are off.

C. In general, your F.A.C.E.T. setup will be used for one or more review
questions, so you should not disconnect it immediately after the
procedure. When you have completed your work for the day, remove all
circuit board connections, and turn off the power sources before opening
the base unit connector and removing the circuit board from the base unit.
Stow the circuit board and all connectors as directed by your instructor. .
ECE 301 6

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 1
INTRODUCTION TO SEMICONDUCTOR DEVICES

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

EXPT. 1A – SEMICONDUCTOR COMPONENT IDENTIFICATION

I. OBJECTIVE:

 To be able to identify various semiconductor devices and verify the knowledge by

locating several devices in the trainer.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T Base Units
 Power Supply, 15 Vdc ( 2 required)
 SEMICONDUCTOR DEVICES CIRCUIT BOARD

III. THEORY:

Semiconductor devices can be grouped into many categories. The first classification is diodes. All diodes
have a common characteristic: two electrical connections. Diodes are sometimes called two-terminal
devices. The word diode includes the prefix di-, which means two.
Most semiconductor diodes are constructed from germanium or silicon, although some very high-
frequency diodes and certain other diodes are constructed with special materials or methods. Common
diodes have a single PN junction, and an electrical connection is attached to each type of material. The P
type material in a diode is called the anode, and the N type material is called the cathode. Figure 1-7(a)
shows the physical construction of a common diode and Figure 1 -7(b) shows its corresponding
schematic symbol. Diodes are usually identified by the letters CR (such as CR15) on schematic drawings.

(a) DIODE CONSTRUCTION

CA THODE ANODE

(b) DIODE SCHEMATIC SYMBOL

CATHODE (NOTE THE Z-SHAPE) ANODE

(c) ZENER DIODE SCHEMATIC SYMBOL
ECE 301 7

CATHODE ANODE

(d) LIGHT-EMITTING DIODE SCHEMATIC SYMBOL

Figure 1 -7. Diode symbols.

Diodes are designed to perform specific tasks. The physical size of the semiconductor pellet
and the outer package are mi3de larger fpr diodes designed to pass high currents. Diode
packages are constructed from plastic, glass, or a combination of metal and glass or ceramic.
All diode packages are tightly sealed to prevent contamination of the semiconductor by
airborne gasses or moisture. Figure 1-8 illustrates several diode packages. Diode packages
identify the cathode end with a dot or band of color. High current diodes are usually stamped
with a diode schematic symbol.

The diode family includes some devices which have become more familiar by other names. For
example, light-emitting diodes are usually called LEDs, and a type of constant voltage diode is
commonly called a zener. Figure 1-7 shows the schematic symbols for these devices, and Figure 1-
8 shows some typical packages for these devices. Note that zener diodes are in packages that are
identical to those of ordinary diodes [Figures 1-8(a), (b), and (c)] and that the cathode of typical
LED packages is the shorter of the two leads.
The second major semiconductor category, transistors, can be divided into two major families.
Field-effect transistors are described in another volume; this volume provides information on
junction transistors, or bipolar transistors. Junction transistors have three terminals and, in general,
function by allowing one current to control a second current. Because the controlling signal can be
ECE 301 8

weaker than the controlled current, transistors have the very important ability to amplify signals, a
property called gain.
The word transistor was formed by combining the word resistor with the prefix trans-, which means
across or through. In effect, transistors operate by controlling current that passes through the
resistance of a semiconductor.
Junction or bipolar transistors are constructed from N type and P type silicon or germanium
material joined into three regions. The two types of transistors can be N-P-N or P-N-P. Note that in
either case, two junctions are present, as indicated by the dashes. The dashes are not usually used
when describing transistor types-the transistors are referred to simply as PNP or NPN. Figure 1-9
illustrates both types of transistors with their schematic symbols. As indicated on the figure, one
end of the transistor is called the emitter, the middle region is called the base, and the other end is
called the collector. Each of these elements of a transistor has an electrical connection to the
outside of the package. Note that NPN transistors are schematically drawn with the emitter arrow
pointing away from the base, while PNP transistors have the emitter arrow pointing toward the
base.

Because many packages are available for transistors, stating a simple rule for determining
which lead is the base, which lead is the emitter, and so forth, would be nearly impossible. The only
sure way to identify the leads of an unfamiliar transistor is to refer to manufacturers' diagrams or to
standard packaging diagrams. You must confirm transistor lead connections, for a transistor
connected improperly into a circuit can be destroyed.
Like diodes, transistors are designed for specific applications. Power transistors are physically
larger than transistors designed to operate at low power levels. Some transistors are designed to
work well at very high frequencies, while still others are designed for high voltage circuits.
Transistors are usually identified by the letter Q (such as Q7) on schematic drawings.
Transistor packages are made from plastic or metal/glass combinations. They are tightly sealed for
the same reasons diode packages are tightly sealed. Figure 1-10 shows a selection of transistor
packages; many other packages are also available.
ECE 301 9

IV. PROCEDURE:

1. Locate the SEMICONDUCTOR DEVICES circuit board. You do not need to turn on the
power sources or connect the circuit board to the base unit for this procedure.
2. What type of packaging material is used for the diodes in the DIODES AND 1/2 WAVE
RECTIFICATION circuit block?

____________________________________________________________

___________________________________________________________
3. Which end of CR1 is at the top in this circuit block?

___________________________________________________________

_____________________________________________________________

4. What part of the symbol for CR1 in the ZENER DIODE REGULATOR circuit block differs
from the symbol for"CR1 in the DIODES AND 1/2 WAVE RECTIFICATION circuit block?
This difference indicates that the first diode is what kind of diode?
____________________________________________________________

___________________________________________________________

5. What type of transistor is used in the TRANSISTOR LOAD LINES AND GAIN circuit block
PNP or NPN?
_____________________________________________________________

____________________________________________________________

6. The schematic symbol for Q1 on the TRANSISTOR LOAD LINES AND GAIN circuit block
differs from the symbol for 01 on the PNP DC BIAS circuit block in that the emitter arrow in
the latter circuit block is pointing toward what? What kind of transistor is indicated by the
arrow?

____________________________________________________________

_____________________________________________________________

7. What kind of diode does the symbol in the PNP DC BIAS circuit block indicate?
ECE 301 10

____________________________________________________________

_____________________________________________________________

8. What packaging material is used for Q2 in the TRANSISTOR JUNCTION circuit block?

____________________________________________________________

_____________________________________________________________

V. EVALUATION:

1. Semiconductor packages are tightly sealed to

a. improve electrical conductivity
b. Protect the semiconductor from contamination.
c. maintain a high vacuum.
d. prevent the escape of free electrons

2. How many electrical connections do transistors have?

a. between the emitter and collector.
b. always N type material.
c. always P type material.
d. None of the above

3. The base region of a junction transistor is

a. between the emitter and collector.
b. always N type material.
c. always P type material.
d. None of the above

4. The two elements of a diode are the

a. anode and cathode.
b. emitter and cathode.
c. base and cathode.
d. emitter and collector.

5. A junction transistor is made with

a. three junctions.
b. two doped regions.
c. pure silicon or germanium.
d. two junctions.

VI. CONCLUSION
ECE 301 11

EXPT. 1B – CONTROL OF A SEMICONDUCTOR SWITCH

I. OBJECTIVE:

 To be able to turn a light-emitting diode on and off using a transistor as a switch and to
verify the results by observing the illumination of an LED.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T Base Units
 Power Supply, 15 Vdc ( 2 required)
 SEMICONDUCTOR DEVICES CIRCUIT BOARD

III. THEORY:

Transistors are used in thousands of ways to perform thousands of different tasks

every day. Transistors in a television receiver are used to amplify the antenna signal, which
may be only a few millionths of a volt, until it reaches the strength necessary to control the
picture tube display. Transistors in computer circuits can perform millions of arithmetic
operations in a single second. In short, transistors can perform so many jobs that an attempt
to list just the "regular" uses of these devices would require hundreds of pages.
Once you learn how transistors operate, however, you will easily understand from a
few basic rules how even complicated circuits function. In this exercise, we won't try to
explain the operation of a transistor; instead, we will demonstrate how a transistor may be
used to switch a current on or off.
A second concept that will be demonstrated is the use of a light-emitting diode (LED)
to transform an electric current into visible light. Incandescent lamps produce light by heating
a wire (the filament) to a very high temperature in a glass bulb filled with an inert gas.
Because LEDs produce light at low temperatures and without delicate filaments, they are
very long-lasting. A complete understanding of how an LED operates requires a study of
quantum mechanics, but you can easily understand the basic idea of an LED without
knowing any special physics (just as you can use a light bulb without understanding all the
principles of electricity).
The electrons in an atom normally are found at specific, stable energy levels. The electrons
in the atoms of an LED are temporarily excited into higher energy levels by the flow of an
electric current. When these electrons return to their stable energy levels, they release the
extra energy in the form of tiny packets of light called photons. Individually, photons
represent such tiny amounts of light that they would be invisible except to very sensitive
measuring equipment.
In an LED, hundreds of millions of electrons continuously switch back and forth between
stable and excited levels, and easily visible light is produced. The materials and doping
concentrates are selected to maximize light production in an LED; otherwise, an LED differs
very little from an ordinary diode. The packaging material for LEDs is clear or tinted
translucent plastic or glass so that, of course, the light is not blocked from view. Although the
packaging is usually tinted to emphasize a color, the color is primarily determined by the
materials used to manufacture the diode.
IV. PROCEDURE:

1. Adjust the dc power sources to +15 Vdc and -15 Vdc. Turn the power sources off.
Insert the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn
on the power sources at this time.

2. Locate the PNP DC BIAS circuit block, and connect the circuit shown in Figure 1-11
(a).

Figure 1-11. Transistor switch-LED demonstration circuit.

ECE 301 12

3. Turn the power sources on. Is the LED on or off?

__________________________________________________________

4. Move the two-post connector as shown in Figure 1-11 (b). Is the LED on or off?

_________________________________________________________

5. Inserting the two-post connector in step 4 provided a current to the base of 01. Is the
transistor on or off when base current is provided?

__________________________________________________________

6. Observe the LED as you insert and remove the two-post connector a few times. Can
you compare the operation of the transistor with an electrically controlled switch?

__________________________________________________________

7. During a later study of this circuit, you will find that the current into the base through
R1 [when the two-post connector is inserted as in Figure 1-11 (b)] is about 1.4 mA.
The current through the LED and the collector of 01 is about 13 mA when the
transistor is on. Does the transistor also provide current amplification?

_________________________________________________________

8. Do not turn off the power sources. The F.A.C.E.T. setup will be used for a review
question.

V. EVALUATION:
1. Locate the PNP DC BIAS circuit block on the SEMICONDUCTOR DEVICES circuit
board. Connect the circuit shown in Figure 1-12 and note that the LED is on. Place
CM switch 10 in the ON position to connect the base of 01 to its emitter. The LED
goes out because
a. no current flows through R1.
b. the current through R1 is diverted to common.
c. Q1 has been shorted from collector to emitter.
d. None of the above.

Figure 1 -1 2. Transistor - LED review circuit.

Turn CM switch 10 and the power sources off. Remove all circuit board
connections.
2. The color observed when an LED is lit is
a. always red.
b. primarily determined by the current flow.
c. primarily determined by the package color.
d. primarily determined by the materials used in the diode.
ECE 301 13

3. The primary purpose of Q1 in this exercise is to

a. switch current on or off.
b. limit the current through the LED.
c. increase the current through the LED.
d. None of the above.
4. An LED produces light because
a. a small filament glows when current flows.
b. the semiconductor gets very hot.
c. photons are emitted as electrons release energy.
d. it is made of fluorescent materials.
5. Compared with incandescent lamps, LEDs are
a. more resistant to breakage.
b. cooler in operation.
c. longer lasting.
d. All of the above.

VI. CONCLUSION
ECE 301 14

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 2
DC DIODE CHARACTERISTICS

______________________________ _____________________________
NAME COURSE & YEAR

________________________________ _____________________
GROUP DATE

I. OBJECTIVE:

 To be able to utilize a diode operating curve to test a diode by using a typical

diode circuit and verify the results with a multimeter.

II. APPARATUS AND MATERIALS

- F.A.C.E.T.Base Unit
- SEMICONDUCTOR DEVICES Circuit Board
- Multimeter
- Oscilloscope, dual trace
- Generator, sine wave

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this experiment. Measured
values will differ from nominal due to normal circuit and instrument variations. Your
measurements in the experiment will be acceptable if your power voltages and circuit
measurements lie within the following ranges from nominal unless otherwise noted in a
procedure step:
External power source settings: +15 Vdc = ± 3 percent
-15 Vdc = ± 3 percent

POSITIVE SUPPLY and NEGATIVE SUPPLY settings: Stated value: ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope): ± 8 percent

III. THEORY:

Check valves in piping systems Figure 2-1 (a)] allow the passage of fluid or gas in one direction
only. Semiconductor diodes, one of which is shown in Figure 2-1 (b), are the electronic
equivalent to check valves. They permit the flow of electrons in only one direction. Most diodes
used today are semiconductor junction diodes.
ECE 301 15

Figure 2-1. Check valve and diode comparison

When N type semiconductor material is joined to P type material, a depletion region is

formed near the junction, as shown in Figure 2-2(a). The depletion region develops
when a few electrons from the N type material migrate into the P type material and
when a few positive charges from the P type material migrate into the N type material.
These charge migrations partially neutralize the crystal in an area very close to the
junction. As a result, an additional force is required to pass current through the junction,
just as the spring tension on a check valve must be overcome by sufficient pressure to
allow the passage of fluid.

Figure 2-2. Junction diode showing depletion region

The extra force generated at the depletion region of a semiconductor junction is the
barrier voltage, which is determined by the basic semiconductor material. The barrier voltage for
germanium semiconductors is about 0.3 volts, and for silicon-based semiconductors it is about
0.7 volts. You may think of the barrier voltage as a small battery opposing current flow through
an ideal diode, as shown for the silicon diode in Figure 2-2(b). This voltage. called the forward
voltage drop (V F) subtracts from the circuit voltage when the diode conducts.
One can easily visualize the operation of the check valve shown in Figure 2-1 (a). When
ECE 301 16

pressure is applied from the left, the check ball is moved to the right against the pressure of the
spring, and fluid moves through the space around the ball. If pressure is applied from the right, it
merely adds to the pressure of the spring and seals the ball more tightly against the flow of fluid.
Operation of the diode shown in Figure 2-3(a) is a little more difficult to visualize. When a
negative potential from an external source is applied to the right side of the diode, electrons in
the N type material of the diode cathode are forced closer to the junction. Similarly, the positive
charges in the P type material of the diode anode are attracted toward the junction by the
increased negative charge across the barrier. When the applied voltage is sufficient to
overcome the barrier voltage, the barrier width is effectively reduced, and electrons move
across the junction toward the positive terminal of the voltage source. As long as this potential
exceeds the barrier voltage, the electrons that leave the semiconductor are continuously
replaced by electrons that arrive from the voltage source. At this time. the diode is forward
biased, or in its on state.

Figure 2-3. Semiconductor diode with bias voltages applied

When the external potential is removed, the negative and positive charges in the N
and P type materials return to their original positions, except for the few charges in the
depletion region. This action is due to the fixed locations of the impurity atoms in the
crystal's structure.
When the external potential is reversed, as shown in Figure 2-3(b), a positive voltage
is applied to the cathode and a negative voltage is applied to the anode. Electrons in the N
type material are attracted away from the junction toward the positive terminal of the voltage
source. Positive charges in the P type material are also attracted away from the junction, but
they are attracted toward the negative terminal of the voltage source. These charge
movements increase the width of the depletion region. The diode is reverse biased (in its off
state) under these conditions, and almost no current flows.
As the reverse bias voltage increases, the depletion region widens further and
continues to block the passage of current until the diode's breakdown rating is exceeded.
Diodes, like check valves, are designed to operate within a limited range of reverse
pressures. If an ordinary diode is subjected to reverse voltages that exceed its breakdown
voltage limits, the diode will be destroyed. This important diode characteristic is also called
the peak inverse voltage (PIV) rating. Circuit designers are careful to select diodes with PIV
ratings that are two (or more) times higher than any reverse voltages normally present in a
circuit.
If an ac voltage large enough to overcome the barrier voltage is applied to a diode,
the diode conducts during alternations when the voltage is in the forward bias direction. The
diode can not conduct during alternations when it is reverse biased. The resulting current is
a pulsating dc; that is, current flows in one direction or not at all. The process of converting
an ac voltage to a pulsating dc voltage is rectification, one of the many applications of
semiconductor diodes.
Diodes are also used to perform many other tasks in modern electronic systems, so
they are available in different types of packages. Diodes designed to withstand high reverse
voltage or to pass large currents in the forward direction are often quite physically large.
Some diodes designed for use in logic gating or small signal detection circuits are less than
one-eighth of an inch long. Diodes are designed for specific operating conditions, and if
these ratings are exceeded, the diode may be destroyed.
Diode manufacturers publish application information to help circuit designers select
the most suitable type. Diode types are generally standardized, and most common diode
types begin with 1N, such as 1N829A or 1N4002. The cathode end of a diode is usually
identified by a color dot or band, although some large diode packages are imprinted with the
diode schematic symbol indicating the anode end as well as the cathode end. Diodes are
ECE 301 17

usually identified with CR (crystal rectifier) on schematic drawings (CR1, for example).
NEW TERMS AND WORDS
o anode - the end of a diode doped with electron-deficient material. The anode must
be positive with respect to the cathode for conduction to take place.
o barrier voltage - the force resulting from the depletion region at a PN junction. The
barrier voltage must be overcome by the forward bias voltage before current can
flow in a diode.

o breakdown voltage - the reverse voltage that causes a diode to conduct heavily and
destructively in the "wrong" direction. Diodes should be selected to have a
breakdown voltage greater than any normally-applied reverse voltage.

o cathode - the end of a diode doped with excess electron material. The cathode must
be negative with respect to the anode for conduction to take place.

o characteristic curve - a graphic representation of diode current flow versus diode

voltage drop.

o depletion region - a partially neutralized region that occurs at a PN junction due to

charge migration across the junction

o dynamic forward resistance (rf) - the apparent resistance of a conducting diode;

calculated from a measured change in diode voltage drop divided by a measured
change in current.

o forward bias -the condition in which the cathode of a diode is negative with respect
to its anode, and forward current flows.

o forward voltage drop (VF) - the nearly constant voltage that is developed across a
conducting diode.

o front-to-back ratio - the resistance of a reverse biased diode divided by the

resistance measured when the diode is forward biased.

o half-wave rectification - rectification in which output current flows only during half-
cycles of the ac input.

o heat sinks - metal plates, often having vanes or fins, designed to remove heat from
a semiconductor quickly and efficiently.

o leakage current - the very small current that flows through a reverse biased diode.

o minority carriers - free electrons in P type material. and holes (positive charges) in N
type material. Minority carriers are caused by the presence of tiny quantities of
natural impurities in the base semiconductor material. They are responsible for most
reverse (leakage) current through a semiconductor.

o peak inverse voltage (PIV) - the maximum reverse voltage that can be applied to a
diode without causing damage. This voltage is usually a little less than the diode's
breakdown voltage.
o pulsating dc - the rectifier output puIses of one polarity that correspond to half-
cycles of the rectifier ac input voltage when the diode is forward biased.

o rectification - the process of converting an alternating current into a pulsating direct

current.

o reverse bias - the application of a negative voltage on the anode of a diode with
respect to the cathode. .

o reverse recovery time (trr) - the time required for a diode to stop conducting after
forward bias is removed. Reverse recovery time is due primarily to stored charges.

o ripple - the pulsations appearing in the output voltage of a rectifier circuit.

o stored charges - positive and negative charges temporarily existing in a forward

biased semiconductor due to current flow. Stored charges reduce the efficiency of
common semiconductors at high frequencies because they increase the time
required for a junction to switch from the forward to the reverse biased state.
ECE 301 18

DIODE DC CHARACTERISTICS:
A diode operating curve describes the current flow through the diode for a complete
range of applied voltages. This data is presented in the form of a graph called a dc
characteristic curve, shown in Figure 2-4. The part of the graph to the right of the vertical
axis describes diode operation when the diode is forward biased (cathode negative with
respect to anode), while the part of the curve to the left of the vertical axis shows the reverse
bias characteristics (cathode positive with respect to anode).

Figure 2-4 Silicon diode DC Characteristic Curve

The horizontal voltage scale to the. right of the graph center point indicates the
voltage across the diode when forward bias is applied. This scale is usually calibrated from
fractions of a volt up to a few volts.
The vertical forward current scale above the graph center point indicates current
through the forward-biased diode. It is usually marked in mjlliamps or in amps. The
magnitude of this current, determined by the type Of diode, ranges from a few milliamps for
signal diodes up to hundreds of amps for high power diodes.
The portion of the graph to the left of center shows the reverse bias characteristics of
the diode. The horizontal reverse voltage scale to the left of center is marked in tens,
hundreds, or even thousands of volts, depending on the type of diode.
The vertical reverse current scale below the center point is most often calibrated in
picoamps or microamps. This current range typically depends on the physical size of the
diode; the greater the diode's junction area, the greater the reverse current.
When a small forward voltage is applied to a silicon diode (between 0 and 0.5 volts
on Figure 2-4), almost no current flows because the barrier voltage has not been reached.
As the forward biasing voltage increases, the barrier voltage is overcome, and forward
current rapidly increases. For the diode represented in this illustration, conduction begins
when forward voltage reaches approximately 0.55 volts. The characteristic curve for a
germanium diode would indicate conduction beginning at a lower forward voltage. Note that
after conduction begins, the voltage across the diode increases only a little as current
increases. This nearly constant voltage is the forward voltage drop (VF).
When the diode is reverse biased, the characteristic curve lies almost along the
horizontal axis of the graph. The reason is that as reverse voltage increases from zero, a
normal, very small leakage current flows in the reverse direction. Leakage current results
from the presence of minority carriers in both the anode and cathode regions of the diode.
Minority carriers consist of holes (positive charges) in the cathode region and free
electrons in the anode region. They occur due to the virtual impossibility of manufacturing
semiconductors of absolute purity. A very small number of impurities remain in the silicon or
germanium material before doping, and some "of these natural impurities are of the "wrong"
type. Modern diodes are carefully constructed, however, so they limit leakage currents to
very small values.
As reverse voltage continues to increase, a point of reverse breakdown voltage is
reached. At this point, diode current begins to increase rapidly in the reverse direction. This
current is labelled breakdown current in Figure 2-4. The increase in breakdown current is
caused by the high reverse voltage "punching through" the diode junction and breaking
down the diode's structure. If the reverse voltage reaches this level in normal operation, the
ECE 301 19

diode may be destroyed.

We may conveniently, but not quite accurately, consider the forward voltage drop of
a diode to be a constant value (0.3 volts for germanium diodes, 0.7 volts for silicon diodes).
The forward voltage drop actually increases as forward current increases, and it is affected
to a lesser extent by temperature changes. Because forward voltage does increase as
current increases, diodes have a characteristic called dynamic forward resistance (rf), often
simply called forward resistance. Figure 2-5 shows an expanded part of the diode dc
characteristic curve that illustrates the forward resistance of a high power diode family
operating at a junction temperature of 25 degrees Celsius (77 degrees Fahrenheit).
You can calculate dynamic forward resistance by examining the curve for a typical
diode from the family and performing a few simple calculations. For example, note from
point A in Figure 2-5 that the typical diode has a forward voltage drop of 2.0 volts when
diode current is 24 amps. When diode current increases to 33 amps (point B), forward
voltage drop increases to 2.4 volts.

Using the values of these two points on the graph, we can calculate dynamic forward resistance
(rF) as follows:

r F= Measured voltage change = ∆V = 2.4 - 2.0 = 0.4 = 0.044ohm

Measured current change ∆I 33 – 24 9

Figure 2-5. High power diode forward dc characteristic curve.

As you can see, typical diodes have very low dynamic forward resistance. The delta symbol (∆)
is used in the equations to mean difference or change. When you see an expression such as
∆V/ ∆I, you should read it as the difference in voltage divided by the difference in current.
Because a forward biased diode offers little resistance to the passage of current an external
resistance must be included in the circuit to prevent damage to the diode. The highest current
allowed through a diode before it is damaged is the maximum forward current, often abbreviated
as (lmax) on diode specification sheets. Maximum forward current is usually specified at a
particular temperature. It must be reduced, or derated, at higher temperatures.
Forward biased diodes dissipate power in the form of heat. A diode's power dissipation is easily
calculated if circuit current and diode forward voltage are known. For example, due to the
combined effects of barrier voltage and dynamic forward resistance, a particular silicon diode
has a forward voltage drop of 1.8 volts when it conducts a current of 10 amperes. At this current
level, the power dissipated within the diode is:
P = IE = 10 x 1.8 = 1 8 watts
Although eighteen watts seems like a small amount of power, it is created in a very small area
near the junction. If the heat is not continuously removed, the diode can be destroyed. For this
reason, diodes with an IF rating of more than a few amps are usually constructed in metal
packages. These metal packages are designed to be'att13ched to larger metal plates called
heat sinks.
A heat sink helps to transfer heat from the diode into the surrounding air; thereby preventing the
temperature of the junction from reaching destructive levels.
A good diode junction has a low forward resistance compared to its reverse resistance, which is
very high. Measuring the actual forward resistance of a diode junction is difficult because
forward current increases very rapidly with small increases in forward voltage.
When an ohmmeter is used to test a diode, the reading should be interpreted as an indication of
conduction (current flow) or no conduction (no current flow). The reading is not the correct
ECE 301 20

resistance of the junction.

When the ohmmeter is connected to forward bias a good diode junction, it should show a
number (reading), which indicates conduction. The number showing on the meter is not the
actual resistance but indicates only that current is flowing through the junction. The magnitude
of the meter reading depends on the type of meter and the selected meter scale. It can vary
widely for different meters and scales.
When the ohmmeter is connected to reverse bias a good diode junction, it will show an off-scale
(overload) reading, which indicates no conduction.
To forward bias a diode junction with an ohmmeter, connect the positive lead (usually the red
lead) to the anode and the negative lead (usually the black common lead) to the cathode.
To reverse bias a diode junction with an ohmmeter, connect the positive lead to the
cathode and the negative lead to the anode.
In general, you may test a diode without connecting other circuit components. Power to
the circuit must be shut off to avoid damage to the ohmmeter. If necessary, disconnect one end
of the diode to eliminate parallel circuit paths around the diode.
IV. PROCEDURE:
1. Adjust the power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert the
SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the power
sources at this time.
2. Locate the TRANSISTOR JUNCTION circuit block. You will use an ohmmeter (digital or
analog) to test the junction of diode CR1.
Connect the black (common) meter probe to the test point at the CR 1 anode. Connect the
red meter probe to the test point at the GB1 cathode. Does your meter reading indicate that
the diode is conducting or not conducting?
_________________________________________________________________

3. Does your meter reading indicate that the diode is forward or reverse biased?
__________________________________________________________________
4. Reverse the meter probes by connecting the red probe to the CR1 anode and the black
probe to the cathode. Does your meter reading indicate that the diode is conducting or not
conducting?
__________________________________________________________________
5. Does your meter reading indicate that the diode is forward or reverse biased?
__________________________________________________________________

6. Based on the above measurements, is diode CR1 a good or bad diode?

__________________________________________________________________
7. Locate the DIODES AND ½ WAVE RECTIFICATION circuit block, and connect the circuit
shown in Figure 2-6. Turn on the power sources, and adjust the negative voltage (VA) to -10
Vdc.

Figure 2-6. Diode dc bias (VA negative)

8. Measure and record the voltages across R1 and R2. Which diode is forward biased, and
which diode is reverse biased?
_______________________________________________________________
ECE 301 21

9. Which diode circuit allows current to flow? Does current flow because this diode is reverse
biased or because it is forward biased?
____________________________________________________________

10. Connect the circuit shown in Figure 2-7. Adjust the positive variable supply to 10 Vdc.
Measure and record the voltages across R 1 and R2.
____________________________________________________________

Figure 2-7. Diode dc bias (VA positive).

11. Which diode is forward biased, and which diode is reverse biased?
_____________________________________________________________

12. In the circuit of Figure 2-7, which component determines the amount of current through the
forward biased diode?
_________________________________________________________________
13. Use the current form of Ohm's law to calculate the current through R2. Record your results.
________________________________________________________________

_________________________________________________________________

14. Using the value of current that you found in step 13, determine and record the amount of
current through CR2.
_________________________________________________________________

15. Set the positive variable supply voltage to 0.25 Vdc. Measure VR2 and calculate circuit
current (IR2 = V R2/R2). Calculate the diode voltage drop (Vo = VA - VR2). Record the
measured and calculated values in Table 2-1.
ECE 301 22

16. Increase the positive applied voltage to each value indicated in the first column of Table 3-1.
At each voltage level, measure VRZ and calculate circuit current and diode voltage drop.
Enter your values in the appropriate columns of the table.

Figure 2-8. CR2 characteristic curve.

17. Compare the results recorded in Table 2-1 with the dc characteristic curve of Figure 2-8.
Based on VD, at what point does your data indicate that the diode is forward biased?
______________________________________________________________

18. Based on your data, does the diode forward voltage remain about the same after the diode
reaches full conduction (that is, forward current of 1 mA or more)?
______________________________________________________________

19. Turn off the power sources, but do not remove circuit board connections. The F.A.C.E.T.
setup will be used for the evaluation.

V. EVALUATION:
1. Locate the TRANSISTOR JUNCTION circuit block on the SEMICONDUCTOR
DEVICES circuit board. Using a digital multimeter or an analog ohmmeter, forward
and reverse the junction of CR1. Set CM switch 1 in the ON position, and repeat the
forward and reverse measurements. Based on these measurements, CR 1
a. tests good when the switch is off and bad when it is on.
b. tests good when the switch is on and bad when it is off.
c. is bad in both switch positions.
d. is good in both switch positions.

Turn off CM switch 1. Remove all circuit board connections.

2. Diode forward voltage drop is

a. a desirable characteristic for circuit protection.
b. nearly constant when the diode is fully forward biased.
c. not related to the semiconductor material.
d. determined by the circuit resistance.
ECE 301 23

3. Leakage current
a. flows when the reverse breakdown voltage is exceeded.
b. flows when the barrier voltage is exceeded.
c. improves diode performance.
d. should be very small in a good diode.

4. Diode characteristic curves

a. describe the forward bias operation of the diode.
b. describe the reverse bias operation of the diode.
c. show the forward voltage drop of the diode.
d. All of the above.

5. The cathode end of a diode package

a. is usually marked with a dot or color band.
b. can be located only by measurement.
c. is marked with an arrow.
d. is positive when the diode is forward biased.

VI. CONCLUSION
ECE 301 24

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 3
RECTIFIERS

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. HALF-WAVE RECTIFICATION:

I. OBJECTIVE:
 To be able to use semiconductor diodes in half-wave rectifier circuit using
a typical half-wave rectifier and to verify the results with an oscilloscope and a
multimeter.

 To be able to utilize a diode operating curve to test a diode by using a

typical diode circuit and verify the results with a multimeter.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit

 SEMICONDUCTOR DEVICES Circuit Board
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this unit. Measured
values will differ from nominal due to normal circuit and instrument variations. Your
measurements in the following exercises will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise
noted in a procedure step:
External power source settings: +15 Vdc = ±3 percent
-15 Vdc = ±3 percent

POSITIVE SUPPLY and NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: : ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope): ± 8 percent

III. THEORY:

INTRODUCTION/ HALF WAVE RECTIFIERS

The simplest method for converting an alternating current into a pulsating direct current
is through half-wave rectification. A half-wave rectifier circuit requires only a diode and a load
resistance, as shown in Figure 2-9(a).
A half-wave rectifier can produce either a positive or a negative pulsating dc output, depending
on how the diode is connected in the circuit. Figure 2-9(a) shows positive half-wave rectification
with respect to circuit common, and Figure 2-9(b) shows a negative half-wave rectification
circuit.
ECE 301 25

Figure 2-9. Basic half-wave rectifier circuit.

In Figure 2-10 (a), the anode of the diode (point A of the drawing) is positive with respect
to the cathode during positive alternations of the ac input waveform, so current flows. The
current flow through CR1 results in a voltage drop across the series-connected load resistor,
R1. This conduction period is indicated by the shaded portions of the V1N and VOUT waveforms
of Figure 2-10(a). During negative alternations, no current flows because the anode is negative
with respect to the cathode.
If the diode is reversed, as shown in Figure 2-10(b), the diode conducts during negative
alternations of the ac input. The resulting output is negative with respect to common, as shown
by the shaded areas of the waveforms in Figure 2-10(b).
The output from either circuit is no longer an ac voltage, but rather a pulsating de
voltage. The process whereby the diode conducts during one alternation of the input cycle and
blocks current flow during the other is called rectification. For half-wave rectifiers, the diode will
conduct for about one-ha If of every complete ac cycle. This conduction occurs during either the
positive or negative alternation, depending on the direction in which the diode is connected into
the circuit.
An ideal diode would have no forward voltage drop or reverse leakage current. Practical
diodes have leakage currents that are small enough to be ignored. However, when a diode is
fully conducting, electrons are present in the P type material and positive charges are present in
the N type material. When the voltage across the diode switches suddenly from the forward to
the reverse bias direction, these charges must be swept from the diode before conduction
stops. Just as a check valve will allow a small slug of fluid to move in the reverse direction
before the check ball seals, a pulse of current flows in the reverse direction through a diode until
the stored charges are removed from the semiconductor. The time required to remove these
stored charges is called reverse recovery time (tRR).

Figure 2-10. Half-wave rectifier input! output

relationship.
The amount of stored charge depends on the size of the diode, the doping material and
doping level, and several other factors. Reverse recovery time limits the operation of general
purpose rectifier diodes to relatively low frequencies (less than 1 kHz) because the pulses of
current allowed in the reverse direction become significant at higher frequencies. Some diodes
are designed to limit the effect of stored charges; these diodes are called high speed or fast
recovery diodes.

Forward voltage drop (VF) is another diode characteristic that can cause significant losses,
especially if applied voltages are small. During l1e forward biasing alternation of the input signal,
no current flows until the input voltage exceeds VF. When that point is overcome, the diode
ECE 301 26

starts to conduct, and voltage appears across the load resistor. You can estimate the peak
output circuit voltage (Vopeak) by simply subtracting the diode forward voltage drop (about 0.
7V for silicon diodes) from the peak input voltage (ViPeak).
For example, Vipeak is equal to 2.0V in Figure 2-11. The rectified circuit output voltage is
calculated as follows:

Figure 2-11 . Voltage levels of a half-wave rectifier.

Figure 2-11 illustrates this relationship between input and output peak waveforms for
a positive half-wave rectifier. Notice that the output waveform contains a positive pulsation
that is only a portion of the positive alternation of the input waveform. During the negative
alternation of the input signal, no current flows because the diode is reverse biased. Also
notice that the starting point of the VOUT pulsation begins when the input voltage reaches
0.7V, the point at which the diode barrier voltage is overcome.

The VOUT waveform of Figure 2-11. shows that the output pulsation is less than the
input alternation by 0.7 volts at every point. When you use an oscilloscope to measure the
input and output voltages of a half-wave rectifier, you can observe and compare both signals
together. You may measure the 0.7 Vdc forward voltage drop of the diode by dc coupling
both channels.
Oscilloscope readings are peak-to-peak for ac (input) waveforms and peak for
rectified (output) waveforms. By using the conversion factors which follow, you can convert
the values measured on the oscilloscope to approximate rms or average values. These
conversion factors apply only to half-wave rectifiers and only when the rectifiers are supplied
with ac sine wave inputs. Note that the diode forward voltage drop is accounted for when you
view the peak output voltage on the oscilloscope.
Half-wave rectifier voltage conversion factors:
rms output voltage = 0.5 x peak output voltage
average output voltage = 0.318 x peak output voltage

Figure 2-12 illustrates the relationship between peak, rms, and average values as they apply to
a half-wave rectifier circuit.

Figure 2-12. Half-wave rectifier voltage

relationship.
ECE 301 27

In Figure 2-12, a voltage is developed across load resistor RL. As a result, current must
flow through the load. When the voltage and load resistance are known, you can calculate the
approximate current through the load by using the following formula and conversion factors.

Half-wave rectifier current relationships:

The variations in the pulsating dc output of a rectifier are referred to as ripple. The
higher the ripple frequency, the more effective the circuit. The frequency of an ac waveform is
defined by the number of complete cycles in one. second. An alternating current of 60 Hz has
60 positive and 60 negative alternations in one second. In a half-wave rectifier, the ripple
frequency. is the same as the input voltage frequency because only the negative or /he positive
(depending on how the diode is connected in the rectifier circuit) alternations are allowed to
pass. Figure 2-13 shows the ripple frequency for ac frequencies of 50 and 60 Hz.

Figure 2-13. Half-wave rectifier ripple frequency.

IV. PROCEDURE:

1. Adjust the dc power sources to+15 Vdc and -15 Vdc. Turn the power Sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Turn on the power
sources.

2. Locate the DIODES AND 1/2 WAVE RECTIFICATION circuit block, and connect the
circuit shown in Figure 2-14.

Figure 2-14. Half-wave rectifier circuit.

3. Connect the sine wave generator signal leads to the 50-ohm output of the generator. If
your generator output impedance is not 50 ohms, insert the GENERATOR BUFFER into
the SEMICONDUCTOR DEVICES circuit board. and connect the buffer between your
generator and the circuit. If you use the buffer circuit. connect the buffer output terminals
to the generator terminals on the DIODES AND 1/2 WAVE RECTIFICATION circuit
block. Set the generator frequency controls to 1000 Hz and the output level to zero.

4. Connect X10 probes to both channels of the oscilloscope. Set the input controls for both
channels to ground, and adjust the vertical centering controls for both channels to align
both traces exactly on the center horizontal line of the scope graticule. Now switch the
input controls for both channels to dc coupling, and set the calibrated oscilloscope
controls of channels 1 and 2 for 50 mV/cm sensitivity. Set the horizontal sweep controls
for a sweep rate of 0.1ms/cm. Trigger the sweep on channel 1, and adjust for positive
sync level.
ECE 301 28

5. Connect oscilloscope channel to observe the ac input to the circuit. Adjust the output
level of the sine wave generator for 2 V pk_pk.
6. Set the multimeter to read ac voltage. Connect the multimeter temporarily to the circuit
input and record the voltage reading.

__________________________________________________________________

7. Calculate the rms and average voltage values at the circuit input. Note that peak input
voltage is one-half of the peak-to-peak value.

__________________________________________________________________
__________________________________________________________________

8. Do the values in steps 6 and 7 agree?

__________________________________________________________________

9. Connect oscilloscope channel2 across load resistor R2 and observe the CR2 output
waveform. What is the amplitude of the positive pulsations?

__________________________________________________________________

10. Observe the input and output signals on channels 1 and 2, respectively, by using the
oscilloscope CHOP method. Is the ripple frequency the same as the input frequency?
What is the ripple frequency?
__________________________________________________________________

11. Measure and record the peak voltage displayed on each oscilloscope channel. What is
the difference in voltage, and what causes the difference?

__________________________________________________________________

12. Set the oscilloscope time base for 50 µs/cm. Set both input channel selector switches to
the GND position. Adjust the vertical position controls for both channels so that both
traces lie along the center horizontal grid line of the oscilloscope graticule. Set the
volts/division control for channel 2 to 20 mV /cm, and set both input channel selector
switches to the dc coupling position.

13. Observe both traces in the CHOP sweep mode, and compare the display with Figure 2-
15. Adjust the oscilloscope controls to match the figure, if necessary.

Figure 2-15. Comparison of oscilloscope waveforms to reference.

14. What happens (in regard to conduction) at point A on the illustration and the
oscilloscope display?

_____________________________________________________________

15. What happens (in regard to conduction) at point B?

_____________________________________________________________
ECE 301 29

16. Is the voltage before point A and after point B sufficient to overcome the diode barrier
voltage?
________________________________________________________
17. What is subtracted from the input peak amplitude to make the peakamplitudes of the
input and output waveforms unequal?

_____________________________________________________________

18. Adjust the oscilloscope time base to 0.2 ms/cm. Set channel 1 for 50 mV/cm and
channel 2 for 20 mV/cm. Adjust the oscilloscope, if necessary, until the displayed
waveform duplicates Figure 2-16.

Figure 2-16. Oscilloscope waveform adjustment

19. From the appearance of the oscilloscope waveforms, is this a positive or a negative
half-wave rectifier circuit?

_______________________________________________________

20. Connect the oscilloscope channel 2 input to the top of R 1. Why is this circuit a negative
half-wave rectifier?
__________________________________________________________________

21. Do the same input/output relationships apply to both the positive and the negative half-
wave rectifiers?
_______________________________________________________

22. Is CR1 conducting or is it cut off during the negative portions of the output waveform?

__________________________________________________________________

23. Place CM switch 7 in the ON position. What now appears at the output?

__________________________________________________________________

24. CM switch 7 connects a 1K resistor across CR1, allowing current to flow during positive
peaks of the input waveform. From your observations, can you conclude that the normal
reverse resistance of CRl is much higher than lK?

__________________________________________________________________
_____________________________________________________

25. Does CM switch 7 cause CRl to simulate a good diode with sufficient reverse resistance
or does it cause CRl to simulate a defective diode with insufficient reverse resistance?
__________________________________________________________________
______________________________________________________

26. Turn off CM switch 7. Adjust the sine wave generator for a 4 Vpk-pk input signal on
oscilloscope channel. Measure and record the dc output voltage across Rl (use the dc
volts function of your multimeter).

_________________________________________________________________
__________________________________________________________________
ECE 301 30

27. Calculate and record the expected average output voltage based on a 2 Vpk output.
Use this formula for a half-wave rectifier: Average dc output = 0.318 x peak output
voltage
__________________________________________________________________
__________________________________________________________________
28. Why does the multi meter display a lower reading in step 26 than the value calculated in
step 27?
__________________________________________________________________
__________________________________________________________________

29. Disconnect the multi meter, and increase the frequency of the generator to 10kHz. Set
the input selector switches for both channels to the GND positi9n. Adjust the vertical
position controls to I align the channel 1 trace along the second grid tine from the top of
the screen, as well as to align the channel 2 trace along the second. grid line from the
bottom. Set both channels to 0.2 V/cm, and set both input selector switches to dc
coupling.

30. Connect channel 2 of the oscilloscope to the top of R1. Set the sweep speed of the
oscilloscope to 0.1 ms/cm. What causes the positive peaks that are visible on the
channel 2 trace?
__________________________________________________________________

31. Increase the sine wave generator frequency to 100 kHz and the oscilloscope sweep
speed to 10 us/cm. Can the channel 2 waveform be called pulsating dc?
__________________________________________________________________

32. Turn off all power sources and the generator. Remove all circuit board connections.

V. EVALUATION:
1. Refer to Figure 2-17. The signal observed at the output of this circuit with respect to
circuit common would be
a. positive pulsations.
b. negative pulsations.
c. alternating current.
d. None of the above.
CR1

AC
Generator OUTPUT

Figure 2-17. Half-wave rectifier test circuit.

2. If the diode in Figure 2-17 opens, the observed

output becomes
a. positive pulsations
b. negative pulsations
c. alternating current
d. none of the above
3. If the diode in a positive half-wave rectifier circuit has insufficient reverse resistance,
then
a. less current flows when the diode is forward biased.
b. current can flow in the negative direction.
c. the efficiency of the rectifier increases.
d. the circuit acts as a negative half-wave rectifier.
ECE 301 31

4. In a half-wave rectifier circuit, the output voltage pulse width (diode conduction time)
a. is greater than one-half of the input cycle time.
b. is equal to one-half of the input cycle time.
c. is slightly less than one-half of the input cycle time.
d. depends on the amplitude of the ac input signal.
5. If ac generator connections A and B were reversed in Figure 2-17,
a. the diode would be destroyed.
b. there would be no effect on circuit operation.
c. ac would appear across RL.
d. the output would reverse its polarity.

VI. CONCLUSION:
ECE 301 32

B. FULL- WAVE RECTIFICATION:

I. OBJECTIVE:
 To be able to demonstrate rectification using a full-wave bridge rectifier circuit and to
verify the results with an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

MEASUREMENT TOLERANCES

Nominal values have been determined for all measurements in this unit. Measured
values will differ from nominal due to normal circuit and instrument variations. Your
measurements in the following exercise will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise
noted in a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLYand
NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope): ± 8 percent

III. THEORY:

AC current is simpler and more economical to generate and transmit than is dc

current. For this reason, electric utility companies generate and distribute ac power. But
typical electronic circuits require a de source of power. A rectifier circuit can be used to
convert ac into pulsating dc.
To convert ac to dc, the rectifier circuit must be capable of passing current in one
direction (forward biased) and blocking current in the reverse direction. The diode, with its
unidirectional (one way) current characteristic, is well suited for rectification. Diodes may be
configured in three basic ways to perform rectification.
The first part of this experiment lets you observe how a single diode is able to
perform half-wave rectification on low current applications. Groups of diodes allow a circuit
to perform full-wave rectification, a more efficient process. Figure 3-7 illustrates the two
circuit configurations that provide for full-wave rectification.

Figure 3-7. Full-wave circuit configurations.

ECE 301 33

Circuit operation is nearly identical for both configurations. Figure 3-7(a) shows a
center-tapped full-wave rectifier circuit. Figure 3-7(b) shows a full-wave bridge rectifier
circuit. Due to design considerations and transformer efficiencies, the circuit configuration of
Figure 3-7(b) is generally preferred. .
Rectification is a process in which a diode conducts during one alternation of the
input cycle (half-wave rectification). The full-wave bridge rectifier makes possible the
rectification of both alternations of the input cycle.

Figure 3-8 shows a full-wave bridge rectifier circuit with four diodes (01,02. 03. and 04).
The bridge has two input terminals and two output terminals

Figure 3-8. Full-wave BRIDGE rectifier.

The input terminals are marked with a symbol () that indicates the ac sides of the
bridge. The output terminals are marked with plus (+) and minus (-) symbols that indicate the
positive and negative dc output sides of the bridge. When the bridge is in operation, a pair of
diodes at a time conducts. The diode pairs are D1 and D3, and D2 and D4. Because of the
diode pairing, both alternations of the input ac signal are converted to pulsating dc, resulting in
full-wave rectification.

Figure 3-9 shows the conduction of the bridge for each ac alternation. In Figure 3-9(a),
the positive alternation causes diodes D1 and D3 to be forward biased. As a result, current
flows through D3 and the load resistor, then back to the transformer through D1. Because
diodes D2 and D4 are reverse biased at this time, they perform no function in the circuit, and
so they are not shown.

Figure 3-9(a). Conduction paths of a full-wave bridge rectifier.

ECE 301 34

Figure 3-9. Conduction paths of a full-wave bridge rectifier

In Figure 3-9(b). the negative alternation causes diodes D2 and D4 to be forward biased.
As a result. current flows through D2 and the load resistor. then back to the transformer through
D4. During this alternation. diodes D1 and D3 are reverse biased and so are not shown.

Notice that both the positive and negative alternations of the input ac voltage are
converted to pulsating dc. Figure 3-9(c) shows the resulting rectified voltage wave shape. ln
addition, the diode pairs steer the pulsating dc output so that current flows through the loading
the same direction during both input voltage alternations.
Because there are two pulses for one complete cycle of the input waveform, as Figure 3-
9(c) indicates. the output pulse frequency of a fuII-wave rectifier is twice that of the input
frequency. Therefore, the ripple frequency of the output is equal to two times the input, or line,
frequency.
The relationship between peak, rms, and average voltages of a full-wave rectifier are shown in
Figure 3-10. ln general, the average value is twice that of a half-wave configuration. The rms
value increases to 0.707.

IV. PROCEDURE

1. Adjust the dc power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.

2. Locate the FULL WAVE RECTIFICATION WITH POWER SUPPLY FILTER circuit block,
and connect the circuit shown in Figure 3-11. Install the GENERATOR BUFFER as
shown in the figure.
ECE 301 35

Figure 3-11. Test circuit hook up for full-wave bridge rectifier.

3. What is the purpose of R1?

_____________________________________________________________________

4. Using X10 probes, set oscilloscope channels 1 and 2 for 0.5 VIcm. DC couple each input.
Set the time base for 1 ms/cm. Use posit1ve level triggering, and sync the oscilloscope on
channel 1.

5. Connect channel 1 of the oscilloscope to the output terminals of the GENERATOR BUFFER.
Connect channel 2 across the secondary terminals of T1.

6. Measure the transformer secondary, and adjust the generator for a 20 Vpk-pk 100 Hz sine
wave. Compare the secondary voltage to the primary voltage displayed on channel 1 of the
oscilloscope. Based on your voltage readings, is the primary-to-secondary a step-down or a
step-up voltage relationship?

___________________________________________________________________________

7. Move channel 2 of the oscilloscope to the output side of the bridge (CR1) circuit. Place
the common side of the test probe on the negative point of the bridge. Are one or both
alternations of the input waveform displayed at the output? If one, which one?

___________________________________________________________________________

8. What is the frequency of the output pulsations of the full-wave rectifier circuit (measure
the period of the waveform on channel2 of the oscilloscope)?

___________________________________________________________________________
ECE 301 36

9. Set channel 2 for 2 V Icm. Draw the output waveform on the graph of Figure 3-12. What
is the peak output voltage value?

Figure 3-12. Graph for output voltage waveform.

10. Calculate and record the dc average output voltage (Vavg = Vpk x 0.636). Use the peak
value that you recorded in step 9.

___________________________________________________________________________

11. Set your multimeter to dc Volts. Measure the circuit output voltage. Compare your
calculated and measured readings. Are they equal within measurement tolerance?

12. The peak output secondary voltage of the transformer is 10 Vpk. The peak output of the
rectifier circuit is 9 Vpk. Are the readings different due to the forward voltage drop of the
diodes?
____________________________________________________________________________

13. Move the channel 2 oscilloscope probe to the top terminal of the transformer secondary.
Ensure that the common lead of the test probe is at the negative terminal of the bridge
circuit. Refer to Figure 3-13 for proper circuit measurement points.

Figure 3-13. One diode drop test points.

14. Using a Xl0 probe, set channel 2 for 0.2 V / cm. Monitor channel 1 of the oscilloscope and
adjust the output of the external sine wave generator for a 10 Vpk_pk signal. Position the
test waveform as indicated by Figure 3-14.
ECE 301 37

Figure 3-14. Diode drop test waveforms.

15. Refer to the oscilloscope display. During which alternation of the input voltage is the diode
under test forward biased?
__________________________________________________________________________

__________________________________________________________________________

16. What is the approximate forward bias voltage drop of the diode being measured?
NOTE: Measure the drop from the channel 2 reference line on Figure 3-14.

__________________________________________________________________________

__________________________________________________________________________

17. Refer to the test voltages displayed on the oscilloscope. Is the test diode forward or reverse
biased during the positive alternation of the input voltage?
__________________________________________________________________________

__________________________________________________________________________

18. Move the channel 2 reference line to the middle line of the oscilloscope graticule. Move the
common lead of the channel 2 probe from the negative side of the bridge to the positive side of
the bridge.

19. Refer to your displayed test voltages. During which input alternation does this diode
conduct?
__________________________________________________________________________

__________________________________________________________________________
20. Is the diode forward drop about the same as that measured in step16?
_________________________________________________________
21. Figure 3-15 shows a full-wave rectifier circuit in a non-bridge configuration. Based on your
test results, which other diode conducts while D1 is forward biased?

__________________________________________________________________________

__________________________________________________________________________

22. Do not turn off the power source. The F.A.C.E.T. setup will be used for a review question.
ECE 301 38

Figure 3-15. Full-wave rectifier in a non-bridge configuration.

V. EVALUATION:
1. Locate the FULL WAVE RECTIFICATION WITH POWER SUPPLY FILTER circuit block
on the SEMICONDUCTOR DEVICES circuit board. Connect the circuit shown in Figure
3-16. Place CM switch 16 in the ON position. What effect does this circuit modification
have on the output voltage?
a. None. Only the input signal is converted
b. The output signal is converted to pulsating ac
c. Both output pulses are reversed
d. The output looks like half-wave rectification

Figure 3-16. Test circuit hookup for full-wave bridge rectifier.

Turn off CM switch 16 and the power sources. Remove all circuit board connections.

2. The purpose of a rectifier circuit is to

a. convert direct current to pulsating current.
b. convert alternating current to pulsating dc.
c. convert pulsating direct current to dc.
d. isolate the source and load voltages.

3. In a full-wave bridge rectifier circuit configuration,

a. only negative input alternations are passed.
b. only positive input alternations are passed.
c. both input alternations are passed at the same time.
d. each input alternation is passed in turn.

4. The output ripple frequency of a full-wave rectifier is

a. double the input frequency.
b. the same as the input frequency.
c. half of the input frequency.
d. 200 Hz.

VII. CONCLUSION:
ECE 301 39

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 4
POWER SUPPLY FILTERING AND VOLTAGE DOUBLING

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. POWER SUPPLY FILTERING

I. OBJECTIVE:
 To be able to convert pulsating dc to a smooth, filtered dc voltage and to verify the
results with a multimeter and an oscilloscope.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this unit. Measured
values will differ from nominal due to normal circuit and instrument variations. Your
measurements in the following exercise will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise
noted in a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLYand
NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope): ± 8 percent

III. THEORY:

As you have observed, rectifiers without output filters are limited in application
because they have high ripple content in their output voltages. Because most electronic
equipment requires smooth dc voltage, filters are used to reduce the ripple to very low
levels. A basic capacitive input filter is shown in Figure 3-17.

Figure 3-17. Capacitive input filter

ECE 301 40

A capacitive filter is simply an electrolytic capacitor connected across the rectifier

circuit output. Other types of filters are configured with inductors or combinations of
resistors, capacitors, and inductors. These filters are called pi type or L 'type, based on
the circuit configuration. Figure 3-18 shows various types of filter circuits. In general,
each type of filter is used to convert the pulsating output voltage of a rectifier circuit into a
smooth dc voltage.

Figure 3-18. Examples of filter circuits

The L type is so named because the upside down letter L is produced by component
placement. The pi type is so named because the Greek letter  is produced by component
placement, The name of the filter is taken from the first component that connects to the rectifier
output terminals. For example, Figure 3-18(c) shows an inductive input. or choke input, L type
inductive/ capacitive (LC) filter.
Each filter section, such as the Rs/CF1 section of Figure 3-18(b), removes a portion of
the rectifier ripple content. Therefore, a pi (two-section) filter produces a smoother dc voltage
than does a single-section filter. In general, the larger the value of the capacitor or inductor, the
smoother the dc voltage.
Figure 3-19 shows a schematic of the power supply filter circuit used in this exercise.
The circuit indicates a full-wave bridge rectifier working into a single stage capacitive filter. The
circuit load resistor is in parallel with the filter capacitor.

Figure 3-19. Power supply filter circuit.

Recall that the ripple output of the bridge supplies energy to the load in pulses. The
ripple can be reduced if some of the energy from the source is stored while the rectifier is
delivering a pulse. The stored energy can then be released to the load between supply pulses.
This release provides energy to the load on a continuing (dc) basis and is the basic operating
principle of a capacitive filter.
The action of the capacitive filter circuit shown in Figure 3-19 is illustrated in Figure 3-
20. Capacitor CF in Figure 3-19 charges rapidly to the peak rectifier voltage, as shown in
Figure 3-20. When the rectifier output drops to zero between output pulses. the charged
capacitor discharges and supplies current to the load. Before the capacitor voltage drops too
low, another output pulse supplied by the rectifier recharges the capacitor to the peak voltage
value of the pulse.
ECE 301 41

As indicated by Figure 3-20, the charge time is much smaller in duration than the
discharge time. Therefore, you might conclude that all of the capacitor energy would be
removed over some period of time. However, this is not the case.

The rate at which the capacitor discharges, and therefore the average level of the load
voltage, depends mainly on the RC time constant of the filter capacitor and the circuit load
resistor. The input circuit charge time is generally much faster than that of the load circuit
because the RC time constant of the source resistance and filter capacitor is much less,
Therefore, over time, more energy is put into the capacitor than can be taken out. This action
results in a dc load voltage that is an average of the pulsating dc rectifier output.

Figure 3-21 shows the averaging concept as it applies to the waveform of a full-wave
rectifier filter circuit.

For the waveform in Figure 3-21, the average circuit voltage is 8.00 Vdc. However,
due to the pulsating input voltage and the circuit load resistor, the filter capacitor can not
remove all of the ripple voltage. The remaining ripple voltage rides above and below the
average dc voltage, creating a sawtooth-like waveform. Generally, filtering is selected to
maintain the ripple content to about 1 percent of the average dc voltage.

For a constant load, a larger filter capacitor value will provide less ripple and
higher average dc voltage. However, for a constant value of filter capacitor, a lower
value of load resistor (more load current required) will generate higher ripple
voltages and less average dc voltage.

IV. PROCEDURE:
1. Adjust the dc power sources to +15 Vdc and -15 Vdc. Turn the power
sources off. Insert the SEMICONDUCTOR DEVICES circuit board into the
base unit. Do not turn on the power sources at this time.
ECE 301 42

2. Locate the FULL WAVE RECTIFICATION WITH POWER SUPPLY FILTER

circuit block. Connect the circuit shown in Figure 3-22. Install the
GENERATOR BUFFER as shown in the figure.

Figure 3-22. Test circuit hook-up for full-wave bridge rectifier and filter.

3. What type of filter circuit is represented by Figure 3-22?

____________________________________________________________

4. Connect channel of the oscilloscope to the output terminals of the

GENERATOR BUFFER. Connect channel 2 to the output terminals of the
bridge circuit. Place the common lead of the channel 2 test probe on the
negative side of the bridge (circuit common).
NOTE: For the remainder at this procedure,
adjust the oscilloscope settings for best results.

5. Monitor channel of the oscilloscope. Set the external sine wave generator
for the frequency supplied by your local utility. Adjust the generator
amplitude for a 20 Vpk-pk indication on the oscilloscope. Will the source
(line) frequency have an effect on the average dc and ripple values of the
circuit output voltage?

____________________________________________________________

____________________________________________________________

6. Remove C1 from the circuit by removing its two-post connector. Measure

and record the peak-to-peak voltage at the transformer secondary terminals.

____________________________________________________________

____________________________________________________________

7. Based on this reading, what should the de average voltage at the circuit
output be when C1 is placed into the circuit?
HINT: The circuit is unloaded: therefore. the output
voltage equals fhe maximum peak charge of fhe
capacitor.
____________________________________________________________

____________________________________________________________

8. Use your multimeter to measure the circuit output dc voltage. Does your
reading agree with the answer you provided in step 7?
____________________________________________________________

____________________________________________________________

9. Remove the multimeter from the circuit. Using channel 2 of the oscilloscope.
measure and record the ripple content of the dc voltage.
NOTE: Remember to ac couple fhe channel 2 input.
____________________________________________________________

____________________________________________________________
ECE 301 43

10. Based on the circuit load and on your result in step 9. is your observation in
step 9 correct?
____________________________________________________________

____________________________________________________________
11. To complete Table 3-1, you will use your multimeter and channel 2 of the
oscilloscope as required. Your multimeter should be set to read dc voltage.
The oscilloscope channel 2 should be let for ac coupling. Use two-post
connectors to insert and remove various circuit components as indicated by
Table 3-1. Measure the required values and complete the table.
NOTE: Ensure that the output voltage oj the GENERATOR
BUFFER is set for 20 Vpk-pk.

12. Refer to Table 3-1. Without C1 or C2 placed at the bridge output, is any
circuit filtering provided?

____________________________________________________________

____________________________________________________________

Table 3-1. Filter circuit test results.

OUTPUT DC OUTPUT RIPPLE

C1 C2 R2 R3 VOLTAGE VOLTAGE
OUT OUT OUT OUT

IN OUT IN OUT

IN OUT OUT IN

IN IN IN out

IN IN OUT IN

13. Refer to Table 3-1. Does dc .output voltage increase or decrease when the
circuit load is increased?

____________________________________________________________

____________________________________________________________

14. Does the ripple content of the output voltage increase or decrease as the
value of the filter capacitor is reduced?

____________________________________________________________

____________________________________________________________

15. Refer to Table 3-1. Is the ripple content of the output voltage less than 1
percent?
____________________________________________________________

____________________________________________________________

16. Using two-post connectors, configure the circuit so that C1 and R2 are in the
circuit. C2 and R3 should not be connected.

17. Increase the external sine wave generator frequency to 1000 Hz. Ensure
that the GENERATOR BUFFER output voltage, monitored on channel 1 of
the oscilloscope, does not change.

18. Does the ripple content of the output voltage increase or decrease when
line frequency increases?

____________________________________________________________
ECE 301 44

____________________________________________________________

19. If, in step 18, the line frequency remained the same but the filter capacitor
increased, would the effect on ripple content be in the same direction?

____________________________________________________________

____________________________________________________________
20. Adjust the frequency of the external generator back to its initial setting.
Place CM switch 15 in the ON position. Based on the channel 2 display of
the circuit output voltage, is Cl performing its assigned circuit job?

____________________________________________________________

____________________________________________________________

21. Turn off CM switch 15 and the power sources. Remove all circuit board
connections.

V. EVALUATION:

1. If the amount of filter capacitance in a rectifier circuit is increased, the

a. percent ripple increases.
b. dc output voltage decreases.
c. load current increases.
d. percent ripple decreases.

2. The amount of ripple in a filtered rectifier circuit is inversely proportional to

a. the amount of filter capacitance in the circuit.
b. the load resistance.
c. All of the above.
d. None of the above.

3. The sawtooth ripple waveform in a filtered rectifier circuit is caused by the

a. rapid charging and slow discharging of the filter capacitor;
b. slow charging and rapid discharging of the filter capacitor.
c. rapid charging and discharging of the filter capacitor.
d. slow charging and discharging of the filter capacitor.

4. A decrease in the ripple content of a filtered output rectifier circuit can be

caused by
a. a decrease in line frequency.
b. a decrease in the value of filter capacitance.
c. an increase in the line frequency.
d. the addition of a smoothing diode.

5. Removing the load from a filtered rectifier circuit will cause its output voltage
to
a. decrease to zero.
b. increase to its maximum value.
c. decrease to its minimum value.
d. reverse its ac polarity.

VI. CONCLUSION:
ECE 301 45

B. VOLTAGE DOUBLER

I. OBJECTIVE:
 To be able to demonstrate the operation of a voltage doubler using measured
average and peak output voltages and verify your results with a multimeter and
an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this unit. Measured
values will differ from nominal due to normal circuit and instrument variations. Your
measurements in the following exercise will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise
noted in a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLYand
NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope): ± 8 percent

III. THEORY:

A combination of rectifier diodes and filter capacitors can be configured to double the peak
output voltage of a rectifier circuit. Such a configuration is called a voltage doubler. A typical
doubler circuit is shown in Figure 3-23. In general, this type of circuit is used to provide
power for light loads.

Figure 3-23. A typical voltage doubler.

Notice that the capacitors in Figure 3-23 are in series. Like the voltage across batteries in
series, the voltage across each series capacitor in a voltage doubler is added together. This
addition provides the doubling action of the circuit, The total circuit capacitance is one-half
of the value of either capacitor: Therefore, for a given load current, the filter capacitor values
of a doubler are higher in value than those of a comparable full-wave rectifier circuit.

A full-wave voltage doubler uses both alternations of the ac input voltage. Similar to the
diodes in a full-wave bridge rectifier, the components of a doubler are paired-one diode and
one capacitor for each half-cycle of the input ac waveform. Only one diode/capacitor pair
charges at a time. Due to this action, the output ripple frequency is twice the source voltage
frequency. The charge paths of the doubler circuit are illustrated in Figure 3-24.
In Figure 3-24(a), the positive alternation of the input voltage forward biases diode D1. As a
result, filter capacitor C1 is charged. During this half-cycle, diode 02 is reverse biased and
capacitor C2 is not charging.
ECE 301 46

In Figure 3-24(b), the negative alternation forward biases D2. C2 is now charged.
During this half-cycle, D1 is reverse biased and capacitor C1 is not charging.
With very high values of R1 and R2, each capacitor charges to peak line value. Because the
discharge time of each capacitor is long (R1 x C1or R2 x C2), each capacitor holds its
charge while it is not being charged. The resulting output voltage of the circuit is shown in
Figure 3-24(c). Because both capacitors are in series, the output voltage is equal to the sum
of the voltages across each capacitor.

Figure 3-24. Charge paths of a voltage doubler.

In practice, a circuit load resistor takes some energy away from each capacitor during
the time in which the capacitor is not being charged. However, the discharge time is small
when the load resistor is kept at a relatively high value. The output voltage of the doubler is
approximately twice the peak input line voltage.
In practical applications, the values of filter capacitors tend to be unequal. The voltage
charge across each capacitor in series is therefore unequal. To prevent this inequality,
equalizing resistors are sometimes used. These resistors, R1 and R2 in Figure 3-24, evenly
divide the charge voltages within the circuit.
A practical voltage doubler circuit is shown in Figure 3-25. Note that the output voltage is
across the load resistor (RL). Also, the values of the equalizing resistors are made high so as to
draw little energy away from the load.

Figure 3.25. A practical voltage doubler circuit.

ECE 301 47

IV. PROCEDURE:

1. Adjust the dc power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.

2. Locate the FULL WAVE RECTIFICATION WITH POWER SUPPLY FILTER and
VOLTAGE DOUBLER circuit blocks. Connect the circuit shown in Figure 3-26. Install
the GENERATOR BUFFER as shown in the figure.
NOTE: in this procedure,. points A and B in the TI power transformer are used to power
the VOLTAGE DOUBLER circuit block.

Figure 3-26. Test circuit hook-up for the voltage doubler,

3. Connect channel 1 of the oscilloscope to the output of the GENERATOR BUFFER.

Adjust the external sine wave generator for a frequency equal to that supplied by your
local power utility. Set the generator for 20 Vpk-pk.

4. Between what two circuit component points is the circuit output voltage measured?
________________________________________________________________

________________________________________________________________

5. Based on a 20 Vpk_Pk circuit input voltage, what should the voltage across R1, R2, and
the circuit output be?
________________________________________________________________

________________________________________________________________

6. To verify your answer in step 5, measure and record the voltages across R1, R2, and
the circuit output.

________________________________________________________________

________________________________________________________________

7. Refer to the values recorded in step 6 and the values of R1 and R2. Should the output
ripple content be high or low?
________________________________________________________________

________________________________________________________________

8. Use channel2 of your oscilloscope to measure the ripple content of the output voltage.
Does the measurement confirm your answer in step 7?
NOTE: Remember to ac couple your scope input.

________________________________________________________________

________________________________________________________________

9. Place CM switch 18 in the ON position to place a 39K load resistor into the circuit.
Should this load increase or decrease the de output voltage and its ripple content?
________________________________________________________________

________________________________________________________________
ECE 301 48

10. Measure both the dc output voltage and its ripple content. Do your findings agree with
your answer in step 9?

________________________________________________________________

________________________________________________________________

11. What is the frequency of the ripple voltage?

________________________________________________________________

________________________________________________________________

12. Place CM switch 18 in the OFF position. Do not turn off the power sources. The
F.A.C.E.T. setup will be used for a review question.

V. EVALUATION:

1. Locate the VOLTAGE DOUBLER circuit block on the SEMICONDUCTOR DEVICES

circuit board. Connect the circuit shown in Figure 3-27. Place CM switch 17 in the ON
position. This circuit modification causes the circuit output voltage to
a. remain unchanged.
b. increase from its normal value
c. decrease from its normal value.
d. drop to zero.

Figure 3-27. Test circuit hookup for the voltage doubler.

2. The most likely cause of your circuit output voltage reading is

a. normal circuit operation.
b. that one side of the circuit is open.
c. that both sides of the circuit are open.
d. insufficient input voltage.

Turn off CM switch 17 and the power sources. Remove all circuit board connections.

3. In a voltage doubler circuit, each diode/capacitor pair of components will conduct

a. for alternate half-cycles of the input voltage.
b. for alternate cycles of the input voltage.
c. for the same half-cycle of the input voltage.
d. at the same time.

4. The basic function of a voltage doubler depends on the actions of rectifiers and
capacitors in
a. a series-opposing configuration.
b. one series-aiding loop.
c. parallel.
d. a series-aiding configuration.

5. A resistor may be placed across each filter of a voltage doubler to

a. equalize the capacitor voltage drops.
b. increase the filter voltage ratings.
c. load the output voltage.
d. decrease the filter voltage drops.

VI. CONCLUSION:
ECE 301 49

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 5
DIODE WAVESHAPING
(THE DIODE LIMITER)

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

I. OBJECTIVE:
 To be able to demonstrate the effects of a dc biased diode on an ac signal waveform
using a simple test circuit and verify the results with an oscilloscope.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this unit. Measured
values will differ from nominal due to normal circuit and instrument variations. Your
measurements in the following exercises will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise noted in
a procedure step:

External power source settings: +15 Vdc = ±3 percent

-15Vdc = ±3percent

POSITIVE SUPPLY and NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope: ±8 percent

III. THEORY:

Diode applications are not limited to rectification and voltage multiplication. The zener
characteristics of diodes, unidirectional conduction and avalanche, make them ideal devices
for waveshaping and voltage regulation.
The two types of waveshaping circuits associated with rectifier diodes are limiters
and clampers. Limiters are classified as peak clippers, base clippers, or slicers, depending
on how they modify an input waveshape. Clamping circuits are classified as dc restorers or
level shifters.
Figure 4-1 shows the basic effects of limiting and clamping on an input signal. Figure
4-1 (a) illustrates how limiting or clipping an ac input voltage allows only a portion of each
alternation to pass from input to output. Figure 4-1 (b) shows that the input waveform is
passed without limiting; however, the reference, or dc level, is shifted.
ECE 301 50

Figure 4-1. Examples of limiting and clamping.

The circuit in Figure 4-2(a) represents a basic limiter. The output voltage is limited by
the forward voltage of diodes CR1 and CR2. Resistor Rs determines diode current and
forms a voltage divider with the forward, or on, resistance of the diodes. As a result, the
output voltage is limited to approximately 1.4 V pk-pk.

Figure 4-2. Limiting (peak clipper) and clamping (level shifter) circuits.
The circuit in Figure 4-2(b) represents a basic clamper. This circuit clamps the output
voltage and shifts the input signal reference level. The change in reference level between input
and output signals is due to the dc blocking ability of capacitor Cs. In this circuit, the capacitor
charges through CR1 and discharges through Rp. Depending on the direction of CR1, the circuit
can clamp either the positive or negative peaks to zero (output circuit reference point).
Because diodes are used to provide the clipping action, you can control the clipping level
by introducing a dc bias voltage. Figure 4-3 shows a basic limiting circuit modified to include
variable bias voltages for the clipping diodes. In the figure, each diode starts to clip at a level
determined by its bias supply. For example, when the positive bias supply voltage of CR 1 is
increased, the diode conducts for a shorter period of the positive input alternation, resulting in a
higher amplitude positive output voltage.
ECE 301 51

Figure 4-3. Biased peak clipping circuit.

Combining dc biased clipping circuits provides a function called slicing. In a slicing circuit
(slicer), the output waveform consists of a slice of the input waveform. Figure 4-4 shows a
typical slicer and its waveforms.

In this slicer, CR1 and V1 form a peak clipper that limits the peak value of the input
positive alternation. CR2 and V2 form a base clipper that determines the point at which the
positive input alternation begins to be transferred to the circuit output. While the level of
input voltage exceeds V1, the circuit output voltage equals V1 - V2. While the level of input
voltage is less than V2, the output voltage equals zero volts. .

Limiting is removing an extremity of an input wave by electronic means. Circuits

that perform this function are called limiters or clippers. For example, a sine wave input
applied to a limiter can produce a square wave output. A limiter could be used to eliminate
either the positive or the negative peak of a peaked input waveshape.
Diode limiters are separated into two general circuit categories: series and parallel.
For the series type, the circuit diode is placed in series with the input signal. For the
parallel type, the diode is placed in shunt with the output terminals of the circuit.
Figure 4-6 shows two series limiters. In Figure 4-6(a), the output is positive; in
Figure 4-6(b), the output is negative. The figure shows a limiter function called half-wave
rectification.

Figure 4-6. Basic series limiters.

ECE 301 52

Figure 4-7 shows two parallel limiters. Recall that a forward biased diode drops
approximately 0.7 volts. Therefore, when the diode is forward biased, as in Figure 4-7(a).
the circuit output voltage is limited to its forward drop during the positive alternation of the
input waveform.

Figure 4-7. Basic parallel limiters.

The diode has a very high impedance when it is reverse biased (negative alternation of
the input waveform). Most of the circuit voltage appears at the circuit output because the high
impedance of the diode and Rs appear as a divider, with Rs much smaller than the impedance
of the diode.
The action of Figure 4-7(b) is identical to that of Figure 4-7(a) with one exception:
because the diode is reversed, the circuit of Figure 4-7(b) limits the negative input alternation to
Va, as shown by the output waveform.
Notice that the limiting point is fixed at a level equal to the forward voltage conducting
point of the diode. If this voltage could change, then the limiting point could be shifted. Adding a
second diode in series with the first would shift the limiting point to 1.4volts, or two diode drops
(O.7V+O.7V). However, the circuit would still be dependent on diode drops.
Figure 4-8 shows a circuit where the bias of the diode is independently set. The point at
which circuit limiting begins is controlled by the amount of bias added to the circuit. The starting
point of positive limiting increases as the bias supply voltage (VB) is increased; therefore, as
VB is increased, more and more of the input positive alternation appears at the circuit output.
The starting point equals VB plus the diode forward voltage. Example waveforms are provided in
the figure.

If the diode and bias supply were reversed, as shown in Figure 4-9, circuit action
would be the same as that of Figure 4-8, but the negative alternation would be limited
instead of the positive. The amount of negative input alternation produced in the output
waveform would depend on the setting of the negative Va supply, as illustrated by the
waveforms in the figure.
ECE 301 53

Figure 4-9. Negative adjustable limiter.

A modified form of limiting is called clamping. Clamping circuits are also referred
to as de restorers or baseline stabilizers. This type of circuit holds or shifts either
extreme of a waveform to a given reference level.
Figure 4-10 shows examples of how a clamping circuit can act on an input
waveform. An input waveform [Figure 4-10(a)] can be shifted so that its negative or
positive peak is clamped to zero, as shown in Figures 4-1 O(b) and (c). Figure 4-1 O(d)
illustrates how either peak can be shifted to a specified voltage level by an applied
independent bias supply.

Figure 4-10.

Figure 4-10. Waveform examples of clamping circuits.

Figure 4-11 shows how the simplest type of clamping circuit utilizes a diode in parallel
with the resistance of an ordinary RC coupling circuit. Depending on the polarity (direction) of
the diode, the circuit is either a positive clam per or a negative clamper.
ECE 301 54

Figure 4-11. Basic positive clamper.

In Figure 4-11 (a), clamping results because capacitor C1 charges during the short time
constant period in which diode CR1 is forward biased (R1 bypassed by CR1). C1 holds this
charge during the longer time constant period (C1 x R1) in which the diode is reverse biased
(R1 not bypassed).

To produce good waveform clamping, make sure that the charge time constant of the
capacitor is short and its discharge time constant is long-as compared to the period of the input
signal. If the discharge time is short, the capacitor will discharge, the bias across the resistor
will decrease, the output signal clamp level will shift, and the output waveform will be distorted
to a sloping waveform. If the discharge time constant is too long, then the capacitor will not be
able to respond to changes in the period or level of the input waveform, and the circuit output
will not be able to indicate small changes in the circuit input signal.

The accumulated charge of the capacitor in Figure 4-11 (a) produces a bias across
R1. This bias equals the negative peak of the input square wave, is positive at the cathode
of CR1, and tends to hold the diode in reverse bias. Notice that the diode is forward biased
on the negative alternation of the input waveform. Figure 4-11 (b) shows the relationship
between input and output waveforrns with respect to the circuit reference point.
IV. PROCEDURE:
1. Adjust the dc power sources to +15 Vdc and -15 Vdc. Turn the power source off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.
2. Locate the DIODE WAVESHAPING circuit block on the SEMICONDUCTOR DEVICES
circuit board. Connect the circuit shown in Figure 4-12. Install the GENERATOR
BUFFER to interface the external sine wave generator to the circuit block.

Figure 4-12. Initial waveshaping test circuit

3. Use a multimeter set for dc volts to monitor V1 and V2, in turn. Adjust the positive and
negative variable supplies for approximately zero volts on the multimeter.
ECE 301 55

4. Connect channel 1 of the oscilloscope to the output terminals of the GENERATOR

BUFFER. Set the generator for a 20Vpk-pk 1000 Hz sine wave.
NOTE: For this procedure, dc couple both input channels of your oscilloscope.
5. Connect channel 2 of the oscilloscope to monitor the circuit output (across R2). Should
the output waveshape be about the same as the circuit input waveshape?
_________________________________________________________________
_________________________________________________________________
6. With V1 set for zero volts, will CR1 limit the positive or negative alternation of the input
signal? To what level?
_________________________________________________________________
_________________________________________________________________
7. Using a two-post connector, connect CR1 into the circuit. Does the waveshape on
channel 2 of the oscilloscope clip at approximately 0.7 volts? Does your answer in step
6 agree with your measured results?
_________________________________________________________________
_________________________________________________________________
8. With V2 set for zero volts, will CR2 limit the positive or negative alternation of the input
signal? To what level?
_________________________________________________________________
_________________________________________________________________
9. Move the two-post connector from the CR1 connection point to the CR2 connection
point. Based on the channel 2 display, which alternation of the input voltage is limited?
_________________________________________________________________
_________________________________________________________________
10. What is the level of voltage to which the negative alternation is limited?
_________________________________________________________________
_________________________________________________________________
11. With both diodes in the circuit and both bias voltages set to zero, describe the expected
output waveform.
_________________________________________________________________
_________________________________________________________________
12. Use a second two-post connector to insert CR1 back into the circuit (keep CR2 in the
circuit as well). Based on the channel 2 display, describe the circuit output signal. Does
this agree with your answer of step 11?
_________________________________________________________________
_________________________________________________________________
13. Adjust V1 (positive variable supply) for a reading of +5 Vdc on your muItimeter. This
bias voltage causes either the positive or the negative alternation to be partially
reproduced in the output waveform. Which one?
_________________________________________________________________
_________________________________________________________________
14. What is the peak level of this voltage?
_________________________________________________________________
_________________________________________________________________
15. Adjust V2 (negative variable supply) for a reading of -5 Vdc on your multimeter. Based
on channel 2 of the oscilloscope, did this bias voltage affect the negative alternation of
the input waveform?
_________________________________________________________________
_________________________________________________________________
ECE 301 56

16. Make sure the osciilloscope is dc coupled for both input channels. Establish a known
reference point for each channel. Compare the input waveform to the output waveform
with respect to circuit common levels. Compare your displayed results to Figure 4-13.

Figure 4-13. Circuit waveforms with respect to common.

17. Based on the observed waveforrns, is the output signal dc level shifted with respect to
the input signal?
_________________________________________________________________
_________________________________________________________________
18. Does this circuit act as a dc restorer (baseline stabilizer)?
_________________________________________________________________

19. Modify your test circuit to look like the one shown in Figure 4-14. Remove CR2 from
the circuit.

Figure 4-14. Negative clamper test circuit.

20. Adjust the generator for a 1000 Hz, 10 Vpk-Pk square wave. Connect channel 1 of the
oscilloscope to the output terminals of the GENERATOR BUFFER. Connect channel 2
to the circuit output (for CR1 circuit). Ensure that the channel inputs are dc coupled.
21. Adjust V1 for zero volts. What effect does this circuit have on the input waveform
positive peaks?
_________________________________________________________________
_________________________________________________________________
22. Remove CR 1 from the circuit and insert CR2. Adjust V2 for zero volts. What effect
does this circuit have on the input waveform negative peaks?
_________________________________________________________________
_________________________________________________________________
23. Set CM switch 14 to the ON position. Based on the waveform displayed on channel 2 of
the oscilloscope, is the circuit discharge time too short or too long with respect to the
input signal?
ECE 301 57

_________________________________________________________________
_________________________________________________________________
24. Turn off CM switch 14 and the pOWfeJr sources. Remove all circuit board connections.

V. EVALUATION:
1. A circuit is used to clip a portion of its input waveform. The output waveform
a. can not be used because it is distorted.
b. is flattened off or limited to an arbitrary level.
c. is converted to an ac voltage.
d. is converted to a dc voltage.
2. A base line stabilizing circuit
a. rectifies and filters a sine wave.
b. converts a dc reference into an ac reference.
c. removes distortion from circuit input signals.
d. shifts or reinserts a dc component at the circuit output.
3. You can adjust the limiting level of a limiter's output waveform by
a. adding a second or third capacitor to the circuit.
b. using two diodes in parallel.
c. adding a dc bias voltage to the diode.
d. changing the value of circuit resistance.
4. In an RC coupled clamping circuit, the relationship of the circuit discharge time
constant and the input waveform period
a. should be long.
b. should be short.
c. does not matter.
d. is ignored if the RC value is less than one.
5. In the circuit of Figure 4-15,
a. R1 is effectively out of the circuit because CR1 is forward biased.
b. CR1 can not be forward biased because C1 blocks all dc voltages.
c. C1 charges through R1 and discharges through CR1.
d. C1 charges through CR1 and discharges through R1.

Figure 4-15. Basic clamper circuit.

VI. CONCLUSION:
ECE 301 58

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 6
ZENER DIODE AND VOLTAGE REGULATION

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. ZENER DIODE CHARACTERISTICS

I. OBJECTIVE:
 To be able to describe the dc characteristics of a zener diode using information from
this text and verify the results by plotting measured data.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

MEASUREMENT TOLERANCES

Nominal values have been determined for all measurements in this unit. Measured values
will differ from nominal due to normal circuit and instrument variations. Your measurements
in the following exercises will be acceptable if your power voltages and circuit
measurements lie within the following ranges from nominal unless otherwise noted in a
procedure step:

External power source settings: +15 Vdc = ±3 percent

-15Vdc = ±3percent

POSITIVE SUPPLY and NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope: ±8 percent
III. THEORY

Recall that a conventional silicon PN junction, such as a rectifier diode, has excellent
forward and reverse current characteristics. Its forward biased resistance is low and permits
a large current flow. Its reverse biased resistance is high and permits very little current to
flow. However, as the reverse bias voltage of a PN junction continues to increase, a voltage
is reached at which the junction breaks down, and current through the diode increases to a
high value. The voltage at which this breakdown occurs is the avalanche, or zener voltage.
A zener diode is a PN junction diode designed to use the avalanche characteristic.
Figure 4-16 compares a zener diode to a standard rectifier diode. The schematic symbols in
Figure 4-16(a) show that both the zener (CR1) and the rectifier (CR2) have a plus (anode)
and minus (cathode) end. The zener is set apart by the shape of its cathode end.
ECE 301 59

When both diodes are forward biased by the source voltage (Vs), as in Figure 4-
16(b), their voltage/current characteristics are identical. This likeness is indicated by the
O,7V drop across each diode.

When both diodes are reverse biased, as in Figure 4-16(c), the rectifier diode remains
in its off state, while the zener behaves like a conventional diode until V s reaches the
avalanche level. At this point, the zener conducts current and drops a voltage equal to its
avalanche value.
At the avalanche point, the reverse current through the zener increases rapidly while its
voltage drop remains practically constant. This feature of maintaining a relatively constant
voltage drop (Vz) over wide variations in reverse current (Iz) makes the zener diode a useful
voltage reference and regulating device.
Figure 4-17 shows the voltage/current characteristic curve of a conventional zener
diode. Notice that the horizontal voltage scales are marked off in different increments. In the
forward voltage direction, the voltage levels correspond to the typical forward voltage drops
associated with a PN junction. In the reverse direction, the voltage levels are determined by the
value of the avalanche, or breakdown voltage, of the zener being plotted (6.8 Vdc for this plot).

Figure 4-17. Voltage/current characteristic plot of a zener diode.

ECE 301 60

In the forward direction, the zener displays a typical PN junction plot. In the reverse
direction, very little zener current flows until the breakdown voltage (Vz on the plot) is reached.
At this point, heavy avalanche current flows through the zener.
NOTE: In practice, the amount of avalanche current is controlled bv resistance added to
the zener circuit. Otherwise, the zener would be damaged by excessive power dissipation.

As shown on the plot of Figure 4-17, the breakdown point of the zener is placed in a
circle called the zener region or knee region. This region indicates that a zener has a range of
voltages centered around a nominal value. For example, the zener used in this exercise has an
avalanche of 6.8 Vdc, ±10 percent, meaning that it can exhibit avalanche current between 6.12
volts and 7.48 volts.

Figure 4-18 shows a magnified view of the zener region of a typical general purpose
zener diode. As you can see, the voltage developed at the zener region does not represent a
sharp transition to 6.8 volts.

The zener test current (labeled IZT on the graph) is a current, specified by the device
manufacturer, where the zener voltage is within its specified tolerance value. Notice that below
IZT (toward zero current), the voltage drop of the zener shows a gradual decrease. This area is
known as the soft region of the zener, or an area where the voltage drop of the zener is not well
defined. Contrastively, the zener voltage is well-defined from IZT and beyond, an operating area
referred to as the stiff region. Practical circuits are designed so that the current through the
zener (lz) is around the IZT point.
Because a zener diode produces a voltage drop while current (lz) flows through it, power in the
form of heat is dissipated. The amount of power in a zener diode can be calculated from the
following form of Ohm's law:
Pz = Vz x Iz

Figure 4-19 shows a schematic of a typical zener test circuit. The source voltage (Vs) provides a
voltage higher than the zener value. R1 is selected to control the amount of avalanche current
that will flow. Zener CR1 provides a constant output voltage (Vz).

Figure 4-19. Typical zener test circuit.

The circuit of Figure 4-19 represents a series voltage divider. Therefore, Ohm's law can
be applied to solve for zener test current (IZT), the required source voltage to produce IZT or the
ECE 301 61

required value of R1 that will supply IZT . The controlling element is a solution that will ensure
IZT flowing through the zener diode.
Table 4-1 gives equations that solve for IZT based on known circuit values.

Table 4-1. Solutions for a zener test circuit.

Known
Circuit Formula To Solve For IZT
Values
Vs and Vz R1 = (Vs - Vz)/ IZT where Vs - Vz = VR1
R1 and Vz Vs = (IZT x R1) + VZ where IZT x R1= V R1
Vz and V R1 Vs = VZT+ VR1

The value of IZT for the zener diode used in the following procedure is 37 milliamps. Use
this value in the equations of Table 4-1.ln practice, the zener test current varies depending on
the voltage and power rating of the selected zener diode. You can find the required value of IZT
by consulting the device manufacturing specification sheet.

IV. PROCEDURE:
1. Adjust the dc power sources to +1 5 Vdc and -15 Vdc. Turn the power sources off.
Insert the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on
the power sources at this time.
2. Locate the ZENER DIODE REGULATOR circuit block on the board. Determine if current
flows through CR1 when it is forward biased and when it is reverse biased. Do your
readings agree with the results obtained from a standard rectifier diode?
3. Turn on the power sources. Adjust the positive and negative variable supplies for zero
volts. Connect the circuit shown in Figure 4-20(a). Will the source power supply in the
figure bias CR1 for zener operation?
____________________________________________________________________
____________________________________________________________________

Figure 4-20. CR1 test circuit

4. Adjust the negative variable supply to -10 Vdc. Use a two-post connector to insert this
supply into the circuit. Measure and record the circuit output voltage (Vz). Does your
reading indicate that CR1 is forward or reverse biased?
_____________________________________________________________________
_____________________________________________________________________
ECE 301 62

5. Remove the negative variable supply from the circuit. Insert the positive variable supply
into the circuit. Refer to Figure 4-20(b).
6. Measure and record the information required to complete Table 4-2. To perform this
step, adjust the positive variable supply to each VR value listed in Table 4-2. Then use
Ohm's current law and the voltage drop of R3 (VR3) to calculate the circuit current for
each VR value.
NOTE: Each circuit will produce different results. However,
your calculated current should be approximately 44 mA for
a 10 Vdc source voltage. For a nominal zener voltage of
6.8 Vdc, and an R3 value of 10 ohms. Your calculated
current will range between 0 mA and 100 mA. Also, the
maximum value of VR will depend on your circuit zener
diode. The table allows for worst case tolerance of
components; therefore. you may not require the complete
table for this step.
Table 4-2. Zener voltage and current data.

Reverse Voltage Calculated

VR Zener Current
(Measured) Iz = VR3/R3
2.0 Vdc
4.0 Vdc
6.0 Vdc
6.2 Vdc
6.4 Vdc
6.6 Vdc
6.8 Vdc
7.0 Vdc
7.2 Vdc
7.4 Vdc
7.8 Vdc

7. Based on the results of Table 4-2, why is the circuit current zero for
voltages below 6 Vdc?
______________________________________________________________
______________________________________________________________
8. Use the data in Table 4-2 to plot the voltage/current zener characteristic on the graph of
Figure 4-21. Connect each point on the graph with a line. Your results should be similar
to the curve in Figure 4-18.

Figure 4-21. Zener voltage/current graph.

ECE 301 63

9. Refer to the plotted information. Do the reverse characteristics of the zener diode match
those of a rectifier diode?
______________________________________________________________
______________________________________________________________
10. Refer again to the graph. Is the circuit output voltage nearly constant before the diode
breakdown point or after it?
______________________________________________________________
______________________________________________________________
11. Based on your data, does the power dissipation of the zener diode increase or decrease
beyond its avalanche point? Is this increase or decrease due to an increase in current or
to a decrease in current?
______________________________________________________________
______________________________________________________________
12. On the ZENER DIODE REGULATOR circuit block, connect the test circuit shown in
Figure 4-22. Use the GENERATOR BUFFER to interface the external sine wave
generator to the ZENER DIODE REGULATOR circuit block. Place CM switch 5 in the
ON position

Figure 4-22. Zener diode test circuit.

13. Connect channel 1 of the oscilloscope to the output of the GENERATOR BUFFER.
Adjust the generator for a 20 Vpk-pk, 100 Hz sine wave. Using a X10 probe, set
channel 1 for 0.5 V /cm and channel2 for 0.2 V /cm. DC couple both channel inputs. Set
the time base control for 1 ms/cm. Synchronize on the channel 1 positive slope.
14. Adjust the oscilloscope controls to duplicate the waveform illustrated in Figure 4-23.
Based on your measurements, what does point A of the test circuit waveform
represent?
______________________________________________________________
______________________________________________________________

Figure 4-23. Zener test circuit waveform.

15. What does point B of the test circuit waveform represent?
______________________________________________________________
______________________________________________________________
16. Based on the circuit waveforms, can the zener diode perform waveshaping?

______________________________________________________________
______________________________________________________________
ECE 301 64

17. Turn off CM switch 5 and the power sources. Remove all circuit board connections.

V. EVALUATION:
1. A zener diode differs from a conventional rectifier diode when the zener is
a. forward biased.
b. both forward and reverse biased.
c. reverse biased.
d. neither forward nor reverse biased.

2. A zener diode can be used as a

a. voltage reference.
b. voltage limiter.
c. constant voltage regulator.
d. All of the above.

3. Zener voltage refers to

a. the reverse breakdown voltage.
b. the forward breakdown voltage.
c. All of the above.
d. None of the above.

4. In the breakdown region, the resistance of a zener diode is

a. more than 100K.
b. between 100K and 10K.
c. less than 1OK.
d. zero.

5. A zener diode is rated at 6.8 Vdc. 1 watt. What is the maximum zener current the diode
can safely handle at room temperature?
a. 147 mA
b. 73.5 mA
c. 36.25 mA
d. None of the above.

VI. CONCLUSION:
ECE 301 65

B. ZENER DIODE VOLTAGE REGULATION:

I. OBJECTIVE:
 To be able to measure regulation properties using a zener diode shunt voltage
regulator and verify your results with a multimeter.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this unit. Measured
values will differ from nominal due to normal circuit and instrument variations. Your
measurements in the following exercises will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise noted in
a procedure step:

External power source settings: +15 Vdc = ±3 percent

-15Vdc = ±3percent

POSITIVE SUPPLY and NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent
Frequency/Phase shift/Amplitude (as measured by the oscilloscope: ±8 percent
III. THEORY:

A zener diode has a near constant voltage operating point called the avalanche,
breakdown, or zener voltage. When the diode is reverse biased and sufficient current flows
through its PN junction, the voltage across the device appears as a near steady dc voltage.
The zener diode shunt regulator can provide a near constant voltage for changes in both line
and load.
In Figure 4-24(a), a zener diode is replaced by a battery (Vz) that represents the
breakdown voltage of the diode. The source voltage (VsI is greater than Vz, and RL serves
as the circuit load resistor. To analyze the circuit, consider it. to be a series-parallel circuit.

Figure 4-24(a). Zener diode regulator equivalent circuit.

In Figure 4-24(b), the circuit current is distributed between the diode battery and the
load. The sum of these currents is supplied by the source voltage and passes through Rs.
Therefore, Rs must have a value that allows sufficient current to flow from the source into the
diode and load.

Figure 4-24(b). Zener diode regulator equivalent circuit.

ECE 301 66

According to the rules of a series-parallel circuit, the total circuit current equals the sum of
the individual currents. In this circuit, total current is determined from the following formula:
IT = Iz + IRL
The source and diode batteries are series-opposing; therefore, the voltage across Rs is:
VRS = Vs – Vz
Knowing both the total required current and the drop across Rs, you can apply Ohm's
law to find the ohmic value of Rs:
Rs = VRS/IT
The circuit polarities, voltage drops, current distribution, and formulas are shown in Figure 4-
24(c).

Figure 4-24(c). Zener diode regulator equivalent circuit.

Because Vz and RL are in parallel, the total current divides between the diode and the
load. Recall that the zener requires a minimum current to remain beyond its knee (or avalanche
point). If this current is defined as IZT, then the total circuit current supplied by Rs must equal IZT
+ IRL.
By Ohm's law, the load current increases when the load resistor decreases. This
increasing load current takes away from the zener current. If the load resistance drops below a
critical value, all of the current flows through the load. Very little current remains for the zener,
so it drops out of regulation (into the soft region of the knee). If zener current drops low enough,
the diode stops conducting and all voltage regulation is 10s1. At this point, the circuit acts as a
series voltage divider because the zener diode is no longer conducting.
If the load resistor opens, all of its current flows through the zener (in addition to IZT). As
a result, the power dissipation of the zener increases.
Between the critical load value point and the open load resistor value operating point, a
change in load resistor value produces a change in how the current between the zener and
load is shared. However, the voltage of the zener, and therefore the load voltage, remains
essentially constant.
Changes in load voltage can be measured and are related to a factor called regulation.
Regulation is a measure of the voltage change across the load due to a change in line voltage
and load, Regulation is usually specified in percent and is calculated by the following formula:

% Regulation = [ Vout (no load) - Vout (full-load) / Vout (full-load) ] x 100

Figure 4-25 shows the power distribution equations of a zener diode shunt regulator
circuit. Maximum power is dissipated in the zener when the load circuit is open (no power
dissipated by the load). Minimum power is dissipated in the zener when the load circuit is
maximum. The power in Rs is determined at the maximum total circuit current point.

Figure 4-25. Power equations for a zener shunt regulator.

ECE 301 67

Because the circuit source must supply more power than that required by the load to
maintain proper regulation, the zener shunt regulator is less than 100 percent efficient. For the
circuit in Figure 4-25, the total source power equals the sum of the power dissipated by each
circuit element. Therefore, the circuit efficiency can be calculated from the formula:

% Efficiency = [ Power in load / Power required from source ] x 100

Figure 4-26 is a schematic representation of the test circuit you will use in the following
procedure. In this circuit, the load resistor value can be varied by the action of rheostat R4. R5
is part of the load and acts to protect R4 when R4 is set to its minimum value (CCW position). A
minimum load resistor value means maximum load current and therefore maximum power
dissipation in the load.

Figure 4-26. Zener shunt regulator test circuit.

R3, which would not be included in a practical circuit, serves as a convenient current-
sensing resistor. Therefore, the zener current can be calculated from the Ohm's law formula:
Iz = VR3 /R3
Because of the near constant voltage action of zener diode CR1, most changes in Vs
are not passed through to the load. For small changes in Vs. the load current remains
unchanged because Vz is constant and RL does not change. However, changing Vs does
cause the current through R2 to change. Because IL does not change but IR2 does, the zener
current must change. Within limits, this change in zener current results in very small changes (if
any) in zener voltage. As a result, the zener shunt regulator can maintain a near constant load
voltage within specified circuit limits for changes in both line voltage and load.

IV. PROCEDURE:
1. Adjust the dc power sources to+15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.
2. Locate the ZENER DIODE REGULATOR circuit block on the SEMICONDUCTOR
DEVICES circuit board. Adjust R4 to its maximum CCW position (for maximum load
resistance value and minimum load current). With an ohmmeter, measure and record
the load resistance and R3 values.
______________________________________________________________________
______________________________________________________________________
3. Connect the circuit shown in Figure 4-27. Turn on the power sources. Adjust the
positive variable supply for +10V. Is diode CR1 forward or reverse biased?
______________________________________________________________________
______________________________________________________________________

Figure 4-27. Zener shunt regulator test circuit.

ECE 301 68

4. Based on the answer to question 3, what is the expected circuit output voltage (across
the load) (Vz + VR3)?
______________________________________________________________________
______________________________________________________________________
5. Measure and record the circuit output voltage. Does your measured value support your
step 3 answer?
______________________________________________________________________
______________________________________________________________________
6. Adjust the positive variable supply to the values indicated in Table 4-3. Calculate the
required currents based on your measured values of RL and R3 (step 2). Complete the
table for each value of source voltage (positive adjustable supply).
NOTE: The voltage drop of R3 (VR3) will reduce to zero
when the zener drops out of conduction. Complete the
remainder of the table by indicating that VR1 is zero
volts.
Table 4-3. Line regulation data.

Source Load Load Current Zener Current

Voltage Voltage VR3 IRL = VRL/RL IZ = VR3/R3
(Vs) (VRL)
10 Vdc
9 Vdc
8 Vdc
7.8 Vdc
7.6 Vdc
7.4 Vdc
7.2 Vdc
7.0 Vdc
6.8 Vdc
6.6 Vdc
6.4 Vdc
6.2 Vdc
6.0 Vdc
5.0 Vdc
4.0 Vdc
7. Plot the data from the Source Voltage and Load Voltage columns
onto the graph of Figure 4-28.

NOTE: Your results should show a near constant load voltage above the zener
avalanche point

Figure 4-28. VLOAD vs. VSOURCE data graph

ECE 301 69

8. Based on your data. what is the load voltage change when the source voltage changes
3 volts (use 10 Vdc as your starting point)?
_____________________________________________________________________
_____________________________________________________________________
9. Does the data indicate that a zener regulator circuit provides good line-to-Ioad
regulation?
_____________________________________________________________________
_____________________________________________________________________
10. What value of VR3 indicates that the zener diode is no longer in conduction?
_____________________________________________________________________
_____________________________________________________________________
11. As the value of zener current decreased, did the zener operating point move toward or
away from its knee?
_____________________________________________________________________
_____________________________________________________________________
12. Adjust the positive supply for +10 Vdc. Set the R4 control to the maximum CCW
position. Use the voltage drop across R5 to determine load current (IR5 = VR5/R5).
Record your results at each required load current point in Table 4-4.
NOTE: Adjust R4 to obtain each load current as specified in the table. Due to component
tolerances, use the formula given above to calculate IR5 at the minimum and maximum
R4 points.
Table 4-4

13. Use VR3 recorded in Table 4-4 and the Ohm's law current formula to calculate the zener
current (IR3 = VR3/R3). Record your results in Table 4-4.
14. Using the data from Table 4-4 and the voltage/current graph of Figure 4-29, plot the
circuit output voltage versus load current. Label this line the LOAD VOLTAGE.

Figure 4-29. Voltage /currentgraph

15. Using the same graph and data table, plot the zener current versus output voltage.
Label this line the ZENER CURRENT.
ECE 301 70

16. Based on your data, is the output voltage regulation better at higherlevels of zener
current or at low to zero levels of zener current?
_____________________________________________________________________
_____________________________________________________________________
ECE 301 71

23. Set the source voltage for +10 Vdc. Do not remove power from the circuit. The
F.A.C.E.T. setup will be used for two review questions.

V. EVALUATION:

1. Locate the ZENER DIODE REGULATOR circuit block on the SEMICONDUCTOR

DEVICES circuit board. Connect the circuit shown in Figure 4-30. Place CM switch 6 in
the ON position. Vary R4 from end-to-end. Based on the circuit output voltage, the
regulator
a. is operating properly.
b. has poor regulation.
c. All of the above.
d. None of the above.

Figure 4-30. Zener shunt regulator test circuit.

2. As you vary R4 from end-to-end, measure the drop of R3. Based on the zener current,
you can say that the value of R2
a. is correct.
b. must be higher.
c. should be lower.
d. has no effect on the zener current.

Turn off CM switch 6 and the power sources. Remove all circuit board connections

3. In a zener diode shunt regulator, excess circuit voltage is dropped across the
a. zener diode.
b. load resistor.
c. series dropping resistor.
d. power source.

4. What determines the maximum allowable zener current?

a. zener voltage rating
b. zener wattage rating
c. All of the above.
d. None of the above.

5. The zener diode regulates for all values of

a. input voltage.
b. zener current.
c. forward bias and zener current beyond the barrier voltage of the PN junction.
d. reverse bias and zener current beyond the breakdown point.

VI. CONCLUSION:
ECE 301 72

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 7
BJT CHARACTERISTICS AND BIASING

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. TESTING THE JUNCTIONS OF A TRANSISTOR

I. OBJECTIVE:
 To demonstrate a basic understanding of transistor fundamentals
 To be able to test transistor junctions using a transistor and verify your results with a
multimeter.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board
 Power Supply, 15 Vdc (2 required)
 Multimeter
MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this unit. Measured values
will differ from nominal due to normal circuit and instrument variations. Your measurements in
the following exercises will be acceptable if your power voltages and circuit measurements lie
within the following ranges from nominal unless otherwise noted in a procedure step:
External power source settings: +15 Vdc = ± 3 percent
-15 Vdc = ± 3 percent

POSITIVE SUPPLY and NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent

III. THEORY:
A transistor is a device constructed from two PN junctions. Figure 5-11 shows the
two possible types of transistors: an NPN or a PNP transistor.

PN JUNCTION 1 PN JUNCTION 2

Figure 5-11. PN junction connections.

ECE 301 73

Because each section of a transistor is formed by a PN junction, each section

exhibits the same characteristics as does a rectifier diode. In the forward biased
direction, the junction conducts current. In the reverse biased direction, the junction does
not conduct current. The transistor junction is similar to a typical PN junction (rectifier
diode).
An ohmmeter is used to test transistor junctions in the same way it is used to test
a diode junction. When the ohmmeter leads are connected to forward bias the junction,
the meter indicates conduction if the junction is good. When the ohmmeter leads are
connected to reverse bias the junction, the meter indicates no conduction if the junction
is good. In a good transistor, there is no conduction between the collector and emitter
terminals regardless of the meter probe connections.
If an ohmmeter indicates an overload (off scale) when a transistor junction is
forward biased or reverse biased, the transistor junction is open; the conduction path is
broken. If an ohmmeter indicates a zero or a very low reading when a transistor junction
is forward biased or reverse biased, the transistor junction is shorted.
If an ohmmeter reading indicates current flow when a transistor junction is
forward biased or reverse biased, the transistor has high leakage current and is
defective. If an ohmmeter indicates a zero or a very low reading when connected across
the collector and emitter, there is a short or high leakage current.

Because transistor devices provide a wide range of control applications in

electronics, many different transistor sizes and shapes have been developed.
Figure 5-1 represents a sampling of such devices.

Figure 5-1. Transistor packaging.

Transistors range from low power devices capable of dissipating several hundred milliwatts,
such as a plastic TO-92 case, to high power devices, such as a TO-3 case, which can dissipate
50 watts or more with a heat sink. In addition, transistors can operate from dc to very high
frequency ranges. In fact, special types of transistors are designed specifically for high
frequency use.

Transistors can act as on/off switches, amplifiers, oscillators, modulators, and many other
devices. Regardless of how a device is configured, all transistors have the same fundamental
operating principles.
For example, all transistors are current-amplifying devices. A small change of input current is
used to produce a large change in output current by a transistor mechanism called gain.
In earlier experiments, you learned that a PN junction is formed when P type and N type
materials are joined together. A transistor can be described as a three layer semiconductor
device consisting of two PN junctions. In the transistor construction, a thin layer of one material
type is sandwiched between two layers of the opposite type material.
Because there are two basic material types, there can be only two general types of transistors.
These types are NPN and PNP. Figure 5-2(a) shows the schematic symbol of each. In the NPN
type (Q1), the arrowhead points away from the body of the device. In the PNP type (Q2), the
arrowhead points toward the body of the device.
ECE 301 74

Figure 5-2. Transistor identification.

On schematics, transistors are typically represented by the letter Q and a number.

Notice that Q1 and 02 in Figure 5-2(a) both have three terminals, or leads, connected to the
transistor body. These transistor parts are labeled in Figure 5-2(b) as the emitter (arrowhead
lead), base, and collector.
Transistor terminals are identified by the letters E (for emitter), B (for base), and C (for
collector) in Figures 5-1 and 5-2(c). These designations apply to both types of transistors and
to the different packaging styles (case sizes) available.
Because 8 transistor combines two PN junctions, diodes can be used to represent the
polarities associated with each transistor type.
A transistor is made up of two junctions: the base-emitter junction and the base-
collector junction. Each junction of the device is a practical diode, so each junction has a
forward and a reverse bias direction. Like a diode, each junction can be tested for a forward-to-
back ratio.
Figure 5-3 represents the PN structure of an NPN transistor. Figure 5-4 shows a PNP
transistor following the same basic diode placement as that of the NPN. However, the direction
of the diodes are reversed, so the operation of the PNP device is opposite to that of the NPN
device.

If you examine the diode relationship of both figures, you should see that the voltages
required to forward bias either junction are low in value. Typically, the forward voltage drop of a
transistor junction is 0.7 volts. Therefore, transistor device operation requires low voltages
across forward biased junctions (not the circuit voltages).
As with reverse and forward biased diodes, reverse biased junctions generally exhibit
much larger voltages than do forward biased junctions. The amount of reverse voltage a
transistor can tolerate depends on how the device is manufactured. In general, transistors are
available with a reverse breakdown voltage in ranges as low as 5 Vdc up to hundreds of volts.
In practice, transistors are current-.controlling (amplifying) devices. Although the diode
model is accurate for testing, it does not reflect the proper biasing needed to operate a
transistor in an actual circuit.
In order for the device to be on, the base-emitter junction must be forward biased while
the base-collector junction is either forward or reverse biased. In this state, the device has a
small base current that controls the flow of a much larger collector current.
ECE 301 75

If the base-emitter junction is reverse biased, the device is off. The transistor acts as an
open circuit, and zero current flows. Figure 5-5 shows the polarity of biasing voltages required
for the NPN transistor. In Figure 5-5{a}, the device is biased to its off state. In Figure 5-5(b), the
device is biased to its on state.

Figure 5-5. NPN transistor biasing.

Figure 5-6 shows the polarity of biasing voltages required for the PNP.
transistor. In Figure 5-6(a), the device is biased to its off state. In Figure 5-6(b), the
device is biased to its on state.

In both figures, notice that the base-collector junction supply (VBC) does not
change its polarity between the on and off states of the transistor. In both states, the
VBC supply reverse biases the base-collector junction.
The base-emitter junction supply (VBE) reverse biases the transistor junction
to turn the device off. VSE forward biases the same junction to turn the device on.
The bias supplies of the NPN transistor are connected in the opposite
direction to those of the PNP transistor. Based on this bias description, the base-
collector supply polarity is established once the type of transistor is selected. The
base-emitter bias supply is controlled by the circuit and used to reverse (turn off) or
forward (turn on) bias the transistor junction.
Transistors are used to control the flow of current. Therefore, when the
base-emitter junction of either type of transistor is forward biased, current flows
between the base and the emitter (control current). In addition, base current causes
a collector current (the controlled current) to flow. Figure 5-7 shows the relationship
of these currents in forward biased NPN and PNP transistors.

Figure 5-7. Transistor current distribution

ECE 301 76

The amount of current that flows through a practical transistor must be limited
because excessive current damages the device. Figure 5-8 shows NPN and PNP
transistors that are properly biased and current-limited by external circuit resistances.

Figure 5-8. Practical NPN and PNP circuits.

In each of these circuits, resistor RC determines the amount of collector current. A
series loop is formed by the combination of Vcc (source voltage), Rc (collector resistor),
and the transistor collector-to-emitter terminals. Therefore, the source voltage equals the
sum of the voltage drop across the collector resistor and the collector-to-emitter voltage
(Vcc = VRC+ VCE).
Resistor RB limits the amount of base current. A series loop is formed by the
combination of VB (bias voltage), RB (base resistor), and the transistor base to-emitter
terminals. Therefore, the bias voltage equals the sum of the voltage across the base
resistor and the base-to-emitter voltage (VB = VRB + VBE).
Transistor gain allows a small base current to be amplified into a much larger collector
current. The base current is provided by the transistor input circuit, VB and RB in Figure 5-8.
The amplified collector current is provided by Vcc and RC. The relationship between base
current (IB) and collector current (IC), as determined by gain, is IC /IB.
Usually, the desired collector current is known. RC is then selected to provide this
current. Base current is determined from the required collector current divided by the device
gain. Knowing the base current allows for the selection of RB. Because gain is a transistor
property, its value is given on the manufacturer specification sheet.

Figure 5-9 shows a typical NPN transistor circuit. The collector current must be 10 mA.
Specified Q1 gain is 100. Based on the series relationship of the emitter-collector circuit. the
value of Rc can be determined from the formula:
RC = (VCC – VCE) / lC
Required base current is determined from the formula:
IB = lC/gain of Q1
Based on the series relationship of the base-emitter circuit, RB is determined from the formula:
RB = (VB - VBE)/IB
These circuit equations are solved in Figure 5-9.

Figure 5-9. Typical NPN transistor circuit.

ECE 301 77

Figure 5-10 shows the typical voltage drops of a transistor circuit with
maximum collector current. The circuit input is measured at the end of the
base resistor away from the transistor base terminal. The circuit output
voltage is measured from the collector to the emitter.

Figure 5-10. Typical voltage drops around a forward biased NPN transistor circuit.

If a transistor is pushed into hard conduction (a condition called saturation), the base-collector
junction becomes forward biased.

Because the transistor has a voltage drop across it and a current flowing through
it, it dissipates power in the form of heat. The amount of power dissipated can be
calculated from the power formula:
PCE = VCE X IC

NEW TERMS AND WORDS

 base - the section of a transistor sandwiched between the emitter and the collector.
 collector - the section of a transistor that forms part of a base-collector junction
 emitter - the section of a transistor that forms part of a base-emitter junction.
 forward biased junctions - transistor PN junctions biased to conduct current,
 gain - the property of a transistor that allows a small input current to be amplified into a
much larger output current. It is equal to the ratio of collector current to base current.
 junctions - the points of contact between the emitter and base or the base and collector
sections of a transistor.
 linear device - a device that operates between the full off and full on states.
 NPN - a transistor type that has a Ptype material sandwiched between two N type materials.
 PNP – a transistor type which has an N type material sandwiched between two P type
materials.
 reverse biased junctions - transistor PN junctions biased so that the device does not
conduct current.
 transistor - a semiconductor device designed to act as a current amplifying or current control
device.
 V CE(sat) - abbreviation for the voltage across the collector-emitter terminals of a transistor
when it is in its full conducting state (saturation, or SAT).

IV. PROCEDURE:
1. Adjust the dc power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.

2. Locate the TRANSISTOR JUNCTION circuit block. You will use an ohmmeter (digital or
analog) to test the junctions of the diodes and transistors on the circuit block.

3. Connect your ohmmeter to forward bias and then reverse bias the junction of diode CR1.
What does the ohmmeter indicate when CR1 is forward and reverse biased?

_____________________________________________________________________

_____________________________________________________________________
ECE 301 78

4. Connect your ohmmeter to forward bias and then reverse bias the base-collector
junction of Q1. Are the ohmmeter readings the same as CR1 ?
_____________________________________________________________________

_____________________________________________________________________

5. Connect your ohmmeter to forward bias and then reverse bias the junction of diode CR2.
What does the ohmmeter indicate when CR2 is forward and reverse biased?

_____________________________________________________________________

_____________________________________________________________________

6. Connect your ohmmeter to forward bias and then reverse bias the base-emitter junction
of Q1. Are the ohmmeter readings the same as CR2?
_____________________________________________________________________

_____________________________________________________________________

7. Repeat the same measurements on diode CR3 and the base-collector junction of Q2
and on diode CR4 and the base-em1tter junction of Q2. Do the diode and transistor
junctions have the same readings?

_____________________________________________________________________

_____________________________________________________________________

8. With the ohmmeter, test the conduction between the cathode of CR1 and the cathode of
CR2. Is there conduction?

_____________________________________________________________________

_____________________________________________________________________

9. Would the ohmmeter indicate conduction across the emitter and collector terminals of
Q1 ?
_____________________________________________________________________

_____________________________________________________________________

10. With the ohmmeter, test the conduction between the emitter and collector of Q1. Is there
conduction?
_____________________________________________________________________

_____________________________________________________________________

11. With the ohmmeter, test the conduction between the anode of CR3
and the anode of CR4. Is there conduction?
_____________________________________________________________________

_____________________________________________________________________

12. Would the ohmmeter indicate conduction across the emitter and collector terminals of
Q2?
_____________________________________________________________________

_____________________________________________________________________

13. With the ohmmeter, test the conduction between the emitter and
collector of Q2. Is there conduction?
_____________________________________________________________________

_____________________________________________________________________
ECE 301 79

14. Place CM switch 1 in the ON position. Connect your ohmmeter to the junctions of CR1
and CR2. Are the diodes good or bad?
_____________________________________________________________________

_____________________________________________________________________

15. Place CM switch 1 in the OFF position. Place CM switch 2 in the ON position. Use your
ohmmeter to test the junction of Q1. ls Q1 good or bad?
_____________________________________________________________________

_____________________________________________________________________

16. Place CM switch 2 in the OFF position. The F.A.C.E.T. setup will be used for a review
question.

V. EVALUATION:
1. The emitter-base junction of a transistor conducts
a. in both directions.
b. in one direction.
c. only for high applied voltages.
d. only for low applied voltages.

2. Locate the TRANSISTOR JUNCTION circuit block on the SEMICONDUCTOR DEVICES

circuit board. Place CM switch 3 in the ON position. Testing the conduction state of Q2
indicates
a. that the base connection is open.
b. a shorted base collector junction.
c. an open base-emitter junction.
d. that the collector connection is open.

Place CM switch 3 in the OFF position.

3. The terminals of a transistor are labelled

a. E, PN, C.
b. PN, 8, PN.
c. E, 8, E.
d. E, 8, C.

4. The material that is sandwiched by the two outer sections of a transistor form
a. the emitter section.
b. the collector section.
c. the base section.
d. a CE junction.

5. If the type of transistor being tested is unidentified (you do not know if it is a PNP or an
NPN), a multimeter
a. can be used to determine its type.
b. can not be used to determine its type.
c. should not be used until the type is known.
d. will provide unreliable results.

VI. CONCLUSION:
ECE 301 80

B. PNP TRANSISTOR CURRENT CONTROL CIRCUIT

I. OBJECTIVE:
 To be ableto determine proper biasing and circuit voltages using a PNP current control
circuit and verify the results with a multimeter.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board Power
supply, 15 Vdc (2 required)
 Multimeter

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this experiment. Measured
values will differ slightly from nominal due to normal circuit and instrument variations. Your
measurements in the following exercises will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise noted in
a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLY and

NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent

III. THEORY:
Transistors are current control devices. As such, they can be configured as switches
that interrupt current flow to a load. Figure 5-12 compares this transistor application to the
action of a switch.

Figure 5-12. Transistor and switch comparison.

When switch S 1 is closed, current flows from the source voltage, through the switch.
through the circuit load. and back to the source. When transistor Q1 is forward biased (on),
the circuit action is the same. Current flows from the source, through the on transistor,
through the circuit load. and back to the source. The current paths of the closed switch and
the on transistor form series circuits.

When switch S2 is opened. the circuit is interrupted and current does not flow
through the circuit load. In the same way, when transistor Q2 is reverse biased (off), current
does not flow through the circuit load.
ECE 301 81

Assume the load element of Figure 5-12 is replaced with a light-emitting diode (LED),
as shown in Figure 5-13. The LED (DS1) generates a visible light when transistor Q1 is
forward biased (on), indicating that current flows. When Q1 is reverse biased (off), current
does not flow, and DS1 does not generate light. The LED provides a visual aid for your
determining the status of the transistor.

Figure 5-13. PNP and LED control circuit.

The circuit formed by Vs, DS1, R2, and Q1 is a series loop; therefore, the rules for
a series circuit apply to it. The sum of the voltage drops around the closed loop
should equal the source supply (Vs). We can determine Vs by applying the
following equation. where VLED is the voltage drop across DS1, VR2 is the voltage
drop across R2, and VCE(SAT) is the voltage drop across Q1 when Q1 is in the
saturation mode:

Vs = VLED + VR2 + V CE(sat)

The transistor is forward biased very forcefully, which results in the saturation operating
mode (SAT). During saturation, the transistor drops the lowest possible voltage across its collector-
to-emitter terminals.
The drop of Q1 is typically less than 0.5 Vdc, and the drop of DS1 is about1.2 Vdc. The loop
equation becomes:

Vs = 1.2 Vdc + VR2 + 0.5 Vdc

When the value of the source voltage is given (15 Vdc), and when a value of LED current
(lLED) is selected (13 mA), the complete circuit loop is defined and the required R2 value can be
calculated. In our example, the value of R2 is calculated from the following equation:

Notice that the equation has voltage over current (VR2/IR2), the same relationship established by
Ohm's law (R = V/ I).

When the transistor is biased to its off state, the resistance of the transistor is infinite (the same as
with an opened switch). Because the rules for a series loop state that all of the circuit source
voltage is dropped across the opened switch (emitter-collector terminals of Q1), load current does
not flow, and the LED does not glow.
Recall that a transistor uses gain to multiply the input or base current. From gain, a small
base current can be multiplied into a much larger collector current. The value of the gain of a
transistor is provided by the manufacturer specification sheet. In Figure 5-13, the gain of Q1 selects
the value of R1. The gain (HFE or beta) is expressed as a ratio of collector current to base current:
HFE = lc / Ib
The gain formula for the transistor determines the minimum base current required to
keep a transistor in saturation. When the input signal to the base is too low, or when the
circuit base resistor is too high, the transistor becomes starved. This condition (of insufficient
base drive) causes the transistor to come out of saturation. The transistor collector-to-emitter
voltage increases, and its collector current decreases.
ECE 301 82

In the following procedure, use a multimeter to measure the individual component

voltage drops to define the circuit in Figure 5-13. Use the measurements with Ohm's law to
determine the circuit currents. Because voltage and current can be determined, the power
dissipated by each component can be calculated. Figure 5-14 shows the meter placement
required to measure the key circuit voltages.

Figure 5-14. Multimeter placement for voltage measurements.

Once the measurements are made, use the voltage readings and the formulas given in Table
5-1 to find circuit current and power dissipation.

Table 5-1. Circuit equations.

IBASE : VRI / R1 PDS1 = IDS1 x VDS1

IDS1 = Ic= VR2/ R2 PQ1 = Ic x VCE
CURRENT GAIN= Ic / Ib PR2: lc2 x R2 or VR22/ R2 or Ic x VR2

IV. PROCEDURE:
1. Adjust the dc power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.

2. Locate the PNP DC BIAS circuit block on the SEMICONDUCTOR DEVICES circuit
board. Connect the circuit shown in Figure 5-15.

Figure 5-15. PNP bias test circuit.

3. Based on the required circuit connection, is Q1 biased in the forward or reverse
direction?
__________________________________________________________________

__________________________________________________________________

4. When power is applied to the circuit, will DS1 be on or off?

__________________________________________________________________

__________________________________________________________________
ECE 301 83

5. Turn on the power sources. What is the conduction state of Q1? What circuit indication
confirms your answer?
__________________________________________________________________

__________________________________________________________________

6. If Q1 is in its nonconducting state, what should the measured voltage drop between the
emitter and collector (VCE) be?
__________________________________________________________________

__________________________________________________________________

7. Use your multimeter to measurable drop between the emitter and the collector of Q1.
Does your reading agree with the answer recorded in step 6?

NOTE: Connect the ground (-) lead of the

multimeter to the emitter of QI. The multimeter
input impedance provides a shunt current path
around QI, which causes the voltage reading to
be less than expected.

8. Move the R1 two-post connector from the plus source voltage to the minus source
voltage. Does this change cause Q1 to conduct?
__________________________________________________________________

__________________________________________________________________

9. What circuit indication confirms your answer to step 8?

__________________________________________________________________

__________________________________________________________________

10. In this state, what should the voltage drop (VCE) of Q1 be?
__________________________________________________________________

__________________________________________________________________

11. Measure the voltage drop of Q1. Does your result support the answer recorded in step
10?
__________________________________________________________________

__________________________________________________________________

12. With your multimeter, measure the circuit voltages required to complete Table 5-2. Refer
to Figure 5-16 for your circuit configuration.

NOTE: Ignore the minus (-) polarity of the readings for

this step.

Figure 5-16. Circuit required to complete Table 5-2.

ECE 301 84

Table 5-2.
TEST POINT MEASURED
READING
Source Voltage (Vs)
VDSI
VR2
V CE(SAT)
VBE
VRI
13. Based on the results recorded in Table 5-2, complete Table 5-3. Use the formulas
provided for your calculations.
Table 5-3

CALCULATION RESULT
Ic = IDS1 - IR2 = VR2/R2
lB =VR1 /R1
PQ1: VCE(SAT) x Ic

14. Refer to Tables 5-2 and 5-3 for steps 14 through 18. When a transistor is operated in a
saturated mode, should it have a high or a low voltage drop?
__________________________________________________________________

__________________________________________________________________

15. In the series loop made up of transistor Q1, R2, and DS1, which component drops most
of the circuit source voltage?
__________________________________________________________________

__________________________________________________________________

16. Is the base current greater than, equal to, or less than the load current?

__________________________________________________________________

17. What is the current gain of the circuit (IC/IB)?

__________________________________________________________________

__________________________________________________________________

18. Is the power dissipation of Ql low or high?

__________________________________________________________________

19. Does this mean that any transistor in saturation will have a low power dissipation?
__________________________________________________________________

__________________________________________________________________

20. If the value of Rl were increased to a much higher value while all other circuit
parameters remained the same, would the brightness of DS1 increase or decrease?
Would the voltage across Q1 increase or decrease?
__________________________________________________________________
__________________________________________________________________

21. Place CM switch 9 in the ON position. Does the CM cause the glow of DS1 to brighten
or diminish?
__________________________________________________________________

22. Measure and record the voltage drop of Q1. Has it increased, decreased, or remained
the same? Is the transistor in its saturated mode of operation?
__________________________________________________________________
__________________________________________________________________
ECE 301 85

23. Use the voltage drop of R2 and Ohm's law to calculate Ic. Using the voltage drop
measured in step 22 and the current calculated in this step, compute the power
dissipated by Ql. Does the power increase or decrease when Ql is taken out of
saturation?
__________________________________________________________________

__________________________________________________________________

24. Measure VBE and VCB. Which junction is forward biased and which junction is reverse
biased?
__________________________________________________________________

__________________________________________________________________

25. Place CM switch 9 in the OFF position. Do not turn off the power sources. The
F.A.C.E.T. setup will be used for a review question.

V. EVALUATION:

1. Locate the PNP DC BIAS circuit block on the SEMICONDUCTOR DEVICES circuit
board. Connect the circuit shown in Figure 5-17. Place CM switch 8 in the ON position.
Based on the circuit configuration, the LED should be glowing. Measure the voltage at
the cathode of DS1, with respect to circuit common. The LED does not glow because
a. the circuit between the source voltage and DS1 is open.
b. Q1 is reverse biased.
c. Q1 is forward biased.
d. DS1 is reverse biased.

Turn off CM switch 8 and the power sources. Remove all circuit board connections.

2. The VCE voltage drop of a low power plastic transistor in saturation is

a. much greater than one volt.
b. about one volt.
c. less than one volt.
d. equal to the circuit supply voltage.

Figure 5-17. PNP LED control circuit.

3. VCE of a low power transistor in its off state is

a. much greater than one volt.
b. about one volt.
c. less than one volt.
d. equal to the circuit supply voltage.

4. A transistor in its non saturated conducting state has

a. a forward biased base-emitter junction and a reverse biased base collector
junction.
b. a reverse biased base-emitter junction and a reverse biased base collector
junction.
c. both junctions reverse biased.
d. a zero voltage drop across the transistor.
ECE 301 86

5. The gain of a transistor allows

a. the transistor to multiply a small base current into a larger collector current.
b. a small base current to drive a transistor into saturation.
c. a small base current to control a larger collector current.
d. All of the above.

VI. CONCLUSION
ECE 301 87

C. EMITTER-BASE BIAS POTENTIALS

I. OBJECTIVE:
 To determine the effects on transistor performance using changes in bias voltage,
collector voltage, and collector load.
 To determine the effects on base current using changes in base voltage and verify the
results with a multimeter.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board Power
supply, 15 Vdc (2 required)
 Multimeter

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this experiment. Measured
values will differ slightly from nominal due to normal circuit and instrument variations. Your
measurements in the following exercises will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise noted in
a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLY and

NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent

III. THEORY:

In a previous experiment, you learned that a transistor device is made up of two

semiconductor junctions. Figure 6-1 illustrates this principle as it applies to the NPN
transistor. The figure shows a basic three-element device having an emitter, a base, and a
collector.

Figure 6-1. Basic NPN transistor.

In normal operation, the emitter-base junction is forward biased, and the base-collector
junction is reverse biased. When the two conditions are met, current flows from the emitter
to the base, which, in turn, allows current to flow from the emitter to the collector. This
movement is shown in Figure 6-2.

Figure 6-2. Current flow in an NPN transistor.

ECE 301 88

Transistors are not ideal devices. They dissipate power in the form of heat. This
power is generated when current passes through the device and voltage is dropped by the
device. The combination of voltage and current produces power loss that can range from
fractions of a watt to hundreds of watts. In general, high power devices require heat sinks or
other forms of cooling, such as forced air.
Recall that a transistor is a current-amplifying device. As such, the device has a
property called gain. Gain allows a small current in the base material to be multiplied into a
much larger current through the collector material. This additional current is provided by the
circuit power source. A typical forward biased NPN transistor circuit is illustrated in Figure 6-
3.

Figure 6-3. Typical NPN circuit.

In Figure 6-3, the base-emitter diode junction is forward biased by the 5-volt battery.
Although the collector-base junction is reverse biased by the 10-volt battery, current (Ic) flows
from the battery, into and out of the transistor, then through the 10K load resistor. The collector
current is greater than the base current required due to the gain of the device. Note that the emitter
current is the sum of the base current plus the collector current.
The gain of the transistor determines how much base current must be supplied for a given
collector current. In Figure 6-4, the device has a gain of 100 and must draw (based on the load
resistor and collector supply) a current of about 10 mA (neglect the VCE drop of the device).
Therefore, the required base current is 0.1 mA (10 mA/100). Figure 6-4 shows the ability of a
forward biased transistor to multiply a small base current (0.1 mA) into a much larger collector
current (10 mA).

Figure 6-4. Transistor gain effect.

Up to this point, we have considered the transistor to be forward biased. Forward biasing allows
the device to act as a switch placed in its ON position. Should the transistor be reverse biased,
then it will act as a switch placed in its OFF, or opened, position. In this case, no collector
current will flow through the load. Therefore, a transistor not only acts as an amplifying device,
but it can also be used as a current (flow) control device.
Based on this discussion, three basic elements are to be considered when you use a transistor:
bias potentials, the required load current, and gain.
NEW TERMS AND WORDS
 cut-off point - the dc operating point of a reverse biased transistor (not conducting).
 forward biased - condition in which a voltage potential is applied in a direction so as
to allow a junction to conduct current.
ECE 301 89

 gain - a measure of the amplifying capabilities of a transistor.

 junctions - matting area of P type and N type semiconductor material.
 load line - a plot of collector current versus collector voltage used to determine the
best transisto.r operating point.
 quiescent point - the dc operating point of a transistor equal to about one-half of the
supply circuit voltage.
 reverse biased - condition in which a voltage potential is applied in a direction so as
to prevent a junction from conducting current.
 saturation - the point at which a transistor is passing 100 percent of collector current.
 semiconductor - a material that is neither an insulator nor a pure conductor.
 V CE - the drop measured between the collector and emitter of a transistor.
 V CE(sat) - the drop across a transistor measured at the saturation point of operation.
The emitter-base and base-collector junctions of a transistor are equivalent to
the PN junction of a diode. Voltage applied across a transistor junction can bias
the junction in either the forward or reverse direction.
The typical forward voltage drop of a silicon transistor junction is about 0.5 to
0.7 Vdc, depending on the amount of forward current. A high power diode or
transistor may have voltage drops in the 1 to 2.5 Vdc range. In comparison, the
forward drop of a germanium-type junction is about 0.15 Vdc to 0.3 Vdc.
Diodes may have reverse voltage breakdown capability that ranges from 50
Vdc up to 2000 Vdc. Transistor junctions can not tolerate reverse voltages greater
than approximately 3 Vdc to 5 Vdc. This limit applies to both silicon and
germanium types. If this limit is exceeded, the voltage will "punch" through the
junction barrier and destroy the device.
As with a diode, a transistor junction allows current to pass freely when it is
forward biased. This forward current can be measured and related to forward
voltage. In the reverse direction, no current should flow. However, a transistor is
not an ideal device, so a small leakage current passes through a junction that is
reverse biased. In general, this small current is in the low microampere to
nanoampere range. For the 2N2219A transistor, this current is about 0.01 f-tA (10
nanoamps).
This measurement is made with the collector of the transistor open. The
symbol VEBO means that the device is reverse biased (EB) and that the collector is
opened (0).
Usually, the amount of reverse voltage and the temperature at which the test is
performed are given in the manufacturer literature of the device.
IV. PROCEDURE:
1. Adjust the power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.
2. Locate the TRANSISTOR LOAD LINES AND GAIN circuit block, and connect the
circuit shown in Figure 6-5(a).
3. Adjust the R2 control for a measured voltage of -2.5 Vdc at the base of Q1 (with
respect to the emitter of Q1).
4. Is the emitter-base junction of Q1 forward or reverse biased?
_____________________________________________________________
_____________________________________________________________

5. Measure the voltage drop of R6 (VR6) and determine if base current is flowing. Is this
current large or small?
_____________________________________________________________
_____________________________________________________________
ECE 301 90

Figure 6-5. Transistor base-emitter test circuit.

6. Modify the circuit to look like Figure 6-5(b). Is the base-emitter junction of Q1 forward
or reverse biased?
_____________________________________________________________
_____________________________________________________________

7. Set R2 to its maximum CCW position. With the multimeter set to read dc volts, adjust
R2 for a reading of 0.5 Vdc at VA [refer to Figure 6-5(b)]. Measure VBE and VR6. Use
Ohm's law to calculate the base current. Record your results in Table 6-1 for each
listed value of VA.
Table 6-1. Forward biased junction characteristic.

VA VBE VR6 IB = VR6/R6

10 Vdc
8 Vdc
6 Vdc
5 Vdc
4 Vdc
2 Vdc
1 Vdc
0.5 Vdc

8. Use the values generated for Table 6-1 to plot a graph of the base current versus base
voltage characteristic of Q1. Use the graph of Figure 6-6.

Figure 6-6. Measured IBEO versus V BEO curve of Q1.

ECE 301 91

9. Examine your plotted data. Is there any similarity between your data of VBEO and a
forward biased diode?
_____________________________________________________________
_____________________________________________________________

10. Based on your graph, what is the approximate voltage at which the base-emitter
junction is completely forward biased?
_____________________________________________________________
_____________________________________________________________

11. Turn off the power sources. Remove all circuit board connections.

V. EVALUATION:
1. The base-emitter junction of an NPN transistor will conduct milliarnps of current if the
a. junction is reverse biased.
b. junction voltage is less than 0.1 Vdc.
c. junction is forward biased.
d. emitter is connected to the base.
2. When the base-emitter junction of a transistor is reverse biased, the amount of base
current will be
a. large.
b. zero, except for leakage current.
c. small.
d. dependent on the bias current.
3. For an N PN transistor, the base-emitter junction is forward biased when
a. the base is more negative than the emitter.
b. the emitter is more positive than the base.
c. base voltage is equal to emitter voltage.
d. base voltage is positive with respect to the emitter.
4. When a transistor is forward biased, the base-to-emitter voltage
a. is constant.
b. increases by small amounts as base current increases.
c. decreases by small amounts as base current increases.
d. is Zero.
5. The transistor base-emitter junction can withstand reverse voltages
a. exceeding 100 Vdc.
b. below 100 Vdc.
c. of several volts.
d. only with milliamps of base current.

VI. CONCLUSION:
ECE 301 92
D. COLLECTOR CURRENT VERSUS BASE BIAS

I. OBJECTIVE:
 To determine the effects of base bias (and therefore base current and gain) and collector
voltage using collector current and verify the results with a multimeter.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board Power
supply, 15 Vdc (2 required)
 Multimeter

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this experiment. Measured
values will differ slightly from nominal due to normal circuit and instrument variations. Your
measurements in the following exercises will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise noted in
a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLY and

NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent

III. THEORY:

A transistor used to control the flow of current through a load performs like a switch
placed in series with its load. When the transistor is forward biased, current flows through
the load. When the transistor is reverse biased, no current flows through the load. .
The circuit used in this experiment is the most popular transistor configuration. It is
called a common-emitter configuration because both the input and output signals are
referenced to the emitter, which. is common to both. Figure 6,7 shows a typical common-
emitter circuit.

Figure 6-7. Common-emitter circuit configuration.

Current gain in this circuit is obtained from the base and collector currents. Because a very
small change in base current produces a large change in collector current, the current gain
( or beta) is always greater than unity (one). A typical value is 50; however, some devices
can have gains of 200 or more. For this circuit, gain can be calculated from the following
formula:
Gain = lC / lB (collector current/base current).
Collector current also changes when the circuit supply voltage changes, though the effect is
much less than that produced by a change in base current. This important transistor concept
indicates that a small signal applied to the base can control a much larger collector current,
thus producing amplification.
ECE 301 93
As you know, transistors are forward biased across the emitter-base junction and reverse
biased across the base-collector junction. In Figure 6-7, two batteries are used to generate
the proper bias levels. The bias supply battery generates sufficient voltage to forward bias
the base-emitter junction. RB is used to drop the voltage difference between the base supply
voltage and VBE.
The circuit supply generates the proper bias for the base-collector junction. RL is selected to
provide the desired collector current.

IV. PROCEDURE:

1. Adjust the power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.

2. Locate the TRANSISTOR LOAD LINES AND GAIN circuit block, and connect the circuit
shown in Figure 6-8.

Figure 6-8. Transistor gain test circuit

NOTE: For the remainder of this procedure, select the RB
value (R3, R4, or R5) that provides the easiest collector
current adjustment. Select the desired resistor by using a
two-post connector.

3. Adjust the positive variable supply for 5 Vdc. Use a two-post connector to select a value
for RB.

4. Measure the voltage drop of R9 (VR9). Adjust R2 for a reading of 0.2 Vdc across R9.
Based on Ohm's law, what is the collector current (IC) of Q1 ?
_____________________________________________________________
_____________________________________________________________

5. Measure the voltage drop of R6 (VR6). The current through this resistor is equal to the
base current of the transistor. Based on the voltage drop, use Ohm's law to calculate
and record the base current (IB).
_____________________________________________________________
_____________________________________________________________

6. Adjust R2 for the collector currents specified in Table 6-2. Complete the BASE
CURRENT column.

NOTE: Your calculated base voltage will vary depending on the gain of
your device. The gain will range from 50 to 300. Your calculated base content
should fall within the lines plotted in Figure 6-9. The table and following results
are based on nominal values.
ECE 301 94

Figure 6-9. Max./ min IC versus IB plot.

7. Examine the results in Table 6-2. Does a small change in base current result in a large
change in collector current?
_____________________________________________________________
_____________________________________________________________

8. From Table 6-2, determine the base current change required to increase IC from 2 mA
to 10 mA. To do this, subtract the base current when IC is 12 mA from the base current
when IC is 10 mA. Record your results below.
_____________________________________________________________
_____________________________________________________________

9. What property of the transistor allowed a small base current change to control a
collector current change of 8 mA?
_____________________________________________________________
_____________________________________________________________

10. Based on a nominal transistor gain of 175, what base current is required if a 5 Ma
collector current is required? Does this current fall within the limits specified by Figure 6-
9?
_____________________________________________________________
_____________________________________________________________

11. Adjust R2 for a collector current of 2 mA. Increase the positive variable supply to 10
Vdc. Determine and record the new collector current.
NOTE: The collector current should change by
approximately 50 to 100 µA

____________________________________________________________
_____________________________________________________________

12. Based on your results, which change (base current or collector voltage) had the greater
effect on collector current?
____________________________________________________________
_____________________________________________________________

13. Turn off the power sources. Remove all circuit board connections.
ECE 301 95
V. EVALUATION:
1. In a transistor, collector current ,will flow through a load when the base-emitter junction
is
a. a zero potential.
b. forward biased.
c. reverse biased.
d. tied to the collector supply.

2. A small change in the base current of a transistor results in

a. a large change of collector current.
b. a small change of collector current.
c. no change in collector current.
d. a small change of supply voltage.

3. A doubled collector supply voltage of a transistor results in

a. a large change of collector current.
b. a small change of collector current.
c. no change in collector current.
d. a small change of supply voltage.

4. The current gain of Q1 used in this exercise (refer to Figure 6-1 0) can be represented
by
a. base current/collector current.
b. base voltage/collector voltage.
c. collector voltage/base current.
d. collector current/base current.

Figure 6-10. Transistor gain circuit.

5. Which of the following statements is true?

a. A small change in collector current is produced from a small change in base
current.
b. Base current can not flow unless the collector is connected to the circuit.
c. The base-collector junction of a transistor must be forward biased for operation in
the linear region.
d. The base-collector junction of a transistor must be reverse biased for operation in
the linear region.

VI. CONCLUSION:
ECE 301 96
E. TRANSISTOR DC CIRCUIT VOLTAGES

I. OBJECTIVE:
 To determine dc operating characteristics using an NPN transistor and verify the results
with a multimeter

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board Power
supply, 15 Vdc (2 required)
 Multimeter

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this experiment. Measured
values will differ slightly from nominal due to normal circuit and instrument variations. Your
measurements in the following exercises will be acceptable if your power voltages and
circuit measurements lie within the following ranges from nominal unless otherwise noted in
a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLY and

NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent

III. THEORY:

A transistor controls the flow of current through a circuit or load. It can either allow or
prevent current flow. Figure 6-11 illustrates this principle by comparing the transistor to a switch.
In Figure 6-11 (a), the switch is placed in its ON position to correspond to a forward biased
condition. As a result, current flows through load resistor R1, and the transistor allows current to
flow through R2. The transistor, unlike the switch, is dependent on base current and beta for
proper operation. In addition, the transistor is not an ideal conductor. These factors result in the
transistor having a voltage drop across the collector-to-emitter terminals. This drop varies
according to how hard the transistor is turned on.

Figure 6-11. Transistor current control.

In Figure 6-11 (b), the switch is placed in its OFF position to correspond to a reverse
biased condition. As a result, current can not flow through R 1, and the transistor does not allow
current to flow through R2. Because the circuit shown is a series circuit, all of the circuit voltage
ECE 301 97
is dropped across the open element. For this transistor, the voltage across the collector-to-
emitter terminals is equal to the circuit supply voltage.
Recall from Ohm's law that a voltage is produced if a current is made to flow through a
resistance. Figure 6-12 shows the equivalent series circuit of an NPN transistor.

Figure 6-12. Transistor collector-emitter series circuit.

Current flows in the circuit because the transistor is forward biased. This current
generates a voltage drop across RL and a voltage drop across the collector-to-emitter terminals
of the device. The voltage relationship around the circuit can be expressed by the following
formula:
Vs = V RL +V CE
The voltage across the transistor, then, is equal to the supply voltage (Vs) minus the
voltage drop of the collector resistor, as expressed by the following formula:
VCE=Vs-(IC x RL)
Because this is a series circuit, the collector current equals the current through resistor
RL. Once the current through and the voltage drop across the transistor are known, the power
dissipated by the transistor (PCE) can be calculated from the formula shown below:

P CE = V CE x IC
In a similar fashion, the voltage and base current relationships can be determined by
Ohm's law. The base-emitter series path is illustrated in Figure 6-13. Once the base current is
determined from the beta of the transistor, the circuit path can be determined from the formula:

Figure 6-13. Transistor base-emitter series circuit.

Notice that the base-emitter junction is equivalent to a diode. As a result, its voltage
drop is about 0.7 volts and barely changes with changes in base current. When the base is
reverse biased, very little current flows in the base circuit.

As stated in this discussion, Ohm's law can be applied to the common emitter circuit
to determine the circuit voltage and current distribution. Figure 6-14 shows the common-
emitter circuit and the application of Ohm's law.
ECE 301 98

Figure 6-14. Common Emitter Circuit and Ohm’s Law

Notice from the figure that VCE (the voltage drop from collector-to-emitter), depending on the
amount of current flowing through the collector, can vary from a very low voltage to the
supply level.
When the transistor is turned on and is conducting at its maximum, its voltage drop is low. At
this level. the voltage drop is referred to as V CE(sat) the saturation voltage of the transistor.
When the transistor is turned off and is not conducting, its VCE equals the collector supply
voltage (Vcc)

IV. PROCEDURE:
1. Adjust the power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.
2. Locate the TRANSISTOR LOAD LINES AND GAIN circuit block, and connect the
circuit shown in Figure 6-15.
3. Adjust the positive variable supply for 10 Vdc. Use a two-post connector to select R5
(base circuit RB).

Figure 6-15. DC voltages of a common-emitter circuit.

4. Adjust R2 to its maximum CCW position. Measure and record VCE of Q1. What does the
reading indicate about the conduction of Q1?
_____________________________________________________________
_____________________________________________________________
ECE 301 99
5. Move the two-post connector from its R5 position and select R3. Adjust R2 to its
maximum CW position. Measure and record the VCE of Q1. Does the reading indicate
that the collector current flow is maximum or minimum?
_____________________________________________________________
_____________________________________________________________

6. Insert R4 back into the circuit. Adjust R2 until Ic equals 4.5 mA. Measure and record VCE
of Q1. Does this value indicate that Q1 is at maximum conduction, partial conduction, or
minimum conduction?
_____________________________________________________________
_____________________________________________________________

7. Based on your results, the maximum power dissipated by Q1 occurred at what point of
conduction (maximum, partial, or minimum)?
_____________________________________________________________
_____________________________________________________________

8. Adjust R2 until VCE equals 5 Vdc. Measure the voltage drops of RS, R9, and VCE of Q1.
Do the voltage drops around the collector-emitter loop equal the voltage of the variable
positive voltage source? Refer to Figure 6-16 for proper multi meter placement.
_____________________________________________________________
_____________________________________________________________

Figure 6-16 Meter placement for common emitter circuit readings.

9. Measure and record the voltages around the base-emitter loop of the common-emitter
circuit. Again refer to Figure 6-16 for proper meter placement. What is the relationship
between the voltage drops of the base resistors and the base-emitter junction to VBB?
_____________________________________________________________
_____________________________________________________________

10. Verify that VCE equals 5 Vdc (adjust R2 if required). Calculate and record the voltage
drop of R8 and R9. Based on this value, what is the collector current of Ql?
_____________________________________________________________
_____________________________________________________________

11. Apply Ohm's law to R9 and verify your calculated collector current. (Ic = VR9/R9). Is this
value approximately equal to the value you obtained in step 10?
_____________________________________________________________
_____________________________________________________________
ECE 301 100
12. Based on your results, is the current that flows through R9 and R8 equal to the current
that flows through Q1?
_____________________________________________________________
_____________________________________________________________

13. Do not turn off the power sources. The F.A.C.E.T. setup will be used for two review
questions.

V. EVALUATION:

1. Locate the TRANSISTOR LOAD LINES AND GAIN circuit block on the
SEMICONDUCTOR DEVICES circuit board. Connect the circuit shown in Figure 6-17.
Place CM switch 19 in the ON position. Monitor VCE as you vary R2 from end to end.
Your efforts indicate that
a. Q1 is in the linear region.
b. Q1 is in cut-off.
c. Q1 can not be turned off.
d. the collector of Q1 is not connected.

Figure 9-17.
2. Using the same circuit as was used in question 1, adjust R2 to its maximum CCW
position. Q1 should be in its OFF stage. Monitor Vce. Your reading indicates that
a. Q1 is defective (collector-to-emitter has a low resistance short).
b. the circuit is operating properly.
c. Vcc is improperly adjusted.
d. the collector gain is too high.

Turn off CM switch 19 and the power sources. Refer to Figure 6-18 for the remaining
questions.

Figure 6-18. Common Emitter Circuit

3. In this circuit, VRl is equal to

a. VBB + VBE.
b. VBE.
c. VBB.
d. VBB – VBE.
ECE 301 101
4. If the circuit in Figure 6-18 is operating in the linear region. a voltage reading between
the base and collector junction will show that the junction is
a. forward biased.
b. reverse biased.
c. dropping zero volts.
d. equal to Vcc.

5. Which of the following equations is true?

a. VBB = VR1 + VBE
b. VR1 = VBB + VBE
c. Vcc = VR2 + VBE
d. Vcc = VR2 - VCE

VI. CONCLUSION:
ECE 301 102
F. TRANSISTOR LOAD LINES

I. OBJECTIVE:
 To be able to plot the load line of a 2N2219A transistor, determine its quiescent
operating point and verify the results with a multimeter.
II. APPARATUS AND MATERIALS:
 F.A.C.E.T. Base Unit
 SEMICONDUCTOR DEVICES Circuit Board Power
supply, 15 Vdc (2 required)
 Multimeter

MEASUREMENT TOLERANCES
Nominal values have been determined for all measurements in this experiment.
Measured values will differ slightly from nominal due to normal circuit and instrument
variations. Your measurements in the following exercises will be acceptable if your power
voltages and circuit measurements lie within the following ranges from nominal unless
otherwise noted in a procedure step:

External power source settings: +15 Vdc = ± 3 percent

-15 Vdc = ± 3 percent

POSITIVE SUPPLY and

NEGATIVE SUPPLY settings: Stated value ± 0.2 Vdc
Multimeter voltage and current measurements: ± 8 percent
Multimeter resistance measurements: ± 20 percent

III. THEORY:
A transistor is operated between two points of operation. The first point is defined by
VCEtsat), where the device is in full conduction. The second point is defined by VCE at the cut-
off point, where the device is not in conduction. When a line connects these points on a
graph, the graph represents a load line. As the name implies, a load line shows how a circuit
operates for different values of load resistors.

Figure 6-19(a) illustrates a typical load line and identifies the key points of circuit
operation. Recall that a transistor is not an ideal conductor; therefore, it will drop a small
voltage at saturation. In practice, this voltage is low enough to be excluded from a load line
plot. As a result, the VCE(sat) point is

Figure 6-19. Typical transistor load line

ECE 301 103
plotted at zero volts VCE. The point of transistor cut-off (no conduction) is plotted where VCE
equals the circuit supply voltage. In the figure, this point is plotted at the cut-off point of the VCE
line.
Figure 6-19(a) shows the active area over which the collector current may be varied. A
desirable operating point is one where maximum collector current control is provided on both
sides of the point. When this operating point called the quiescent point, is properly selected, the
transistor is able to control collector current for a wide variation of loads.
The quiescent point of operation is shown in Figure 6-19(b). Generally, this point is selected to
be at the midpoint of the circuit supply voltage (5 Vdc). The transistor is selected from the
expected load current range. In this example, the maximum circuit current is 10 mA, so the
selected transistor operates at this load current.

Figure 6-20 shows how the end points of a load line are determined. The maximum collector
current point is determined by Ohm's law:

Figure 6-20. End points of a transistor load line

Because the voltage drop of the transistor is small at saturation, it is neglected in this
calculation. The maximum VCE point is determined by the supply voltage. This voltage appears
across the transistor when it is not in conduction.
The use of a transistor load line for two different load resistors is illustrated in

Figure 6-21. Here the load resistors are 1 K and 5K. Notice that the operating point of the 5K
resistor has dropped.

Figure 6-21. Transistor Load line

ECE 301 104
In addition, the transistor can control a maximum collector current of 2 mA. For this
example, a 5K load resistor is not an ideal choice. The 1K resistor provides a much greater
collector current control range and represents a better choice.
Notice in Figure 6-21 that the plot relates current, voltage, and resistance. Recall that
Ohm's law relates the same quantities. One advantage of a load line is that the resistance
required to make the line can be determined by an Ohm's law calculation (voltage over
current). The formula for this calculation is:
RL = (V cc - V CE) / lc
Applying this formula to the midpoint of the load line in Figure 6-21, we can find the 1K
load line.
RL = (10- 5)/ 5 = 5/5
=1K
The plot indicates that the 1K value is constant anywhere along the line.
IV. PROCEDURE:
1. Adjust the power sources to +15 Vdc and -15 Vdc. Turn the power sources off. Insert
the SEMICONDUCTOR DEVICES circuit board into the base unit. Do not turn on the
power sources at this time.

2. Locate the TRANSISTOR LOAD LINES AND GAIN circuit block, and connect the circuit
shown in Figure 6-22.

Figure 6-22.Load line test circuit

3. Adjust the positive variable supply for 10 Vdc. Use two-post connectors to select R5 and
R8.

4. Adjust R2 to maximum CCW position. Measure and record VCE of Q1. What point on the
load line plot does this voltage reading represent?
_____________________________________________________________
_____________________________________________________________

5. Move the two-post connector from its R5 position and select R3. Adjust R2 to its
maximum CW position. Use VR9 to calculate Ic. Measure and record VCE of Q1. What
point on the load line plot does the voltage reading represent?
_____________________________________________________________
_____________________________________________________________

6. Take your readings from steps 4 and 5. and locate the points on the graph of Figure 6-
23. Connect both points on the graph with a straight line.

NOTE: Remember that RL = R9 + R7 or R9 + R8,

depending on which resistor (R7 or R8) is selected
with a two-post connector. Refer to Figure 6-22.

7. Based on the load line represented by Figure 6-23, what point on the plot should be
picked as the quiescent point of operation? Mark this point on your load line.
_____________________________________________________________
_____________________________________________________________
ECE 301 105

Figure 6-23. Load line graph.

8. Based on your load line graph. calculate the approximate collector resistive value
required to generate this load line [RL = (Vcc – VCE) /lc ). Use the Ic value that
corresponds to the quiescent point of operation. Record your answer below.
_____________________________________________________________
_____________________________________________________________

9. From the load line. determine the collector currents for VCE at 2.5 Vdc and at 7.5 Vdc.
Record the expected currents below.
_____________________________________________________________

_____________________________________________________________

10. Adjust R2 for a collector-to-emitter voltage of 2.5 Vdc. Determine the collector current
by using VR9. Does this current approximately equal the value predicted by your load
line graph?
_____________________________________________________________
_____________________________________________________________

11. Repeat step 10 with a VCE of 7.5 Vdc. Do your results match the predicted current
indicated by the load line graph?
_____________________________________________________________
_____________________________________________________________

12. Move the two-post connector from the R8 position to the R7 position. The collector load
resistor is now equal to 4800 ohms (R7 + R9). Using the same cut-off point (10 Vdc),
calculate the saturation current (IC SAT = VCC/RL). Record this value below, and plot this
point on the load line graph of Figure 6-23
_____________________________________________________________
_____________________________________________________________

13. Repeat steps 10 and 11 using the new load line. Do your results indicate that the load
line can be used to predict the collector current for a specific value of collector-to-emitter
voltage?
_____________________________________________________________
_____________________________________________________________

14. Compare the load lines of Figure 6-23. Which load resistor provides a better range of
collector current for the specified circuit supply voltage?
_____________________________________________________________
_____________________________________________________________

15. Do not turn off the power sources. The F.A.C.E.T. setup will be used for the review
questions.
ECE 301 106

V. EVALUATION:

NOTE: For the first three review questions, refer to

Figure 6-24. Select the R8 value (R3, R4, or R5) that
provides the easiest collector current adjustment. Select
the desired resistor by using a two post connector.

1. Locate the TRANSISTOR LOAD LINES AND GAIN circuit block on the
SEMICONDUCTOR DEVICES circuit board. Connect the circuit shown in Figure 6-24.
Place CM switch 20 in the ON position. Adjust the positive variable supply to 10 Vdc.
Adjust potentiometer R2 to determine the saturation and cut-off points for the circuit. If
necessary, measure only the R9 voltage drop between VA and the terminal next to the
Q1 collector. Based on your data. plot the circuit load line on Figure 6-25.

The load line of this circuit indicates that the saturation point will
a. Occur at 10 volts
b. occur at 9 mA.
c. occur at 4.3 mA.
d. not occur.

Figure 6-24. Load line test circuit.

Figure 6-25. Load line graph.

2. Based on the load line, a collector-emitter voltage of 3 Vdc will result in a collector
current of
a. 1.5 mA.
b. 3 mA.
c. 1 5 mA.
d. 30 mA.

3. If the quiescent point of this circuit is moved to where VCE equals 3 Vdc while Ic remains
the same, the circuit
a. will not operate.
b. will require a 300 ohms load resistor.
ECE 301 107
c. supply voltage must be 3 Vdc.
d. load resistor will have to be increased.

Turn off CM switch 20 and the power sources. Remove all circuit board connections.

4. In a practical circuit, the V CE(sat) of a transistor is not indicated on a load line graph
because
a. the voltage level is low.
b. the voltage level is high.
c. it is part of Vcc.
d. it is equal to zero volts.

5. A circuit load line can be used to

a. pick a quiescent operating point.
b. determine the beta range of a circuit.
c. calculate maximum operating voltage.
d. calculate circuit gain.

VI. CONCLUSION:
ECE 301 108
CEBU INSTITUTE OF TECHNOLOGY
Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 8
COMMON-BASE CIRCUIT
( SMALL SIGNAL AMPLIFIERS )

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. CIRCUIT LOCATION AND IDENTIFICATION

I. OBJECTIVE:
1. To be able to locate and identify the functional circuit blocks on the
TRANSISTOR AMPLIFIER CIRCUITS circuit board and observe the operation of
two basic amplifier circuits by using an oscilloscope.

II. APPARATUS AND MATERIALS

1. F.A.C.E.T. Base Unit

2. TRANSISTOR AMPLIFIER CIRCUITS Circuit Board Power
supply, 15 Vdc (2 required)
3. Multimeter
4. Oscilloscope, dual trace
5. Generator, sine wave

III. THEORY:

Most things that we think of as electronic-stereo systems, television receivers, and the
like-use transistor amplifier circuits.
The succeeding experiments describes the circuit blocks on the TRANSISTOR
AMPLIFIER CIRCUITS circuit board (Figure 1-1) and presents some background on
transistor amplifiers.
ECE 301 109
Transistor amplifiers are grouped into one of three basic circuit configurations
depending on which transistor element is common to both input and output signal
circuits (Figure 1-2).
Each circuit configuration has its own characteristics, and design engineers
use the configuration that best suits a particular application.
Multistage transistor amplifiers include more than one transistor. The output
of the first stage is connected (coupled) to the input of the second stage. The output
of the second stage is coupled to the input of the third stage, and so forth.
Three methods of coupling amplifier stages are included on the circuit board:
RC coupling, transformer coupling, and direct coupling.

Figure 1-2. Basic transistor amplifier circuit configurations.

NEW TERMS AND WORDS

 active component- a circuit component that controls gain or directs current fiow.
 Ambient - the environment surrounding a component or a device.
 Distortion -undesired changes to a signal waveform.
 gain - the amount by which an amplifier increases signal voltage, current, or power;
expressed as a ratio of the output to input value.
 multistage - an amplifier circuit that uses more than one active component (transistor).
 temperature drift- the tendency of a transistor bias point to change with changes in
temperature.

Amplifiers are circuits that increase the voltage, current, or power of a signal. An amplifier
requires an active component and a source of power. The active components on the circuit
board are transistors; the power is supplied by the external power sources.
Transistor amplifiers may be classified in many different ways, as indicated by Table 1-1.
The characteristics listed in the table are only approximations because boundaries between
classes are not clearly defined. Most amplifiers fall into more than one class. For example, an
audio frequency amplifier could also be a direct coupled (DC) amplifier.
ECE 301 110
Table 1-1. Transistor amplifier classes.

CLASSIFICATION EXAMPLES CHARACTERISTICS

BY COMMON COLLECTOR WILL BE EXAMINED
COMPONENT COMMON BASE LATER IN
ARRANGEMENT COMMON EMITTER THIS MANUAL
POWER OUTPUT GREATER
BY POWER AMPLIFIER THAN APPROXIMATELY
PURPOSE OR 50 mW
APPLICATION VOLTAGE GAIN
VOL TAGE AMPLIFIER GREATER THAN 1.0
DIRECT COUPLED FREQUENCIES FROM 0 Hz
(dc) TO VERY HIGH
(DC) AMPLIFIER
FREQUENCIES
BY
SIGNAL AUDIO FREQUENCY BANDWIDTH FROM 20 Hz
FREQUENCY (AF) AMPLIFIER TO ABOUT 20 kHz
RADIO FREQUENCY FREQUENCIES ABOVE
(RF) AMPLIFIER 20 kHz

The TRANSISTOR AMPLIFIER CIRCUITS circuit board has five circuit blocks. Two
types of amplifier circuits can be configured on the COMMON BASE/ EMITTER and RC
COUPLING/TRANSFORMER COUPLING circuit blocks. Two-post connectors are used to
configure the circuits.
The circuit board also has a mounting position for the GENERATOR BUFFER. Use of
the GENERATOR BUFFER is explained in Appendix E.
The circuit board includes a fixed ATTENUATOR. If you experience difficulty in adjusting
your signal generator for low amplitude signals, you may connect the signal generator to the
circuit block through the ATTENUATOR. The ATTENUATOR output signal is approximately
one-tenth of the input signal voltage. When you use the ATTENUATOR, measure the signal
level at the amplifier circuit input location described in the exercise; do not measure at the
output of the signal generator, the GENERATOR BUFFER, or the ATTENUATOR OUT
terminals.

The first circuit block on the trainer is the COMMON BASE/EMITTER circuit block.
The NPN transistor (Q1) within this circuit may be connected in either the common base or
the common emitter configuration. You will observe the operation of both configurations in
this exercise and determine that both circuit arrangements produce signal gain. In later
units, you will learn how to measure the characteristics of both circuits.
The second circuit block is the COMMON COLLECTOR. Potentiometer R4 is used
as the load resistor. You will study the common collector circuit, often called an emitter
follower, in a later unit.
The BIAS STABILIZATION circuit block includes a resistor, labeled HEATER, that
is physically close to the case of a transistor. A separate dc power supply is used to pass a
current through this resistor (HEATER). A positive variable Vdc power supply is used in the
BIAS STABILIZATION circuit. Potentiometer R3 is used in the voltage divider circuit. This
circuit block does not use a sine wave generator.
The heat dissipated by the HEATER warms the transistor to demonstrate the effect
of ambient temperature changes on transistor characteristics. In a later unit, you will study
some of the biasing methods used by designers to compensate for transistor temperature
drift.
The RC COUPLING/TRANSFORMER COUPLING circuit block includes components that
are used in studying a two-stage amplifier. The two NPN transistors (Q1 and Q2) can be
connected by either RC (resistor-capacitor) or transformer coupling between the stages.
You will observe the operation of a two-stage amplifier in Exercise 1-2
ECE 301 111
IV. PROCEDURE:
1. Review the Introduction to this manual for information about circuit board
insertion, power source adjustment, and circuit modification (CM) switch usage.

2. Examine the TRANSISTOR AMPLIFIER CIRCUITS circuit board. Which circuit

blocks can be configured as two different circuits?
________________________________________________________________

________________________________________________________________

3. Examine the TRANSISTOR AMPLIFIER CIRCUITS circuit board. Which circuit

blocks have a potentiometer?

________________________________________________________________

________________________________________________________________

4. Which circuit block is powered by a positive variable dc power supply?

________________________________________________________________

________________________________________________________________

5. Which circuit block has a PNP transistor?

________________________________________________________________

________________________________________________________________

6. Which circuit block does not have a connection for the sine wave generator?

________________________________________________________________

________________________________________________________________

7. On the COMMON BASE/EMITTER circuit block, connect the common base

amplifier circuit of Figure 1-3. While observing the signal on channel 1 of the
oscilloscope, adjust the sine wave generator for a 1 kHz, 50 mVpk-pk ac input
signal (V;) at the location shown in Figure 1-3.
NOTE: If you have trouble accurately setting this level with your signal
generator, connect the generator to the ATTENUATOR IN terminals.
Connect the ATTENUATOR OUT terminals to the GEN terminals of the
COMMON BASE EMITTER circuit block.

Figure 1-3. Connection diagram for a common base amplifier circuit.

8. Measure and record the dc power supply voltage (VA), with reference to
ground.
ECE 301 112
________________________________________________________________

9. What is the ac output signal (Vo)?

________________________________________________________________

10. Does the circuit produce voltage gain?

________________________________________________________________

11. What is the phase relationship between the input and output signals?

________________________________________________________________

12. On the COMMON BASE/EMITTER circuit block, connect the common emitter
amplifier circuit shown in Figure 1-4. While observing the signal on channel 1 of
the oscilloscope, adjust the sine wave generator for a 1 kHz, 100 mVpk_Pk ac
input signal (V;) at the location shown in Figure 1-4

Figure 1-4. Connection diagram for a common emitter amplifier circuit.

13. What is the ac output signal (Vo)?

________________________________________________________________

________________________________________________________________

14. Does the circuit produce voltage gain?

________________________________________________________________

15. What is the phase relationship between the input and output signals?
________________________________________________________________

________________________________________________________________

V. EVALUATION:
1. Transistor amplifiers may be configured in a common
a. base circuit.
b. emitter circuit.
c. collector circuit.
d. All of the above.

2. Transistors in a multistage amplifier may be connected by

a. RC coupling.
b. transformer coupling.
c. direct coupling.
d. All of the above.
ECE 301 113

3. When small ac input signals are required,

a. channel 1 on the oscilloscope should be used.
b. the ATTENUA TOR should be used.
c. the potentiometer should be adjusted carefully.
d. the variable dc power supply should be used.

4. The circuit block(s) used to configure two types of transistor amplifiers

a. is the COMMON COLLECTOR circuit block.
b. is the BIAS STABILIZATION circuit block.
c. are the COMMON BASE/EMITTER and RC COUPLING/TRANS-
FORMER COUPLING circuit blocks.
d. is the DIRECT COUPLING circuit block

5. The potentiometers on some of the circuit blocks are used to

a. change the value of the resistor.
b. adjust the dc voltage supply.
c. configure the amplifier circuit.
d. adjust the ac input signal.

VI. CONCLUSION:
ECE 301 114

B. COMMON BASE CIRCUIT DC OPERATION

I. OBJECTIVES:
 To be able to demonstrate the operation of the common base transistor amplifier circuit
by using calculated and measured conditions.

 To be able to determine the dc operating conditions of a common base (CB) transistor

circuit by using a typical CB circuit and verify the results with a multimeter and with
calculations.

II. APPARATUS AND MATERIALS:

 FAC.E.T. Base Unit

 TRANSISTOR AMPLIFIER CIRCUITS Circuit Board Power
Supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:

The base terminal is common to both the input and output signals in a common base
(CB) transistor circuit, shown in Figure 2-1.

The ac output signal of a CB circuit is in phase with the input signal.

For a PNP or an NPN transistor to function normally in any type of amplifier circuit, the
base-emitter junction is forward biased, and the base4collector junction is reverse biased.
ECE 301 115
The emitter current (IE) increases very rapidly after a base-emitter voltage (VBE) of
about 0.6 Vdc (Figure 2-2).

A transistor circuit operates between the saturation and cut-off points on its load line, as
shown in Figure 2-3.

Proper biasing of a CE transistor circuit can be provided by a connection between the base
terminal and a voltage divider circuit across a single dc power supply (Figure 2-4).

The CB circuit has a current gain less than 1.0 and a high voltage gain. The input
impedance is low, but the output impedance is high.

NEW TERMS AND WORDS:

 active region - the region on the transistor load line between the saturation point and
the cut-off point.
 alpha ,  - the symbol used for the ratio of the dc collector current to the dc emitter
current.
ECE 301 116
 cut-off point - the point on the load line where the collector current is essentially zero.
 Q-point (quiescent point) - the dc steady state operating point set by the dc bias
conditions.
 saturation point - the point on the load line where the collector current is maximum.

Figures 2-5(a) and (b) show the dc operation schematic of the common base (CB) amplifier
circuit on the TRANSISTOR AMPLIFIER CIRCUITS circuit board. Both schematics are identical
circuits. Figure 2-5(b) is rearranged to match the schematic shown on the circuit board. The
base terminal is common to the input and output signals and is connected to ground by
capacitor C2.

The dc power supply voltage (VA) is typically 15.0 Vdc. A voltage divider circuit (R1
and R2) across the dc power supply provides a fixed dc base voltage necessary to forward
bias the base-emitter junction. For ac signals, capacitor C2 shorts the base to ground. You
can calculate the base voltage (VB) from the following voltage divider equation.

The base-emitter voltage difference (VB E) of a silicon NPN transistor is about 0.6 Vdc (0.5 to
0.7 Vdc). Consequently, the emitter voltage (VE) is about 0.6 Vdc less than the base voltage
when the transistor is operating normally.
VE = VB - 0.6
From Ohm's law, you can calculate the emitter current (IE) of the emitter
circuit in Figure 2-5, where R5 is the emitter resistor

IE = VE/R5
The collector current is the difference between the emitter and base currents.

Ic= IE - IB
The collector current nearly equals the emitter current because the base
current is much smaller than the emitter current.
ECE 301 117
The ratio of the dc collector and emitter currents is the dc forward-current transfer ratio.
The symbol for alpha (a) represents this ratio.
a = IC/IE

Alpha (a) is always less than 1.0 but usually greater than 0.98.
A transistor circuit is usually designed for a dc collector voltage (Ve) about halfway
between the power supply voltage (VA) and the emitter voltage. To reverse bias the collector-
base junction of an NPN transistor, the collector voltage is more positive than the base voltage.
From Ohm's law, you can calculate the collector current (Ie) of the collector circuit in
Figure 2-5, where R4 is the collector resistor. It is essentially equal to the emitter current (IE).

Figure 2-6 shows the dc load line drawn on the collector current characteristic curves of
the circuit shown in Figure 2-5. The dc operating point, or Q-point (quiescent point), of the
transistor is on the dc load line at the intersection of iile operating collector current (Ie) on the Y-
axis and the collector-base voltage (VeB) on the X-axis. The Q-point is determined by the dc
bias conditions (currents and voltages) of the transistor.
The cut-off point, on the X-axis, is where the collector and emitter currents are
essentially zero; the base-emitter junction comes out of forward bias. Because the collector
current (Ie) is essentially zero, the collector voltage is considered to be equal to the dc supply
voltage (Ve = VA). At the cut-off point, the collector-base voltage equals the difference between
the dc supply voltage and the base voltage [VeB(cutoff) = VA - VB]. The base voltage (VB) does
not change at the cut-off point because of the voltage divider circuit (R1 and R2).

The saturation point on the Y-axis, is where the base-collector junction

comes out of reverse bias. At the saturation point, the collector-base voltage (VCB) is
considered to be zero on the plotted load line, and the collector current [ IC(sat)] is
maximum [IC(sat)= (VA - VB/R4]. The saturation point of the CB circuit is located by a
straight line drawn from the cut-off point, through the Q-point, to the Y-axis. The line
connecting these points is the load line.
The area between the saturation point and the cut-off point on the load line is the active
region of the transistor circuit.
ECE 301 118
IV. PROCEDURE:

1. Locate the COMMON BASE/EMITTER circuit block on the TRANSISTOR

AMPLIFIER CIRCUITS circuit board. Connect the circuit shown in Figure 2-7.

2. Measure and record the supply voltage (VA) with reference to ground.

_______________________________________________________________

_______________________________________________________________

3. Calculate and record the base voltage (VB) for 01, at the junction of resistors R1
and R2, with the voltage divider equation below.
VB = VA X [R2/(R1 + R2)]

_______________________________________________________________

_______________________________________________________________

4. Measure and record the base voltage (VB) with reference to ground.

_______________________________________________________________

_______________________________________________________________

5. Measure and record the base-emitter voltage (VBE).

_______________________________________________________________

_______________________________________________________________

6. Is the base-emitter junction forward biased?

_______________________________________________________________

_______________________________________________________________

7. What is the measured collector-base voltage (VCB).

_______________________________________________________________

_______________________________________________________________

8. Is the collector-base junction reverse biased?

_______________________________________________________________

_______________________________________________________________

9. Is the NPN transistor Q1 in the CB amplifier circuit biased to operate in the active
region?
_______________________________________________________________
ECE 301 119
10. What is the emitter terminal voltage (VE) with reference to ground?

_______________________________________________________________

_______________________________________________________________

11. Calculate and record the emitter dc current (Id by applying Ohm's law for emitter
circuits (IE = VE/R5).
_______________________________________________________________

_______________________________________________________________

12. What is the collector terminal voltage (Vd with reference to ground?
_______________________________________________________________

_______________________________________________________________

13. What is the difference between the dc supply voltage and the collector voltage
V A - V C?
_______________________________________________________________

_______________________________________________________________

14. Calculate and record the collector dc current (Id by applying Ohm's law for
collector circuits [Ic = (VA - Vc/ R4].

_______________________________________________________________

_______________________________________________________________

15. Can the emitter and collector dc currents be considered essentially equal?

_______________________________________________________________

_______________________________________________________________

16. The Q-point of the transistor is on the dc load line at the intersection of the
operating collector current, Ic and the collector-to-base voltage (VCB). Using the Ic
value from step 14 and the VCB value from step 7, place the Q-point on Figure 2-8.

17. The cut-off point is where VCB(cutoff) = VA - VB and where Ic = 0 mA. Using the
values of VA from step 2 and VB from step 14, determine and record the cut-off
point VCB(cutoff) .

_______________________________________________________________

_______________________________________________________________
ECE 301 120
18. On Figure 2-8, place the cut-off point at the intersection of V CB(cutoff) and Ic at 0
mA.

19. The dc load line goes through the Q-point and the cut-off point and intersects the
Y-axis (V CB = 0 Vdc) at the saturation point [Ic(sat)]. On Figure 2-8, draw a line
from the cut-off point, through the Q-point, to the Y-axis. What is Ic(sat)?
_______________________________________________________________
_______________________________________________________________
20. Set CM switch 9 in the ON position to change the value of R2 from 10 K to 3.3K.
Measure and record in Table 2-1 the dc voltages at the collector, base, and
emitter of Q1, with reference to ground.

21. With R2 = 3.3 k-ohms, does transistor Q1 still operate in the active region?

_______________________________________________________________

_______________________________________________________________

22. At what point is the transistor operating?

_______________________________________________________________

_______________________________________________________________

23. Your answer to step 22 is based on what relationship between VB and VE?
_______________________________________________________________

_______________________________________________________________

V. EVALUATION:
NOTE: To answer review questions 1 and 2. connect the
CD amplifier circuit shown in Figure 2-7 to obtain the circuit
conditions at the end of the procedure.

1. Set CM switch 7 in the ON position to change the value of R1 from 120K to 10K.
Measure and record in Table 2-2 the dc voltages at the collector, base, and
emitter of Q1, with reference to ground.

With CM switch 7 turned on, the transistor is operating

a. at the saturation point.
b. in the active region.
c. at the cut-off point.
d. at an optimum Q-point.

2. Set CM switch 7 to the OFF position. Set CM switch 8 in the ON position to

change the value of R4 from 15K to 2.7K. Measure and record the dc voltages in
Table 2-3 with reference to ground.
Table 2-3.
ECE 301 121
With CM switch 8 turned on, the transistor is operating
a. at the saturation point.
b. in the active region.
c. at the cut-off point.
d. at an optimum collector voltage (Vc)

3. The voltage at the base of an NPN transistor operating in the active region is
a. 0.6 volts more positive than the collector voltage.
b. more than 10 Vdc less than the supply voltage.
c. 0.6 volts more positive than the emitter voltage.
d. 0.6 volts less positive than the emitter voltage.

4. At the cut-off point, the collector-base voltage (VCB) is about equal to

a. VA-VB
b. 0 Vdc.
c. VBE.
d. 0.6 Vdc.

5. In a CB transistor circuit, the maximum collector current occurs at

a. The Q point
b. The saturation point
c. The cut-off point
d. A point midway between the saturation and cut-off points

VI. CONCLUSION:
ECE 301 122
C. COMMON BASE CIRCUIT AC OPERATION

I. OBJECTIVE:
 To be able to determine ac operating characteristics of a common base (CB) amplifier by
using a typical CB circuit and verify the results with a multimeter and an oscilloscope.

II. APPARATUS AND MATERIALS:

 FAC.E.T. Base Unit
 TRANSISTOR AMPLIFIER CIRCUITS Circuit Board
Power Supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:

Figure 2-9 shows the ac operation schematic of the CB amplifier circuit on the
TRANSISTOR AMPLIFIER CIRCUITS circuit board. A sine wave generator (Vgen) provides the
ac input signal (V;). For ac signals, the base is shorted to ground by capacitor C2. The ac output
signal (Va) is taken between capacitor C3 at the collector terminal and ground.

Figure 2-9. CB amplifier circuit for ac operation.

The input impedance atthe emitter of the CB transistor circuit is very low(10 to 1000).
Figure 2-10 shows that the input impedance of the CB circuit in Figure 2-9 is equivalent to the
parallel resistance of the dynamic emitterbase junction resistance (re' at about 50 ohms) and
emitter resistor R5 (1 K) in series with R3 (1000). The output impedance is high because it is
equal to the resistance of collector resistor R4 (15 k-ohms). The dc power supply grounds R4
for ac signals.
Because of the low input impedance, CB circuits load down the input signal. However,
the high ratio of output to input impedances makes the CB circuit desirable for high gain
applications.
Figure 2-11 shows that the CB circuit ac output signal peak-to-peak voltage is
considerably greater than (indicating high voltage gain) and in phase with the input signal. As
the ac input signal increases, the current from the emitter terminal decreases, and, in turn, the
collector current decreases. With an ac input signal, the emitter terminal current equals the
emitter resistor current minus or plus the ac signal current.
ECE 301 123

The ac output signal has a considerably larger peak-to-peak voltage than and is in
phase with the input signal. The reason is that the collector load impedance (output) is about
100 times the emitter input impedance and that the collector and emitter currents are in
phase, essentially equal, and 180 degrees out of phase with the input signal voltage.
The voltage gain (Av) of a CB transistor circuit is the ratio of the ac output voltage (Va)
to the input voltage (Vi):
Av = Vo/Vi
The voltage gain is also equal to the ratio of the load and input impedances.

IV. PROCEDURE:
1. Locate the COMMON BASE/EMITTER circuit block on the TRANSISTOR
AMPLIFIER CIRCUITS circuit board. Connect the circuit shown in Figure 2-12.

Figure. 2-12. Connection diagram.

2. Measure and record the supply voltage (VA) with reference to ground?
ECE 301 124

_______________________________________________________________

_______________________________________________________________

3. Measure and record the dc voltages in Table 2-4, with reference to ground. Is the
NPN transistor Q1 properly biased for ac operation?

_______________________________________________________________

_______________________________________________________________

4. While observing the signal on channel 1 of the oscilloscope, adjust the sine wave
generator for a 1 kHz, 50 mVpk_Pk ac input signal (Vi = Vgen).

5. Connect the channel2 probe of the oscilloscope to the the ac output of Q1 (at the
collector terminal). What is the peak-to-peak voltage of the ac output signal (Va)?
_______________________________________________________________

_______________________________________________________________

6. Is there any distortion or clipping of the sine wave signal between the ac input and
output?
_______________________________________________________________

_______________________________________________________________

7. What is the phase relationship between the output and input signals?
_______________________________________________________________

_______________________________________________________________

8. Calculate and record the voltage gain (Av = V/V;).

NOTE: When calculating voltage gains in

this procedure, you can use peak-to-peak
voltage measurements instead of rms.
_______________________________________________________________

_______________________________________________________________

9. Connect resistor R6 to C3 at the collector terminal. The collector terminal output

impedance is now the parallel resistance of R6 and the original collector output
impedance. What is the new peak-to-peak voltage (Va) of the output signal?
_______________________________________________________________

_______________________________________________________________

NOTE: When the output voltage is decreased by 50

percent, the original output impedance equals the
resistance of R6, which was connected in parallel with R4.

10. Based on the decrease in the output voltage, what was the original output
impedance?
_______________________________________________________________

11. If necessary, readjust the ac signal at the output of the signal generator (Vgen) for 50
mVpkopk. Remove the two-post connector between C1 and R3 to disconnect the
ECE 301 125
generator signal from the CB transistor input. Does Vgen increase or does it
decrease?
_______________________________________________________________

_______________________________________________________________

12. Why does Vgen change when the signal generator is disconnected from the CB
transistor input?
_______________________________________________________________

_______________________________________________________________

13. Why is the input signal loaded down when the generator is connected to the CB
transistor input?
_______________________________________________________________

_______________________________________________________________

14. Connect C1 to R3 with the two-post connector. If necessary, readjust Vgen for 50
mVpkopk. Set CM switch 7 in the ON position to change the value of R 1 from 120K
to 10K. Observe the output signal. Did the output signal decrease or did it increase?

_______________________________________________________________

_______________________________________________________________

15. Measure and record the dc voltages in Table 2-5, with reference to ground. Is the CB
amplifier operating in the active region?
_______________________________________________________________

_______________________________________________________________

16. In what region is the CB amplifier operating?

_______________________________________________________________

_______________________________________________________________

17. Your answer to step 16 is based on what relationship between Vc and VB?
_______________________________________________________________

_______________________________________________________________

V. EVALUATION

NOTE: To answer review questions 1 and 2, connect the CB amplifier

circuit shown in Figure 2-12. Connect R6 to C3, and set the sine wave
generator for an ac input signal [Vgen] of 50 m Vpk-pk' This setup
describes the circuit conditions at the end of the procedure.

1. Set CM switch 9 in the ON position to change the value of R2 from 1 OK to 3.3K.

The input signal should be 50 mVpk_Pk' Observe the output signal. The ac output
signal is greatly reduced because the
a. transistor is operating in the saturation region.
b. transistor is operating in the cut-off region.
c. base and emitter terminals are shorted.
d. base current is too high.
ECE 301 126
2. Place CM switch 9 in the OFF position and CM switch 8 in the ON position to change
the value of collector resistor R4 to 2.7 kQ. The output signal is reduced because the
a. input impedance increased.
b. load impedance increased.
c. base voltage changed.
d. load impedance decreased.

3. The input impedance of a CB transistor circuit is

a. very low.
b. equal to the parallel resistance of the emitter and collector resistors.
c. very high.
d. equal to the emitter resistor.

4. The ac output signal of a CB transistor circuit is

a. out of phase with the signal at the collector.
b. in phase with the signal at the emitter.
c. in phase with the signal at the base.
d. smaller than the signal at the emitter.

5. The collector-base voltage (VCB) at the cut-off point is considered to be equal to

a. the base-emitter voltage.
b. the collector-emitter voltage.
c. 0 Vdc.
d. the dc supply voltage minus the base voltage (VA - VB).

VI. CONCLUSION
ECE 301 127
CEBU INSTITUTE OF TECHNOLOGY
Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 9
COMMON EMITTER CIRCUIT
(SMALL SIGNAL AMPLIFIERS)

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. COMMON EMITTER CIRCUIT DC OPERATION

I. OBJECTIVE:
 To be able to demonstrate the operation of the common emitter transistor amplifier
circuit by using calculated and measured circuit conditions.
 To be able to determine the dc operating conditions of a common emitter (CE)
transistor circuit by using a typical CE circuit. You will verify your results with a
multimeter and with calculations.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit TRANSISTOR AMPLIFIER CIRCUITS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:
The emitter terminal is common to both the input and output signals of the common
emitter (CE) transistor circuit, as shown in Figure 3-1.
ECE 301 128
The ac output signal of a CE circuit is 180 out of phase with the input signal. After a
base-emitter voltage (VBE) of about 0.6 Vdc, the base current (IB) increases very rapidly (Figure
3-2).

The transistor circuit ac and dc load lines intersect at the Q-point on the collector current
characteristic curves (Figure 3-3).

A CE transistor voltage divider circuit uses a single dc power supply to provide a

constant base terminal voltage (Figure 3-4).

Figure 3-4. Voltage divider circuit (R1 and R2) for transistor base bias voltage.

The CE circuit has high current, voltage, and power gains. The input and output
impedances are high.
ECE 301 129

IV. PROCEDURE:

I.

V. EVALUATION:
VI. CONCLUSION:
ECE 301 130
ECE 301 131

Ideally, the Q-point of a properly designed transistor circuit should be close to the
midpoint of the dc load line to give an appreciable ac signal operating range.

IV. PROCEDURE:
1. Locate the COMMON BASE/EMITTER circuit block on the TRANSISTOR
AMPLIFIER CIRCUITS circuit board. Connect the circuit shown in Figure 3-7.

Figure 3-7. Connection diagram.

2. Measure and record the supply voltage (VA) with reference to ground.
_________________________________________________________

_________________________________________________________

3. Calculate and record the base voltage (VB) of Q1 (VB is at the junction of resistors
R1 and R2). Use the voltage divider equation below.

4. Measure and record the dc voltages in Table 3-1, with reference to ground

_________________________________________________________

_________________________________________________________

Table 3-1

5. Do the measurements taken in step 4 indicate that the base-emitter junction is

forward biased?

_________________________________________________________

_________________________________________________________

6. Do the measurements taken in step 4 indicate that the base collector junction is
reverse biased?

_________________________________________________________

_________________________________________________________
ECE 301 132
7. Would you conclude that NPN transistor Q1 is biased correctly?

_________________________________________________________

_________________________________________________________

8. Is the transistor operating in its active region close to its optimum operating point?

_________________________________________________________

_________________________________________________________

9. Calculate and record the emitter dc current (IE = VE/R5).

_________________________________________________________

_________________________________________________________

10. Calculate and record the collector dc current [Ic = {VA – VC}/R4].

_________________________________________________________

_________________________________________________________

11. Are the emitter and collector dc currents essentially equal?

_________________________________________________________

_________________________________________________________

12. The operating point, or Q-point, is determined by the dc bias conditions of the
transistor. Using the voltages measured in step 4, what is VCE?

_________________________________________________________

_________________________________________________________

13. On Figure 3-8, place the a-point at the intersection of Ic on the Y-axis and VCE on the
X-axis. Use the values calculated in steps 10 and 12.

Figure 3-8. DC load line.

14. The cut-off point is where V CE(cutoff) = VA (dc supply voltage) and Ic = 0 mA. What is
V CE(cut off)?
_________________________________________________________

15. Place the cut off point in Figure 3-8.

ECE 301 133
16. The dc load line goes through the Q-point and the cut-off point and intersects the
Y=axis ; (Vce=0Vdc) , at the saturation point (Icsat). On Figure 3-8, draw a line from
the cut off point, through the Q-point to the Y-axis. What is Icsat?

Note: This answer has a tolerance of ± 30%.

_________________________________________________________

_________________________________________________________

17. Would you conclude from the location of the Q-point in Figure 3-8 that the transistor
is properly biased?

_________________________________________________________

_________________________________________________________

18. Set CM switch 7 in the ON position to change the value of R1 from 120K to 10 K.
Measure and record the de voltages in Table 3-2, with reference to ground.

Table 3-2

19. What is the new collector current , Ic?

_________________________________________________________

_________________________________________________________

20. What is the new emitter current (IE)?

_________________________________________________________

_________________________________________________________

21. Did Ic and Ie increase?

_________________________________________________________

_________________________________________________________

22. What caused Ic to increase?

_________________________________________________________

_________________________________________________________

23. Does changing R1 to 10K cause transistor Q1 to operate at the saturation point?
_________________________________________________________

_________________________________________________________

24. Your answer to step 23 is based on what relationship between two measured
voltages?

_________________________________________________________

_________________________________________________________
ECE 301 134
V. EVALUATION:

NOTE: To answer review questions 1 and 2, connect

the CE amplifier circuit shown in Figure 3-7 to obtain
the circuit conditions at the end of the procedure.

1. Set CM switch 8 in the ON position to change the value of R4 from 15K to 2.7K.
Measure and record the dc voltages in Table 3-3, with reference to ground. The
transistor is operating
a. at the saturation point.
b. in the active region.
c. at the cut-off point (zero currents).
d. at an optimum Q-point.

Table 3-3

2. Set CM switch 9 in the ON position to change the value of R2 from 10K to 3.3K.
Measure and record the dc voltages in Table 3-4, with reference to ground. The
transistor is operating
a. at the saturation point.
b. in the active region.
c. at the cut-off point (zero currents).
d. at an optimum Q point.
Table 3-4

3. The voltage at the base of an NPN transistor operating in the active region is
a. 0.6 volts more positive than the collector voltage.
b. more than 10 Vdc less than the supply voltage.
c. 0.6 volts more positive than the emitter voltage.
d. 0.6 volts less positive than the emitter voltage

4. The Q-point of a properly biased transistor amplifier should be located

a. close to the saturation point.
b. close to the cut-off point.
c. about on the center of the load line.
d. about 3 Vdc from the cut-off point.

5. In the cut-off region, a transistor is

a. turned off with only emitter current flowing.
b. turned off with only collector current flowing.
c. operating with VCE equal to one half of the supply voltage.
d. turned off with essentially no currents flowing.

VI. CONCLUSION:
ECE 301 135

B. COMMON EMITTER CIRCUIT AC OPERATION

I. OBJECTIVE:

 To be able to determine the ac operating characteristics of a common emitter (CE)

amplifier by using a typical CE transistor circuit and verify the results with a
multimeter and an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit TRANSISTOR AMPLIFIER CIRCUITS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:

Figure 3-9 shows the ac operation schematic of the CE amplifier circuit on the
TRANSISTOR AMPLIFIER CIRCUITS circuit board. A sine wave generator connected between
the transistor base and ground produces the ac input signal.

Figure 3-9. CE amplifier circuit for ac operation.

Because the dc power supply grounds the collector resistor (R4) when ac signals are
applied, the ac load is the parallel resistance of R4 and R6. Figure 3-10 shows the CE
amplifier circuit as it appears to ac input and output signals.

Figure 3-10. CE amplifier circuit as it appears to ac input and output signals.

ECE 301 136

Figure 3-11 shows the voltage and phase relationships of the ac input and output signals
of the CE circuit. The ac output peak-to-peak voltage is greater than (indicating voltage gain)
and 180 degrees out of phase with the input signal. As the base voltage increases, the base
current increases. As a result, the collector current and emitter current increase, as shown at
the lower right side of Figure 3-11. The curve for the ac emitter terminal voltage shows that this
voltage is in phase with the base input signal.

Figure 3-11 . Phase and voltage relationships of the ac input and output signals for the CE circuit.

The ac output signal at the collector has a larger peak-to-peak voltage than and is 180
degrees out of phase with the input signal. The reason is that the collector load resistance (rl) is
7.5 times the resistance of emitter resistor R5 (7.5K to 1K) and that the collector and emitter
currents are essentially equal and in phase.
The voltage gain (Av) of CE transistor circuits is the ratio of the ac output voltage (Vo) to
the ac input voltage (Vi):
Av = -VO /Vj
The minus sign indicates that the output voltage is 180 degrees out of phase with the
input. In a CE circuit where an emitter resistor is not bypassed by a capacitor, the voltage gain
also equals the ratio of the collector load (rl) to the emitter resistor (R5):

Av = -rl / R5
Figure 3-12 shows the ac and dc load lines drawn on the collector current characteristic
curves of the CE circuit in Figure 3-9. The ac and dc load lines have the same Q-point.
The following relationship for the ac collector saturation current [Ic(sat)] is obtained from
the sum of the Q-point conditions (lc and VCE) and the ac voltage drops in the collector and
emitter circuits:

Figure 3-12. AC and DC load lines.

ECE 301 137

By connecting the a-point with the Ic(sat) point and drawing a line to the X-axis, you
obtain the ac cut-off voltage [VCE (cut off)]. The line connecting these points is the ac load
line.
When the ac input signal is large enough to make the peak output voltage exceed the
maximum allowed by the cut-off point, the peak of the output signal is clipped or cut off
(Figure 3-13). This clipping occurs because the collector-to-emitter voltage difference (Vce)
at the peak output voltage exceeds the VCE (cut off) point. Also, the valley of the output signal
may be clipped if the saturation point is reached [Vce{sat)].

Figure 3-13. Cut-off and saturation points of an ac signal.

Figure 3-13 shows that the optimum Q-point is at the center of the ac load line. The maximum
allowable output signal is obtained when the a-point is at the center of the ac load line. The
saturation and cut-off points are equal distances from the optimum Q-point.

IV. PROCEDURE:
1. Locate the COMMON BASE/EMITTER circuit block on the TRANSISTOR
AMPLIFIER CIRCUITS circuit board. Connect the circuit shown in Figure 3-14.

Figure 3-14 Connection diagram

2. Measure and record the supply voltage (VA) with reference to ground.
_____________________________________________________________________

_____________________________________________________________________

3. Measure and record the dc voltages in Table 3-5, with reference to ground. Is the
NPN transistor Q1 properly biased for ac operation?
_____________________________________________________________________
ECE 301 138

TABLE 3-5

4. While observing the signal on channel 1 of the oscilloscope, adjust the sine wave
generator for a 1 kHz, 300 mVpk-pk ac input signal (Vi) at the base of transistor Q1.

5. Connect the channel 2 probe of the oscilloscope to the the ac output of Q1 (at the
collector terminal). What is the peak-to-peak voltage of the ac output signal (Vo)?
_____________________________________________________________________

_____________________________________________________________________

6. Is there any distortion or clipping of the sine wave signal between the ac input and
output?

_____________________________________________________________________

_____________________________________________________________________

7. What is the phase relationship between the output and input signals?

_____________________________________________________________________

_____________________________________________________________________

8. Calculate and record the voltage gain [Av = -Vo/Vi]?

NOTE: When calculating voltage gains in this procedure, you can use peak-to-peak
voltage measurements instead of rms.

_____________________________________________________________________

_____________________________________________________________________

9. Divide the load resistance by the emitter resistance to calculate then record the
approximate voltage gain (Av =-r i /R5). Is this Av value approximately equal to the
value measured from the input and output voltages in step 8?

_____________________________________________________________________

_____________________________________________________________________

10. Connect the channel 2 probe of the oscilloscope to the emitter terminal. What is the
peak-to-peak voltage of the ac signal at the emitter terminal?

_____________________________________________________________________

_____________________________________________________________________

11. What is the magnitude and phase relationship between the ac input signal at the
base terminal and the ac signal at the emitter terminal?
_____________________________________________________________________

_____________________________________________________________________

12. The Q-point on the load line is at the intersection of Ic and VCE. From the voltage
ECE 301 139

measurements taken in step 3, calculate and record Ic and VCE [Ic = (VA – Vc] / R4,
and VCE = VC - VE).
_____________________________________________________________________

_____________________________________________________________________

13. On Figure 3-15, place the Q-point at the intersection of Ic on the Y-axis and VCE on
the X-axis.

Figure 3-15. Load lines.

14. Calculate and record the ac collector saturation current [1c(satJ from the following
equation:

_____________________________________________________________________

_____________________________________________________________________

15. On the Y-axis in Figure 3-15, place a point for the lc(sat) ftalue you calculated (Vce =
0). Connect the a-point with the lc(satl point and extend the line to the X-axis. The ac
cut-off voltage [VCE (cutoffJ is the point where the line intersects the X-axis. What is the
value of V CE(cutoff)?

_____________________________________________________________________

_____________________________________________________________________

16. What is the name of the line connecting lc(sat) and VCE [cut off]?

_____________________________________________________________________

_____________________________________________________________________

17. Connect the channel 1 oscilloscope probe to the output at the collector terminal.
Connect the channel 2 probe to the input at the base terminal. Increase the ac input
signal until the peak of the ac output signal starts to become clipped. What is the
value of Vo when it starts to become clipped?

_____________________________________________________________________

_____________________________________________________________________
18. What point on the ac load line was reached in step 17?
_____________________________________________________________________
ECE 301 140

_____________________________________________________________________

19. Slowly increase the ac input signal until the valley of the output signal becomes
clipped. What is this point on the ac load line?

_____________________________________________________________________

_____________________________________________________________________

20. Set the ac input signal back to 300 mVpk-pk

21. The value of R4 changes from 15K to 2.7K when CM switch 8 is set to the ON
position. This modification changes ri to 2.28K (2.7K in parallel with 15K). With an
input signal of 300 mVpk-pk . What is the calculated peak-to-peak value of Vo when
the ratio of ri /R5 is 2.28/1 ?
_____________________________________________________________________

_____________________________________________________________________

22. Set CM switch 8 to ON the position. Using the oscilloscope, measure and record Vo.

_____________________________________________________________________

_____________________________________________________________________

V. EVALUATION:

NOTE: To answer review questions 1 and 2, connect the CE

amplifier circuit shown in Figure 3-14, and set the sinewave
generator for an input signal of 300 mVpk-pk to obtain the circuit
conditions at the end of the procedure.

1. Place CM switch 9 in the ON position to change the value of R2 from 10 kto 3.3
k. Observe the output signal. The output signal is clipped because the
a. transistor is operating in the saturation region.
b. transistor is operating in the cut-off region.
c. transistor is operating in the cut-off and saturation regions.
d. Q-point is too close to the saturation point.

2. Place CM switch 9 in the OFF position and CM switch 7 in the ON position to change
the value of R1 from 120 k to 10 k. Observe the output signal. The ac output
signal is equal to and in phase with the input signal because the transistor is
operating
a. at the cut-off point.
b. at the Q-point.
c. at the saturation point.
d. with the base-emitter junction in reverse bias.

3. In a CE transistor circuit operating in the active region, the ac output signal is

a. in phase with the input signal.
b. out of phase with the input signal at the collector.
c. 180 out of phase with the input signal.
d. in phase with the signal at the emitter.

4. In a CE transistor circuit, the voltage gain equals the ratio of the

a. load resistance to the emitter resistance.
b. collector resistance to the emitter resistance.
c. input voltage to the output voltage.
d. parallel resistance of the collector and load resistors to the base resistance.
ECE 301 141

5. In order for a transistor to properly amplify ac signals, it must

a. be an NPN transistor.
b. operate in the active region at all times.
c. have the base-emitter junction reverse biased.
d. have a 1K emitter resistor.

VI. CONCLUSION:
ECE 301 142

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 10
COMMON COLLECTOR CIRCUIT
(SMALL SIGNAL AMPLIFIERS)

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. COMMON COLLECTOR CIRCUIT DC OPERATION

I. OBJECTIVE:
 To be able to demonstrate the operation of the common collector transistor amplifier
circuit by using calculated and measured circuit conditions.

 To be able to determine the dc operating conditions of a common collector (CC)

transistor circuit by using a typical CC circuit.and verify the results with a multimeter
and with calculations.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 TRANSISTOR AMPLIFIER CIRCUITS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:
The collector terminal is common to both the input and output signals of the common
collector (CC) transistor circuit, as shown in Figure 4-1.

Figure 4-1. Common collector (CC) transistor circuit configurations.

ECE 301 143

The ac output signal of a CC circuit is in phase with the input signal.

The CC transistor circuit base and collector current characteristic curves are similar to the CE circuit
curves.
A CC transistor voltage divider circuit biases the base terminal with a single dc power supply, as
shown in Figure 4-2.

Figure 4-2. Voltage divider circuit (R1 and R2) for transistor base bias voltage.

The CC circuit has a voltage gain of less than 1.0 and has current gains between 10 and
500.
High input impedance and low output impedance make the CC transistor circuit
desirable for applications between a high impedance source and a low impedance load.

Figure 4-3 shows the dc operation schematic of the common collector (CC) amplifier circuit on
the TRANSISTOR AMPLIFIER CIRCUITS circuit board. The collector terminal is common to the
input and output signals and is connected to the dc power supply.

Figure 4-3. Common collector (CC) amplifier circuit for dc operation.

Because there is no collector resistor, the collector voltage [Vc] equals the dc power supply
voltage (VA), which is typically 15.0 Vdc.
You can calculate the base voltage (VB) from the voltage divider equation:

The emitter voltage (VE) is about 0.6 Vdc less than the base voltage when the transistor is
operating normally:
VE = VB - 0.6
ECE 301 144

You can calculate the emitter current (IE) from Ohm's law:
IE = VE/R3
The collector current is the difference between the emitter and base currents:

IC= IE – IB= IE
The collector current is assumed to be equal to the emitter current because the base
current is very small.
The dc load line (Figure 4-4) goes through the saturation point, Q-point, and cut-off
point.
The cut-off point is the point where VCE [CUT OFF] = VA and IC= 0 mA.

The saturation point is the point where IC(sat) = VA/R3 and VCE = 0 Vdc. The Q-point is
determined by the dc bias conditions.

Figure 4.4. DC load line for the circuit in Figure 4-3.

IV. PROCEDURE:
1. Locate the COMMON COLLECTOR circuit block on the TRANSISTOR AMPLIFIER
CIRCUITS circuit board. Connect the circuit shown in Figure 4-5.

Figure 4-5. Connection diagram.

2. Measure and record the supply voltage (VA) with reference to ground.

_________________________________________________________________
_________________________________________________________________
3. Calculate and record the base voltage (VB) for Q1, at the junction of resistors R1 and
R2, with the voltage divider equation [VB = (VA X R2) / (R 1 + R2)].
ECE 301 145

_________________________________________________________________

_________________________________________________________________

4. Measure and record the dc voltages in Table 4-1, with reference to ground.

Table 4-1

_________________________________________________________________

_________________________________________________________________

5. Do the measurements taken in step 4 indicate that the base-emitter junction is forward
biased?
_________________________________________________________________

_________________________________________________________________

6. Do the measurements taken in step 4 indicate that the base collector junction is reverse
biased?

_________________________________________________________________

________________________________________________________________

7. Would you conclude that NPN transistor Q1 is biased correctly?

_________________________________________________________________

________________________________________________________________

8. Is the transistor operating in its active region?

_________________________________________________________________

________________________________________________________________

9. Calculate and record the emitter dc current (IE) by applying Ohm's law (IE = VE/R3).

_________________________________________________________________

________________________________________________________________

10. What is the collector current (Ic)?

_________________________________________________________________

________________________________________________________________

11. The Q-point is determined by the dc bias condition of the transistor. Determine and
record Vce from the measured voltages in step 4.

_________________________________________________________________

________________________________________________________________
ECE 301 146

12. On Figure 4-6, place the Q-point at the intersection of Ic on the Y-axis and Vce on the
X-axis. Use the values calculated in steps 10 and 11.
Y-axis

Ic (mA)

X-axis

Vce (Vdc)

Figure 4-6 DC Load line

13. The cut-off point is where Vce(cut-off) = VA (dc supply voltage) and Ic=0 mA. What is
Vce (cut-off)?

_________________________________________________________________

________________________________________________________________

14. Place the cut-off point on Figure 4-6.

15. The dc load line goes through the Q-point and the cut-off point , and it intersects the Y-
axis (Vce=0 Vdc) at the saturation point (Ic(sat)). Draw the dc load line on Figure 4-6.
What is Ic (sat)?

_________________________________________________________________

________________________________________________________________

16. Set CM switch 15 in the ON position to change the value of R3 from 6.8K to 15K.
Measure and record the dc voltages in Table 4-2, with reference to ground.

Table 4-2

17. What is the new emitter current (IE)?

_________________________________________________________________

________________________________________________________________

18. What is the new VCE?

_________________________________________________________________

________________________________________________________________
ECE 301 147

19. Did changing R3 to 15K change the dc load line?

_________________________________________________________________

________________________________________________________________

20. What is the location of the new Q-point (what is Ic and VCE)?

_________________________________________________________________

________________________________________________________________

21. Did the cut-off point change?

_________________________________________________________________

________________________________________________________________

22. On Figure 4-6, plot the new Q-point and draw the new dc load line.

23. What is the new saturation point [lcsat)]?

_________________________________________________________________

________________________________________________________________

V. EVALUATION:
NOTE: To answer review questions 1 to 4. connect the CC
amplifier circuit shown in Figure 4-5 for the circuit
conditions at the end of the procedure.

1. Set CM switch 14 in the ON position to change the value of R2 from 120K to 47K.
Measure and record the dc voltages in Table 4-3, with reference to ground.

Table 4-3

The transistor is operating

a. at the saturation point.
b. in the active region.
c. at the cut-off point.
d. at an optimum Q-point.

2. With R2=47K, the emitter current (Ie) is closest to

a. 0.516 mA
b. 0.059 mA
c. 0.155 mA
d. 0.939 mA

3. With R2=47K, the

a. Slope of the load line changes
b. Saturation point changes
c. Cut-off point changes
d. Q-point changes, but the load line does not
ECE 301 148

4. With R2=47K, the new Vce is

a. 11.47 Vdc
b. 0.61 Vdc
c. 7.43 Vdc
d. 15.00 Vdc

5. In a CC transistor circuit, the collector voltage (Vc) equals

a. VA - 0.6
b. The base voltage plus the emitter voltage
c. VB - 0.6
d. The supply voltage (VA)

VI. CONCLUSION:
ECE 301 149

B. COMMON COLLECTOR CIRCUIT AC OPERATION

I. OBJECTIVE:
 To be able to determine ac operating characteristics of a common collector (CC)
amplifier by using a typical CC transistor circuit and verify the results with a multimeter
and an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 TRANSISTOR AMPLIFIER CIRCUITS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:

Figure 4-7 shows the ac operation schematic of the CC amplifier circuit on the
TRANSISTOR AMPLIFIER CIRCUITS circuit board. A sine wave generator connected between
the transistor base and ground produces the ac input signal. The ac output signal is taken
between the emitter terminal and ground. For ac signals, the collector terminal, which is
common to the input and output, is grounded by the low internal resistance of the dc power
supply.

Figure 4-7. CC amplifier circuit for ac operation.

The voltage gain (Av) of the CC transistor circuit is the ratio of the ac output voltage (Vo)
to the input voltage (Vi).
Av = Vo / Vi
The simplified sketch in Figure 4-8 illustrates the voltage gain and the input/output phase
relationship of the CC circuit. The ac emitter resistance is re. The base current is not considered
because it is much less than the emitter current. As shown by the following equations, the
voltage gain is always less than 1.0.
ECE 301 150

Figure 4-8. Simplified sketch illustrating voltage gain and phase relationship of a CC
circuit

Because the ac emitter resistance (re') is very small as compared to R3 (about 250 versus
68000), Av is slightly less than 1.0 (as Figure 4-8 makes apparent). The voltage drop
across re' is very small as compared to the voltage drop across R3. Therefore, Vo is
essentially equal to Vi in a CC circuit without a load resistor in parallel with R3. The output
signal is in phase with the input signal because the emitter current increases with the input
signal. The CC transistor circuit is also known as the emitter-follower transistor circuit.

When a very small resistor is put in parallel with R3, the ac load line becomes very steep, as
shown in Figure 4-9. The maximum non distorted peak-to

Figure 4-9. AC and dc load lines for a CC circuit.

peak voltage of the output signal is greatly reduced because the cut-off point is moved near
VCE at the Q-point. Most loads for CC transistor circuits have small impedances. Without a load
in parallel with R3, the ac and dc load lines are the same.
Some advantages of a CC transistor circuit are its high input impedance and low output
impedance properties. The CC circuit is used as an impedance matching device that matches a
high impedance source with a low impedance load.
The input impedance (Zi) equals the combined parallel resistance of R1, R2, and  x (R3 x re').
Because  x (R3 x re') is more than 100 times as large as R1 II R2, the input impedance can be
considered to equal R1 II R2.
Zi = R1 II R2
ECE 301 151

For the circuit in Figure 4-7, Zi is 60 kQ.

The following equation is for the output impedance (Zo).

Because the emitter resistor (R3) is large, Zo essentially equals [re’ + (RGEN II R1 II R2) ] / .
You can measure Zo by connecting potentiometer R4 in parallel with R3 and adjusting R4 to
obtain an output signal (Vo) that is half the input signal (Vi). With these conditions, the
measured resistance of R4 approximately equals Zoo

IV. PROCEDURE:
1. Locate the COMMON COLLECTOR circuit block on the TRANSISTOR AMPLIFIER
CIRCUITS circuit board. Connect the circuit shown in Figure 4-10.

Figure 4-10. Connection diagram.

2. Measure and record the supply voltage (VA), with reference to ground.

____________________________________________________________

____________________________________________________________

3. Measure and record the dc voltages in Table 4-4, with reference to ground. Is the NPN
transistor Q1 properly biased for ac operation?

Table 4-4

____________________________________________________________

____________________________________________________________

4. While observing the signal on channel 1 of the oscilloscope, adjust the sine wave
generator for a 1 kHz, 4.00 Vpk-pk ac input signal (Vi) at the base of transistor Q1.
ECE 301 152

5. Connect the channel 2 probe of the oscilloscope to the ac output of Q1, which is at the
emitter terminal. What is the peak-to-peak voltage of the ac output signal (Vo)?

____________________________________________________________

____________________________________________________________

6. Is there any distortion or clipping of the sine wave signal between the ac input and
output?
____________________________________________________________

____________________________________________________________

7. What is the phase relationship between the output and input signals?

____________________________________________________________

____________________________________________________________

8. Calculate and record the voltage gain (Av = Vo/Vi ).

____________________________________________________________

____________________________________________________________

9. Adjust the input signal (Vi) to 70 mVpk-pk. Observe the output signal (Vo) on channel 2
of the oscilloscope to be sure that it is essentially equals the input signal (70 mVpk-pk).
Turn the knob on variable resistor R4 fully CW. With a two post connector, connect R4
to C2. Turn the knob on R4 CCW until Vo is exactly half of Vi (35 mVpk-pk). Without
disturbing the R4 knob setting disconnect R4 from C2. Measure and record the
resistance of R4.

Note: This measurement has a tolerance of ± 50%.

____________________________________________________________

____________________________________________________________

10. To what characteristic is the value of R4 essentially equal?

____________________________________________________________

____________________________________________________________

11. Calculate and record the input impedance (Zi) from the following equation.
Zi = R1 ll R2 = (R1 X R2) / ( R1 +R2)

____________________________________________________________

____________________________________________________________

12. Connect R4 to C2 without disturbing the R4 knob setting. Slowly increase the ac input
signal until the valley of the output signal becomes distorted. What point in the load line
is reached when the output becomes distorted?
____________________________________________________________

____________________________________________________________

Note: The following steps require a large input signal. Disconnect any input
attenuator network.
13. Disconnect R4 from C2 by removing the two-post connector. Slowly increase the ac
input signal until the valley of the output signal just starts to become distorted again.
Why does it take a larger input signal (Vi) to distort the output signal when R4 is not
connected in parallel with R3?
ECE 301 153

____________________________________________________________

____________________________________________________________

14. Reduce the input signal (Vi) until the output signal is no longer distorted. The value of R2
changes from 120K to 47K when CM switch 14 is set to the ON position. Turn on CM
switch 14. Observe and record what happens to the output signal.

____________________________________________________________________

____________________________________________________________________

15. Without changing the input signal setting, disconnect the sine wave generator from the
circuit. Measure and record the collector-emitter voltage difference (VCE) with CM switch
14 on.
____________________________________________________________________

____________________________________________________________________

16. Is VCE with CM switch 14 on larger or smaller than VCE calculated from the
measurements recorded in step 3?

____________________________________________________________________

____________________________________________________________________

17. What causes the result in step 14?

____________________________________________________________________

____________________________________________________________________

18. With CM switch 14 on, connect the sine wave generator to the circuit. Reduce the input
signal until there is no distortion in the output signal. Why does reducing the input signal
eliminate distortion of the output signal?
____________________________________________________________________

____________________________________________________________________

V. EVALUATION:
NOTE: To answer review questions 1 and 2, connect the CC amplifier circuit
shown in Figure 4-10 for the circuit conditions at the end of the procedure.

1. Set the input signal (Vi) to 4.0 Vpk-pk. Set CM switch 15 in the ON position to change
the value of R3 from 6.8K to 15K. Observe the output signal (Vo). The transistor is
a. operating at the cut-off point.
b. operating in the active region during the complete cycle.
c. operating at the saturation point.
d. with the base-emitter junction in reverse bias.

2. When R3 was changed from 6.8K to 15K, the

a. slope of the load line became less steep.
b. slope of the load line became steeper.
c. Q-point did not change.
d. base bias voltage changed.

3. In a CC transistor circuit, the ac output signal is

a. in phase with the input signal.
b. 180 degrees out of phase with input signal.
c. one-half of the peak-to-peak voltage of the input signal.
d. in phase and always greater than the input signal.
ECE 301 154

4. In a CC transistor circuit, the input

a. and output impedances are low.
b. impedance is low and the output impedance is high.
c. and output impedances are high.
d. impedance is high and the output impedance is low.

5. A CC transistor circuit is also called a(n)

a. collector-follower circuit
b. base-follower circuit.
c. emitter-follower circuit.
d. low impedance transistor circuit.

VI. CONCLUSION:
ECE 301 155

C. COMMON COLLECTOR CIRCUIT AC OPERATION

I. OBJECTIVE:
 To be able to determine ac operating characteristics of a common collector (CC)
amplifier by using a typical CC transistor circuit and verify the results with a multimeter
and an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 TRANSISTOR AMPLIFIER CIRCUITS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:
Figure 4-7 shows the ac operation schematic of the CC amplifier circuit on the
TRANSISTOR AMPLIFIER CIRCUITS circuit board. A sine wave generator connected between
the transistor base and ground produces the ac input signal. The ac output signal is taken
between the emitter terminal and ground. For ac signals, the collector terminal, which is
common to the input and output, is grounded by the low internal resistance of the dc power
supply.

Figure 4-7. CC amplifier circuit for ac operation.

The voltage gain (Av) of the CC transistor circuit is the ratio of the ac output voltage (Vo)
to the input voltage (Vi).
Av = Vo / Vi
The simplified sketch in Figure 4-8 illustrates the voltage gain and the input/output phase
relationship of the CC circuit. The ac emitter resistance is re. The base current is not considered
because it is much less than the emitter current. As shown by the following equations, the
voltage gain is always less than 1.0.
ECE 301 156

Figure 4-8. Simplified sketch illustrating voltage gain and phase relationship of a CC
circuit

Because the ac emitter resistance (re') is very small as compared to R3 (about 250 versus
68000), Av is slightly less than 1.0 (as Figure 4-8 makes apparent). The voltage drop
across re' is very small as compared to the voltage drop across R3. Therefore, Vo is
essentially equal to Vi in a CC circuit without a load resistor in parallel with R3. The output
signal is in phase with the input signal because the emitter current increases with the input
signal. The CC transistor circuit is also known as the emitter-follower transistor circuit.

When a very small resistor is put in parallel with R3, the ac load line becomes very steep, as
shown in Figure 4-9. The maximum non distorted peak-to

Figure 4-9. AC and dc load lines for a CC circuit.

peak voltage of the output signal is greatly reduced because the cut-off point is moved near
VCE at the Q-point. Most loads for CC transistor circuits have small impedances. Without a load
in parallel with R3, the ac and dc load lines are the same.
Some advantages of a CC transistor circuit are its high input impedance and low output
impedance properties. The CC circuit is used as an impedance matching device that matches a
high impedance source with a low impedance load.
The input impedance (Zi) equals the combined parallel resistance of R1, R2, and  x (R3 x re').
Because  x (R3 x re') is more than 100 times as large as R1 II R2, the input impedance can be
considered to equal R1 II R2.
Zi = R1 II R2
ECE 301 157

For the circuit in Figure 4-7, Zi is 60 kQ.

The following equation is for the output impedance (Zo).

Because the emitter resistor (R3) is large, Zo essentially equals [re’ + (RGEN II R1 II R2) ] / .
You can measure Zo by connecting potentiometer R4 in parallel with R3 and adjusting R4 to
obtain an output signal (Vo) that is half the input signal (Vi). With these conditions, the
measured resistance of R4 approximately equals Zoo

IV. PROCEDURE:

19. Locate the COMMON COLLECTOR circuit block on the TRANSISTOR AMPLIFIER
CIRCUITS circuit board. Connect the circuit shown in Figure 4-10.

Figure 4-10. Connection diagram.

20. Measure and record the supply voltage (VA), with reference to ground.

____________________________________________________________

____________________________________________________________

21. Measure and record the dc voltages in Table 4-4, with reference to ground. Is the NPN
transistor Q1 properly biased for ac operation?

Table 4-4

____________________________________________________________

____________________________________________________________

22. While observing the signal on channel 1 of the oscilloscope, adjust the sine wave
generator for a 1 kHz, 4.00 Vpk-pk ac input signal (Vi) at the base of transistor Q1.
ECE 301 158

23. Connect the channel 2 probe of the oscilloscope to the ac output of Q1, which is at the
emitter terminal. What is the peak-to-peak voltage of the ac output signal (Vo)?

____________________________________________________________

____________________________________________________________

24. Is there any distortion or clipping of the sine wave signal between the ac input and
output?
____________________________________________________________

____________________________________________________________

25. What is the phase relationship between the output and input signals?

____________________________________________________________

____________________________________________________________

26. Calculate and record the voltage gain (Av = Vo/Vi ).

____________________________________________________________

____________________________________________________________

27. Adjust the input signal (Vi) to 70 mVpk-pk. Observe the output signal (Va) on channel 2
of the oscilloscope to be sure that it essentially equals the input signal (70 mVpk-pk).
Turn the knob on variable resistor R4 fully CWo With a two-post connector, connect R4
to C2. Turn the knob on R4 CCW until Vo is exactly half of Vi (35 mVpk-pk). Without
disturbing the R4 knob setting, disconnect R4 from C2. Measure and record the
resistance of R4.

NOTE: This measurement has a tolerance of ±50%

____________________________________________________________

____________________________________________________________

28. To what characteristic is the value of R4 essentially equal?

____________________________________________________________

____________________________________________________________

29. Calculate and record the input impedance (Zi) from the following equation.

Zi = R1 ll R2 – (R1 x R2) / R1 + R2)

____________________________________________________________

____________________________________________________________

NOTE: For the following steps, refer to Figure 4-9

30. Connect R4 to C2 without disturbing the R4 knob setting. Slowly increase the ac input
signal until the valley of the output signal becomes distorted. What point on the load line
is reached when the output becomes distorted?
____________________________________________________________

____________________________________________________________
NOTE: The following steps require a large input signal. Disconnect any input
attenuator network

31. Disconnect R4 from C2 by removing the two-post connector. Slowly increase the ac
ECE 301 159

input signal until the valley of the output signal just starts to become distorted again.
Why does it take a larger input signal (Vi) to distort the output signal when R4 is not
connected in parallel with R3?

32. Reduce the input signal (Vi) until the output signal is no longer distorted. The value of R2
changes from 120K to 47K when CM switch 14 is set to the ON position. Turn on CM
switch 14. Observe and record what happens to the output signal.

____________________________________________________________________

____________________________________________________________________

33. Without changing the input signal setting, disconnect the sine wave generator from the
circuit. Measure and record the collector-emitter voltage difference (VCE) with CM switch
14 on.
____________________________________________________________________

____________________________________________________________________

34. Is VCE with CM switch 14 on larger or smaller than VCE calculated from the
measurements recorded in step 3?

____________________________________________________________________

____________________________________________________________________

35. What causes the result in step 14?

____________________________________________________________________

____________________________________________________________________

36. With CM switch 14 on, connect the sine wave generator to the circuit. Reduce the input
signal until there is no distortion in the output signal. Why does reducing the input signal
eliminate distortion of the output signal?

____________________________________________________________________

____________________________________________________________________

V. EVALUATION:
NOTE: To answer review questions 1 and 2, connect the CC amplifier circuit
shown in Figure 4-10 for the circuit conditions at the end of the procedure.

6. Set the input signal (Vi) to 4.0 Vpk-pk. Set CM switch 15 in the ON position to change
the value of R3 from 6.8K to 15K. Observe the output signal (Vo). The transistor is
a. operating at the cut-off point.
b. operating in the active region during the complete cycle.
c. operating at the saturation point.
d. with the base-emitter junction in reverse bias.

7. When R3 was changed from 6.8K to 15K, the

a. slope of the load line became less steep.
b. slope of the load line became steeper.
c. Q-point did not change.
d. base bias voltage changed.

8. In a CC transistor circuit, the ac output signal is

a. in phase with the input signal.
b. 180 degrees out of phase with input signal.
c. one-half of the peak-to-peak voltage of the input signal.
d. in phase and always greater than the input signal.
ECE 301 160

9. In a CC transistor circuit, the input

a. and output impedances are low.
b. impedance is low and the output impedance is high.
c. and output impedances are high.
d. impedance is high and the output impedance is low.

10. A CC transistor circuit is also called a(n)

a. collector-follower circuit
b. base-follower circuit.
c. emitter-follower circuit.
d. low impedance transistor circuit.

VI. CONCLUSION:
ECE 301 161

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 11
JFET & Dual Gate MOSFET Fundamentals

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. INTRODUCTION TO FET: COMPONENT LOCATION & IDENTIFICATION

I. OBJECTIVE:
 To be able to locate and identify the major components on the FET FUNDAMENTALS
circuit board by using the theory found in the manual

 .To be able to locate all major circuits on the FET FUNDAMENTALS circuit board by
using your manual and trainer and verify the results by correctly identifying circuits and
their major components.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace Generator, sine wave

III. THEORY:
The FIELD-EFFECT TRANSISTOR FUNDAMENTALS circuit board is made up of nine
student training circuit blocks and a GENERATOR BUFFER circuit.
Four circuit blocks explore the junction field-effect transistor (JFET).
One circuit block uses a special type of FET called a metal oxide semiconductor FET
(MOSFET).
One block uses a unijunctlon transistor (UJT). a form of transistor having one PN
junction.
The remaining three circuit blocks contain a thermistor . a photoresistor and a fiber
optic link (transmit/receive).
The schematic symbols of N-channel and P-channel JFETs are shown in Figure 1-1

Figure 1-1. JFET schematic symbols.

ECE 301 162

A JFET is a three-terminal device. The terminals are called drain, D; source, S, and
gate, G.

Figure 1-2 shows the schematic symbols of N-channel and P-channel dual gate
MOSFET devices.

n-channel DUAL MOSFET P-channel Dual MOSFET

Figure 1-2. Dual gate MOSFET schematic symbols.

The device has two gate terminals (G1 and G2), a drain terminal, and a source
terminal.
The schematic symbols of N- and P-channel UJTs are shown in Figure 1-3. Note
the difference in terminal labels between the UJT and the FET devices.

A UJT is a three-terminal device. The terminals are called base 2 ,B2 ; base 1,
B1; and emitter , E.

Figures 1-4(a) and (b) show the schematic symbols of a thermistor and a
photoresistor. These devices are generally called transducers because they convert one
form of energy, such as heat, into resistance change.

The schematic representation of a fiber optic transmit and receive pair is shown in
Figures 1-5(a) and (b). A fiber optic cable, which acts as the conduit for light, connects
the transmit and receive pair.
ECE 301 163
ECE 301 164

The FET FUNDAMENTALS circuit board provides examples of field-effect transistor

circuits as well as several other types of semiconductor components. This exercise provides
a brief introduction to the board to help you locate the circuits and components presented in
later units.
The board is organized into nine circuit blocks (a tenth block serves only to mount the
GENERATOR BUFFER if needed). Each circuit block includes both active and passive
components. Table 1-1 lists the standard industrial part numbers of the devices used on the
trainer. The table also indicates in which circuit blocks the devices are used.
Table 1-1

DEVICE PART NO. CIRCUIT BLOCK

JFET 2N5459 JFET

JFET AMPLIFIER

JFET CURRENT SOURCE

COLPITTS/HARTLEY
2N5488
OSCILLATOR
MOSFET 40841 DUAL GATE MOSFET

UJT 2N2848 UNIJUNCTION TRANSISTOR

XMTR HFBR-1510 FIBE R OPTIC LINK
OR T-1510
RCVR HFBR-2501 FIBER OPTIC LINK
OR R-2501
TRANSDUCER KB23J1 THERMISTOR

CL5M5 PHOTORESISTOR

IV. PROCEDURE:

1. Locate the COLPITTS/HARTLEY OSCILLATOR circuit block of the FET

FUNDAMENTALS circuit board. What type of active device is used in this circuit?
___________________________________________________________________

___________________________________________________________________

2. How many JFET circuits are provided on the circuit board?

___________________________________________________________________

___________________________________________________________________

3. Which circuits on the board include potentiometers?

___________________________________________________________________

___________________________________________________________________

4. Is the active component in the DUAL GATE MOSFET circuit block a P-channel or an N-
channel device?

___________________________________________________________________

___________________________________________________________________
ECE 301 165

5. How many LEDs are included on the circuit board?

___________________________________________________________________

___________________________________________________________________
6. What type of diode is CR1 on the FIBER OPTIC LINK circuit block?

___________________________________________________________________

___________________________________________________________________

7. Locate the THERMISTOR circuit block. Based on the silk screened RT1 symbol, what
physical energy will cause the resistance of the device to change?

___________________________________________________________________

___________________________________________________________________

8. Locate the PHOTORESISTOR circuit block. Based on the silk screened R2 symbol.
What physical energy will cause the resistance of the device to change?

___________________________________________________________________

___________________________________________________________________

9. Locate the JFET circuit block. Is the negative variable supply connected to the Q1 drain
circuit?
___________________________________________________________________

___________________________________________________________________

10. What F.A.C.E.T. component must be used to connect the Q1 gate circuit of the JFET
circuit block to the negative variable supply?
___________________________________________________________________

___________________________________________________________________

V. EVALUATION:
1. Which device(s) on the circuit board is(are) most sensitive to the effects of ESD?
a. the UJT
b. the JFET
c. the MOSFET
d. the thermistor and zenor diode

2. The device in Figure 1-6 is

a. P-channel JFET.
b. an N-channel JFET.
c. an N-channel MOSFET.
d. None of the above.
ECE 301 166

3. A thermistor is used in a circuit to

a. produce heat from an electric current flow.
b. produce an electric current flow from heat.
c. detect changes in applied circuit voltage.
d. detect changes in temperature.

4. A photoresistor is used in a circuit to

a. produce light from an electric current flow.
b. produce an electric current flow from light.
c. detect changes in applied circuit voltage.
d. detect changes in light.

5. JFETs, MOSFETs, and UJT devices may be classified as

a. active devices.
b. neutral devices.
c. passive devices.
d. semi-passive devices.

VI. CONCLUSION:
ECE 301 167

B. JFET OPERATING CHARACTERISTICS

I. OBJECTIVE:
 To be able able to describe the operation of a Junction field-effect transistor (JFET) by
using dc and ac measurements.

 To be able to describe the effects of drain voltage on drain current at zero gate bias by
using a JFET test circuit and verify the results with a multimeter.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power Supply, 15 Vdc (2 required)
 Multlmeter
 Oscilloscope, dual trace Generator, sine wave

III. THEORY
The Junction field-effect transistor (JFET) Is a unipolar device (It has one PN Junction).
Figure 2-1 shows that a JFET has three active elements: gate, source and drain.
 ECE 301 168

In Figure 2-3, the PN, or gate-to-channel diode, junction must be reverse biased to
reduce channel current. With sufficient bias, channel current can be reduced to zero (device
turned off).
The width of the depletion region is increased by an increase in the gate-to source bias
voltage (in its reverse bias direction).
In a JFET device, the drain current equals the source current.
JFETs have a very high input impedance provided that the gate-to-source bias voltage
does not forward bias the gate-to-channel PN junction. Under proper bias conditions, gate
current does not flow.
A JFET operates with its junction in a reverse biased state (zero gate current). Bias
voltage, applied between the gate and source terminals (Figure 2-3), controls channel current
and produces an electric field (the depletion region).
The name JFET means Junction (one PN junction) Field-Effect (reverse biased junction
voltage) Transistor.
Figure 2-4 shows the proper bias voltages required for an N-channel and a P-channel
JFET. The figure also Indicates proper VDD (drain circuit supply voltage) polarity.

JFETs are linear devices that exhibit an ohmic region (or resistive region). On a JFET
characteristic curve, the ohmic region falls between the zero and saturation channel current
points.

Figure 2-5 illustrates a JFET characteristic curve and its major operational points.

JFETs are available in a variety of package styles. Typical packages are shown in Figure 2-6.
 ECE 301 169

JFETs have a natural resistance to electrostatic discharge and are not easily harmed;
however, you should use caution when you handle FETs.

NEW TERMS AND WORDS

 Avalanche region - the destructive breakdown area of an FET that results from
excessive drain-to-source circuit voltage.
 Channel - the source-to-drain-controlled path for current flow through an FET device.
 Cut-off - an FET state in which no source-to-drain current flows.
 Depletion mode FET - a device that is in the on state and must be biased to an off
state.
 Drain - the FET terminal that corresponds to the collector of a bipolar transistor.
 Gate - the FET terminal that corresponds to the base of a bipolar transistor.
 N-channel - an FET device with a P type (doped) gate material.
 Ohmic region - the linear operating area between a JFET's off and saturated limits.
 P-channel - an FET device with an N type (doped) gate material.
 Pinch-off - FET saturation or constant current region; an operating point at which an
Increase in draln-to-source voltage does not produce a change In the draln-to-source
current.
 Source - the FET terminal that corresponds to the emitter of a bipolar transistor.

On the JFET characteristic curve in Figure 2-7, pinch-off (saturation region) voltage Is
represented by VP. In this region, an increase in drain voltage does not increase the drain
current.
ECE 301 170

On the JFET characteristic curve in Figure 2-7, pinch-off (saturation region) voltage Is
represented by VP. In this region, an increase in drain voltage does not increase the drain
current.
Drain current (ID or IDS) increases as drain voltage (VDS) increases until pinch-off saturation of
the JFET device occurs.
Within the saturation point of a JFET is Its constant current region. In this region, drain current Is
referred to as IDSS or IDS(sat).
Below the Vp point, IDS is dependent on VDS. This area of operation is the ohmic region of the
JFET.
A considerable variation exists in the Vp point of the same type of JFETs.
Beyond the saturation region of a JFET, increasing VDS produces avalanche breakdown. This
area is the avalanche region of the JFET.
A JFET operated in its ohmic region can be represented by a variable resistor. Within the ohmic
region, current flow through the JFET varies according to Ohm's law.

IV. PROCEDURE:
1. Locate the JFET circuit block on the FET FUNDAMENTALS circuit board. Connect the
circuit shown In Figure 2-8.

NOTE: Four two-post connectors are required.

2. Adjust VDD (positive variable supply) to 0.5 Vdc. Measure the voltage drop of R3. Use
Ohm's law (I = E/R) to calculate the drain-to-source current (IDS) through Q1. Record
your values in Table 2-1.

Table 2-1. IDS versus VGG data table.

Voo ; Vdc IDS , mA

0 0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
8.0
9.0
10.0
ECE 301 171

NOTE: Values vary due to JFET characteristics. Your values are

correct if they range between 0 mA and 14 mA.
3. Repeat step 2 for each value of VDD given in Table 2-1.
NOTE: Your results should vary between 0 mA and 16 mA of drain current,
depending on the characteristic of your FET

4. Based on your results. does the value of drain current increase or decrease with drain
voltage?
____________________________________________________________________
____________________________________________________________________
5. What gate bias voltage is provided by your test circuit and why?
____________________________________________________________________
____________________________________________________________________
6. Use your data from Table 2-1 to plot the characteristic curve of your JFET (Q1) on the
graph of Figure 2-9. Draw a smooth curve through your plotted points.

7. On your curve, mark the transition point from the ohmic region to the constant current
region. Extend a vertical line from this point down to the VDD scale. Record the value
of the pinch-off voltage.

Vp = ________________ Vdc
8. In the ohmic region of your curve, does the drain current increase or decrease with
drain voltage?
____________________________________________________________________
____________________________________________________________________
9. To make the following statement true, underline the correct answer. In the constant
current region of your curve, the resistance of the channel must (increase, remain the
same, decrease) in order for current to remain constant with increasing values of
drain voltage.
ECE 301 172

10. Based on your data, can the drain current of a zero biased JFET device be reduced
to zero while drain voltage is applied?
____________________________________________________________________
____________________________________________________________________

V. EVALUATION:
1. In a zero gate biased JFET, the
a. drain and gate terminals are connected.
b. drain and source terminals are connected.
c. gate and source terminals are connected.
d. gate and drain terminals are at the same potential.

2. A depletion mode JFET is

a. normally on and must be biased off.
b. normally off and must be biased on.
c. always in its saturated mode.
d. operated beyond pinch-off voltage.

3. The ohmic region of a JFET refers to its

a. constant current mode of operation.
b. zero gate bias.
c. negative resistance.
d. linear mode of operation.

4. Which of the following devices can be classified as unipolar?

a. an NPN transistor
b. a PNP transistor
c. a junction field-effect transistor
d. All of the above.

5. The formation of a depletion region refers to

a. a constant drain current characteristic.
b. gate breakdown.
c. uncontrolled gate current.
d. a constant gate current.

VI. CONCLUSION:
ECE 301 173

C. THE EFFECT OF GATE BIAS ON PINCH-OFF

I. OBJECTIVE:
 To be able to describe the effect that gate bias has on pinch-off by using a JFET circuit
and verify the results with a multimeter.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power Supply, 15 Vdc (2 required)
 Multlmeter
 Oscilloscope, dual trace Generator, sine wave

III. THEORY:

The drain current of a JFET may be reduced to zero by sufficient gate bias (in a
reverse direction). This area is referred to as cut-oft
Applying a forward bias to a JFET gate allows gate current to flow.
JFETs are normally operated with gates in zero or reverse biased states.
A reverse biased JFET gate does not draw gate current from the external bias circuit.
The gate represents a very high impedance to the external bias circuit.
For a fixed value of drain voltage. the operating curve of a JFET circuit is determined
by the applied gate-to-source bias voltage.
One major effect of gate bias is the reduction in the value of the pinch-off (saturation)
voltage level.
JFETs usually operate with a maximum of 5V of reverse bias gate voltage. Higher
voltages can destroy the gate-to-channel PN junction.
Reverse bias voltage is required to turn off a depletion mode JFET device. Recall that
a depletion mode device is on with zero bias.
An N-channel JFET requires a negative gate voltage (with respect to the source) in
order to deplete the channel. When the channel is depleted. the device turns off because the
negative bias voltage has generated a large depletion area. This area effectively blocks the
flow of drain current.

IV. PROCEDURE:
1. Locate the JFET circuit block on the FET FUNDAMENTALS circuit board. Connect the
circuit shown in Figure 2-10.

2. Adjust the negative variable supply (VGG) for a gate-to-source bias (VGS) of 0 Vdc. Adjust
the VDD supply to 10 Vdc.
ECE 301 174

NOTE: Calculate the drain current (IDS) by using the voltage drop of R3
(ID = VR3 / R3). Measure the gate-to source bias as indicated by Figure 2-10.
3. With your multlmeter, monitor the drop of R3. Calculate and record the drain current (ID)
for each value of gate voltage (VGG) given In Table 2-2. Perform this step for both values
of drain voltage listed In the table.

NOTE: Your values of drain current will vary between 0 mA and 20 mA.

Table 2-2. Gate bias control data.

VDD =10 Vdc V DD = 5 Vdc

V GG [Vdc] ID [mA] V GG [Vdc] ID [mA]

-4 -4
-3.5 -3.5
-3 -3
-2.5 -2.5
-2 -2
-1 -1
-0.5 -0.5
0 0

4. Based on your results, did the gate bias voltage needed to turn off the JFET increase,
remain about the same, or decrease as the drain voltage changed?

____________________________________________________________________
____________________________________________________________________

5. Based on your Table 2-2 data, does an Increase In the gate bias voltage result in an
Increase or a decrease in the pinch-off (saturation) current of the JFET?

6. Adjust the gate bias voltage for -0.5 Vdc. Using the VDD values of Table 2-3, complete
the IDS column. Repeat your test using a -3 Vdc value for VGG. Record all values In the
proper columns of Table 2-3.

NOTE: Your values. of drain current will vary between 0 mA and 20 mA. If
there is no conduction (IDS) with VGG equal to -3 Vdc, reduce VGG until you
observe conduction of several mA.
ECE 301 175

7. Using the VDD and lDS data In Table 2-3, plot two curve, on the graph of Figure 2-11.
Label each plot for the specific VGG voltage (-0.5 Vdc and -3 Vdc).

8. Based on your data and plots, what effect did a higher value of bias voltage have on the
pinch-off saturation point of the JFET under test?

____________________________________________________________________
____________________________________________________________________

V. EVALUATION:
1. For an N-channel JFET, bias voltage measured at the gate terminal
a. should be positive with respect to the source.
b. should be negative with respect to the source.
c. can be either positive or negative.
d. should be 0V.

2. An increase in the bias voltage of a JFET

a. . has no effect on the pinch-off voltage.
b. increases the pinch-off voltage point.
c. decreases the pinch-off voltage point.
d. changes polarity of the pinch-off voltage.

3. The gate bias voltage of a JFET

a. ensures a minimum gate current.
b. must forward bias the gate-channel junction.
c. controls the size of the depletion area.
d. should be greater than 5V.

4. You can observe the effect of a varying gate bias voltage by observing
a. varying drain current.
b. steady state drain current.
c. a change in gate current.
d. steady state gate current.

5. In order for an N-channel JFET to be turned off,

a. it should be operating in the saturation region.
b. the gate and source terminals must be shorted.
c. the gate should be zero biased.
d. its channel area must be depleted.

VI. CONCLUSION:
ECE 301 176

D. JFET DYNAMIC CHARACTERISTIC CURVES

I. OBJECTIVE:
 To be able to observe the lDS-VDS family of curves by changing the gate bias voltage and
verify the results with an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit

 FET FUNDAMENTALS Circuit Board
 Power Supply, 15 Vdc (2 required)
 Multlmeter
 Oscilloscope, dual trace Generator, sine wave

III. THEORY:

A JFET can be used as an amplifier.

Dynamic operating curves are used to predict performance levels of JFETs.
A family of curves requires that VDD and VGG be adjustable.
A rectified sine wave (to maintain proper drain polarity) Is applied as the
circuit source supply to the JFET. This signal sweeps the drain voltage between zero and peak
voltage.
Gate bias, provided by a variable negative supply, determines the Vp point of the JFET.
Within the zero and maximum lDS conduction points, each specific value of gate bias
produces a specific operating characteristic curve.
Characteristic curves are used to set proper operating points (recall transistor load lines)
for amplifier circuits.

IV. PROCEDURE:
1. Locate the JFET circuit block on the FET FUNDAMENTALS circuit board. Connect the
circuit shown In Figure 2-12. Note the oscilloscope probe connection points.

NOTE: In the figure, components shown within the dashed block are automatically
connected to your test circuit.

2. Adjust the VGG supply for 0 Vdc. Adjust the sine wave generator for a 12 Vpk-pk, 1000
Hz signal.
ECE 301 177

3. Select the XY mode of display for the oscilloscope. Adjust the input channel amplitude
controls for a convenient display.

NOTE: For this procedure, calibrated scope waveforms are not required.

4. As you vary the bias supply between 0 Vdc and -3 Vdc, you should observe a curve
variation on the oscilloscope. Compare your observed waveforms to those given in
Figure 2-13.

5. Based on your observations, does the Vp point remain approximately the same for all
curves?

____________________________________________________________________
____________________________________________________________________

6. Based on your observations, does a small change in bias voltage produce a large
change in drain current?

____________________________________________________________________
____________________________________________________________________

7. Is there a linear operating area for each curve you have observed?

____________________________________________________________________
____________________________________________________________________

8. Do you think that the JFET will function as an amplifier?

____________________________________________________________________
____________________________________________________________________

V. EVALUATION:
1. For dynamic JFET operation, small changes in gate bias produce
a. a large effect in pinch-off voltage values.
b. little effect in drain current.
c. a large effect in gate current.
d. a large change in drain current.

2. Dynamic JFET characteristic curves observed on an oscilloscope display

a. gate current and drain voltage.
b. gate voltage and drain current.
c. drain current and drain voltage.
d. drain and source voltage.
ECE 301 178

3. Which of the following parameters is not observed on a dynamic curve

oscilloscope display?
a. the JFET avalanche point.
b. drain voltage.
c. drain current.
d. All of the above.

4. On a JFET dynamic curve, the linear portion of the curve

a. is beyond the pinch-off (saturation) point.
b. occurs at the device zero bias point.
c. can not be observed.
d. falls between device turnoff and Vp.

5. The zero bias operating point of a JFET results in

a. minimum drain current.
b. maximum drain current.
c. device turnoff.
d. avalanche destruction of the device.

VI. CONCLUSION:
ECE 301 179

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 12
JFET AMPLIFIER

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. JFET AMPLIFIER DC OPERATION:

I. OBJECTIVE:
 To be able to describe the operation of a JFET voltage amplifier by using dc
measurements and observed waveforms.
 To be able to measure dc operation voltages by using a JFET amplifier and
verify the results with a multimeter.


II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:
Two methods are used to bias JFET amplifiers: source bias (self bias), as shown in
Figure 3-1[a], and fixed bias [ gate bias], as shown in Figure 3-1 [b]

In gate bias, the values of the fixed bias supply are used to oppose a part of the
incoming signal.
ECE 301 180

JFET amplifiers must be biased correctly to:

1. stabilize the circuit against parameter variations between transistors of the same type.

2. ensure that the amplified signal is not distorted. Figure 3-2 illustrates distorted and
undistorted sine wave signals.

3. prevent an incoming signal from forward biasing the gate-channel PN junction.

The voltage drop across a source resistor produces degenerative feedback (reduces
circuit gain).
A source resistor bypass capacitor, or source bypass, reduces the effect of
degenerative feedback (increases circuit gain), while it allows dc bias.

A common source amplifier circuit inverts the input signal.

UNDISTORTED SINE WAVE

POSITIVE DISTORTION (CLIPPED)

NEGATIVE DISTORTION (CLIPPED)

Figure 3-2. Comparison of undlstorted and distorted sine waves.

NEW TERMS AND WORDS

 Amplifiers - circuits that increase the level of an input signal without distortion.
 Common source amplifier - a circuit having an input signal applied to the gate and
an output signal taken from the drain (both with respect to circuit common).
 Degenerative feedback- a type of feedback that reduces circuit gain but increases
circuit bandwidth.
 Fixed bias - a type of JFET bias that requires a fixed level of dc bias voltage
between the gate and source terminals of the device.
 Source bias - a type of JFET bias that requires a resistor in series with the source
terminal.
 Source bypass - capacitive bypass of a source resistor.
 Transconductance - a measure of the amplification capability of a JFET, stated in
siemens.
ECE 301 181

To operate a JFET source amplifier as a linear circuit. the gate-source reverse bias must be set so
that an incoming signal does not forward bias the JFET diode junction.
For resistive loads, the gate bias voltage is chosen so that half of the supply voltage is dropped
across the load resistor.
Figure 3-3 shows a typical JFET voltage amplifier that employs source bias control.

The voltage drop across the source resistor in Figure 3-3 produces a gate-to-source
bias. This voltage is positive at the source terminal (with respect to circuit common).

With respect to the source terminal of Figure 3-3. the gate terminal is negative.

IV. PROCEDURE:
1. Locate the JFET AMPLIFIER circuit block on the FET FUNDAMENTALS circuit board.
Connect the circuit shown in Figure 3-4.

2. With your multimeter, measure and record the value of the fixed positive supply on your
circuit board.
______________________________________________________________________

______________________________________________________________________

3. Measure the gate-to-source bias voltage (across the gate-to-source) of your circuit.
Does this reading indicate a full on or full off JFET device?

______________________________________________________________________

______________________________________________________________________
ECE 301 182

4. Measure the voltage drop of R3. Use Ohm's law (V / R) to calculate the drain current.
Record both values

______________________________________________________________________

______________________________________________________________________

5. Measure and record the voltage between the drain terminal (VD) and circuit common. Is
this value equal to the difference between VDD and VR3?
______________________________________________________________________

______________________________________________________________________

6. Modify your test circuit by inserting R2 into the source terminal current path (remove the
two-post connector across R2).

7. Measure and record VD, the voltage from the drain to circuit common. With respect to
drain current (1D = VR3 / R3), what does this voltage reading indicate about the circuit?
NOTE: Compare your voltage reading to that recorded in step 5.

______________________________________________________________________

______________________________________________________________________

8. Measure and record Vs, the voltage from the source to circuit common. Should the
voltage approximately equal the gate-to-source bias voltage of the circuit?
______________________________________________________________________

______________________________________________________________________

9. Measure the gate-to-source voltage on your test circuit. Connect the positive (red) lead
of your multlmeter to the gate of Q1. Does the polarity of your reading indicate an N-
channel or a P-channel device?

______________________________________________________________________

______________________________________________________________________

V. EVALUATION:

1. Place CM switch 15 in the ON position to change the value of R2 from 27000 to 37000.
Measure and record the voltages In Table 3-1. An Increase of value in R2
a. decreased circuit bias voltage.
b. caused a slightly greater bias voltage.
c. had a large effect on circuit bias voltage.
d. had a large effect on drain current.
ECE 301 183

Table 3-1.

VOLTAGE WITHOUT CM WITH CM

VD

VS
VGS

2. Based on your data, an increase in gate bias produced

a. a decrease in drain current.
b. an increase in drain current.
c. no change in drain current.
d. no change in drain current but a change in source current.

3. The measured gate-to-source bias voltage Is

a. slightly greater than the source voltage.
b. exactly equal to the source voltage.
c. slightly less than the source voltage.
d. None of the above.

4. Place CM switch 15 in the OFF position and CM switch 18 in the ON position to

decrease the value of R3. Carefully measure the source voltage with CM switch 18 in
both the ON and OFF positions. Your readings Indicate
a. a large change In drain current.
b. no change in circuit bias voltage.
c. a small change in gate current.
d. a large change in gate current.

5. In a self-biased JFET circuit, the gate bias voltage is actually developed as a voltage
drop across the
a. load resistor.
b. gate resistor.
c. source resistor.
d. channel of the JFET.

VI. CONCLUSION:
ECE 301 184

B. JFET AMPLIFIER AC OPERATION:

I. OBJECTIVE:
 When you have completed this exercise, you will be able to measure voltage gain by
using a JFET amplifier and verify theresults with an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:

To operate a JFET source amplifier as a linear circuit, the gate-source reverse bias must
be set so that an incoming signal does not forward bias the JFET diode junction.
An improper bias level allows an incoming signal to forward bias the gate, causing gate
current to flow.
Gate current causes the high input impedance characteristic to be severely reduced and
leads to amplifier distortion.
The typical JFET amplifier circuit shown in Figure 3-6 is designed to amplify an input
signal with minimum distortion.

In the figure, Cc couples the circuit input signal to the JFET gate and blocks any
external dc voltage from upsetting the circuit self bias.
RG is a very high value because the gate draws negligible bias current. This high
value maintains the high input characteristic of the JFET.
Input signal voltage coupled to the gate produces a variatitm in the JFET depletion
region. This variation follows the input signal.
The drop across the JFET, produced by drain current, follows the variation in the
depletion region, generating an amplified version of the input signal.
In a self biased common source circuit, the output signal voltage is 180 degrees out
of phase with the input signal voltage.
In the figure, RL is the circuit load.
ECE 301 185

The circuit bias is produced by quiescent current flow through the source resistor (Rs).
The quiescent current controls the operating point of the JFET.
One disadvantage of self bias Is that it produces degenerative feedback if Rs is not
bypassed for ac. Degenerative feedback has the effect of reducing circuit gain while increasing
circuit bandwidth.
Voltage gain in a JFET amplifier without feedback Is a function of the load resistor, RL,
and the transconductance (gm) of the JFET.
Voltage gain (Av) = gm X RL
Transconductance is the ratio of a change in drain current (IDS) to a change in
gate voltage (VG) for a given drain-source voltage (VDS) and is stated as follows.

Transconductance (gm) = ∆I DS / ∆VG siemens (for VDS held constant)

IV. PROCEDURE:
1. Locate the JFET AMPLIFIER circuit block on the FET FUNDAMENTALS circuit board.
Connect the circuit shown In Figure 3-7.

2. Set the generator for a sine wave frequency of 1000 Hz. Monitor the gate signal on
channel 1 of the oscilloscope, and adjust the generator amplitude for a 0.3 Vpk-pk
signal.

3. Measure and record the drain voltage on channel 2 of the oscilloscope.

______________________________________________________________________

______________________________________________________________________

4. Based on a comparison of the Input and output signals. does your circuit with an
unbypassed source resistor provide voltage gain?
______________________________________________________________________

______________________________________________________________________

5. Calculate and record the ac circuit voltage gain (Av = Vo/ Vi).
______________________________________________________________________

______________________________________________________________________

6. Is the output signal a true amplified version of the Input signal?

______________________________________________________________________

______________________________________________________________________
ECE 301 186

7. What will be the effect on circuit gain if the source resistor is bypassed with 47-uF
capacitor C2?
______________________________________________________________________

8. Place capacitor C2 Into your test circuit. Again monitor and record the drain voltage.
Calculate and record the circuit gain for the bypassed circuit.
______________________________________________________________________

______________________________________________________________________
9. Has the bypass capacitor produced higher or lower circuit gain as compared to the gain
of the unbypassed circuit?

______________________________________________________________________

______________________________________________________________________

10. Compare the output and input waveforms on your oscilloscope. Is the output signal in
phase with the Input signal?

______________________________________________________________________

______________________________________________________________________

11. Move the channel 2 scope probe to monitor the drop of Rs. Take the bypass capacitor
out of your circuit. Measure and record the peak-to-peak voltage across the source
resistor.
______________________________________________________________________

______________________________________________________________________

12. Calculate and record circuit gm (gm = ∆I DS/∆VG).

NOTE: ∆I DS = VRSpk-pk / RS and ∆ VG =0.3 Vpk-pk.

______________________________________________________________________

______________________________________________________________________

13. Use your step 12 gm value and the test circuit RL values to calculate and record what
the circuit unbypassed gain should be (Av = gm X RL).

______________________________________________________________________

______________________________________________________________________

14. Do your steps 5 and 12 results agree?

______________________________________________________________________

V. EVALUATION:
1. Connect the circuit shown in Figure 3-8. Adjust the signal generator for a 0.3 Vpk-pk, 1
kHz sine wave at the gate of Q1. Place CM switch 17 in the ON position. What is the
effect on circuit gain when load resistor R3 is increased?
a. Circuit gain is increased.
b. Circuit gain is not affected.
c. Circuit gain is decreased.
d. Circuit gain becomes negative.
ECE 301 187

2. Place CM switch 17 in the OFF position and CM switch 18 in the ON position. What is
the effect on circuit gain when load resistor R3 is decreased?
a. Circuit gain is increased.
b. Circuit gain is not affected.
c. Circuit gain is decreased.
d. Circuit gain becomes negative.

3. Refer to Figure 3-8. The purpose of C2 is to

a. control the amount of gate current.
b. increase degenerative feedback.
c. decrease degenerative feedback.
d. bypass the VDD power supply.

4. Refer to Figure 3-8. Increasing the input signal to a high value would result in
a. normal undistorted circuit operation.
b. a higher than normal input impedance.
c. excessive loading of the VDD supply.
d. reduced input impedance and distorted output signal.

5. The value of R1 In Figure 3-8.ls set at 1 M to keep the

a. circuit input impedance below 1000.
b. circuit input impedance high.
c. gate current very low.
d. gate current very high.

VI. CONCLUSION:
ECE 301 188

C. JFET CURRENT SOURCE DC OPERATION:

I. OBJECTIVE:
 To be able to describe the operation of a JFET current source by using dc
measurements.
 To be able to measure load current and draln-to-source voltage by using a JFET
constant current source circuit and verify the results with a multlmeter.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter

III. THEORY:

An ideal constant current source supplies a fixed value of current to a varying load
impedance.
Figure 4-1 illustrates the constant current source principle. In the circuit, the current
(IT) is equal to 10 volts divided by 10 megohms (M), resulting in 1 microamp.

In Figure 4-1, the current is considered to be constant due to the 10M resistor.
Changes in the load resistor have a negligible effect on the circuit current.
The voltage source (Vs) and its series resistor (Rs) generate a near constant current.
The equivalent circuit is shown in Figure 4-2.

To maintain a constant current, Ohm's law states that load ,oltage must increase as
load resistance increases, and load voltage must decrease as load resistance decreases.
A JFET constant current source operates by biasing the JFET into its pinchoff
(saturation) region.
The drain-to-source saturation current characteristic of a JFET determines its
constant current level.

The drain-source voltage of a JFET current source varies inversely with load voltage.
A JFET constant current source uses zero gate bias; the gate and source terminals are
shorted together.
Drain-source voltage (VDS) must exceed the pinch-off voltage (Vp) if the JFET is to
maintain constant current.
ECE 301 189

The impedance of the constant current source will be high relative to its load.
Figure 4-3 shows a typical JFET constant current source. The drain saturation current
(IDS (SAT) ) be constant provided VDS exceeds Vp (pinch-off voltage).

NEW TERMS AND WORDS

 constant current source - a circuit that supplies a fixed current to a varying load
impedance.

 Drain-saturation current , (IDS (SAT) ) – the current of a JFET operated into its
pinch-off region.

As stated, an ideal constant current source supplies a fixed value of current to a

varying load impedance.
In the JFET constant current source of Figure 4-4, the JFET is in series with the
voltage source (Vs) and the load resistor. Vs and the JFET comprise the constant
current source.

Figure 4-5 shows a typical JFET characteristic curve for zero gate bias. Note the
constant region starting with the Vp point.

IDS (mA) Constant current region

Figure 4-5. JFET Characteristic Curve

ECE 301 190

As long as the drain-to-source voltage of Figure 4-4 exceeds the pinch-off voltage (Vp of
Figure 4-5), Q1 Is operating in its constant current region.

Therefore, drain saturation current [IDS(sat)] flows.

Figure 4-6 indicates that a JFET constant current circuit is a series circuit.

In Figure 4-6, the sum of the voltage drops must equal zero. In other words,the sum of
VDS and VRL must equal Vs.
Vs = VDS + VRL
A current flow through the load produces a voltage drop across the load (VRL). This
voltage Is subtracted from the source voltage (Vs). The result appears across the JFET as VDS
(drain-to-source) voltage.
VDS and VRL are inversely related. If VRL increases, then VDS decreases. If VRL
decreases, then VDS increases.
When the value of the load resistor reaches a critical point, the resistor drops excessive
voltage. The remaining VDS voltage is low and the JFET drops out of its constant current
region of operation. At this point, VDS is less than the value of the JFET's pinch-off voltage.

IV. PROCEDURE:
1. Locate the JFET CURRENT SOURCE circuit block on the FET FUNDAMENTALS circuit
board. Connect the circuit shown in Figure 4-7

2. Measure and record the circuit supply voltage (Vs).

Vs = ____________ Vdc

NOTE: In this procedure, you will use the voltage drop of

R1 divided by the value of R1 (100) to determine circuit
current (IT = VRl /R1).

3. Set R2 to its maximum CW position for minimum resistance. Measure VR1, determine
circuit current, and record both values. Measure and record VDS of Q1.

VR1=_________Vdc IT=_________mA VDS=___________Vdc

ECE 301 191

4. Based on your step 3 data, does the sum of VR1 and VDS equal.the circuit supply voltage
(step 2 value of Vs)?
______________________________________________________________________

______________________________________________________________________

5. Complete Table 4-1. Use each value of load resistor given in the table. Follow the
procedure given in step 3.

NOTE: Readings will vary due to JFET characteristic

differences. Your readings will be correct if the circuit
current falls between 4 mA and 16 mA.

Table 4-1

R2 (OHMS) VR1 IT VR2 VDS

SETTING (VDC) (mA) (VDC) (VDC)
MAX CW
_____________________________________________________

500 ______ ______ ______ ______

1000 ______ ______ ______ ______
1500 ______ ______ ______ ______
2000 ______ ______ ______ ______
2500 ______ ______ ______ ______
3000 ______ ______ ______ ______
3500 ______ ______ ______ ______
4000 ______ ______ ______ ______
4500 ______ ______ ______ ______
MAX CCW ______ ______ ______ ______

6. In your test circuit, is the calculated value of IT equal to both the load current and the
JFET drain-to-source current?
______________________________________________________________________

______________________________________________________________________

7. Use the graph in Figure 4-8 to plot the current versus load resistance characteristic
curve of your circuit

IL (mA)

5K 4K 3K 2K 1K 0
(MAX CCW) (MAX CW)
RL (ohms)

Figure 4-8. Graph for load current versus load resistance

8. Based on your data table and your graph, can your circuit provide a constant current for
approximately the first 2500 of load variation?
______________________________________________________________________
ECE 301 192

______________________________________________________________________
9. Based on your data, what is the pinch-off voltage level of your JFET?
Vp = _________ Vdc
10. Based on your plotted data, does the graph approximate the zero biased characteristic
curve of a JFET?
______________________________________________________________________

______________________________________________________________________

11. The constant load current Is the same as what JFET characteristic?

______________________________________________________________________

______________________________________________________________________

12. Your data Indicates that above 2500 of load resistance, the JFET cannot regulate
current. Why not?
______________________________________________________________________

______________________________________________________________________

V. EVALUATION:
1. In a typical JFET constant current source circuit, the device is operated with
a. positive gate bias.
b. zero gate bias.
c. negative gate bias.
d. None of the above.

2. In a JFET constant current source, the voltage distribution can best be described by
which of the following statements?
a. The sum of all voltages must equal the circuit applied voltage.
b. The drain-to-source voltage drop equals the circuit applied voltage plus the load
voltage.
c. The drain-to-source voltage drop equals the circuit applied voltageminus the load
voltage.
d. The drain-to-source voltage must equal the load voltage.

3. In a JFET constant current source circuit, the voltage across the circuit load
a. increases as its resistance increases.
b. remains constant for changes in load resistance.
c. decreases as its resistance increases.
d. equals the JFET gate bias voltage.

4. The JFET of a constant current source circuit is considered to be out of regulation when
the load resistor
a. value is very low.
b. is varying in value.
c. value is very high.
d. voltage drop is varying.

5. Which equation defines the voltage distribution of the JFET constant current source
circuit of Figure 4-97
a. Vs = VDS - VRL
b. VDS = VRL
c. Vs = VDS + VRL - VGS
d. Vs = VDS + VRL

V1. CONCLUSION.
ECE 301 193

CEBU INSTITUTE OF TECHNOLOGY

Cebu City
COLLEGE OF ENGINEERING AND ARCHITECTURE
Electronics Engineering Department

ECE 301
ELECTRONICS 1
( Electronic Devices and Circuits)

EXPERIMENT NO. 13
DUAL GATE MOSFET

______________________________ _______________________
NAME COURSE & YEAR

________________________________ _______________________
GROUP DATE

A. ZERO BIAS CHARATERISTIC OF A MOSFET

I. OBJECTIVE:
 To able to describe the operation of a metal oxide semiconductor field-effect
transistor (MOSFET) by using ac and dc measurements.
 To be able to measure the zero bias characteristics of a MOSFET by using a test
circuit and verify the results with an oscilloscope.

II. APPARATUS AND MATERIALS

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave
III. THEORY:
MOSFET’s are either N-channel or P-channel devices.
A MOSFET can have two gates. Such a device is known as a dual gate MOSFET.
Figure 5-1 shows the schematic symbols of various types of MOSFETS (and JFETs,
for comparison). Each symbol provides the voltage polarities associated with normal
operation of the device.
NOTE: Polarity symbols near gate indicate polarity as follows: (least source drain
voltage) (most source-drain voltage).
DEPLETION MODE
DEVICES

a. n-channel JFET b. p-channel JFET

DEPLETION MODE OR
DEPLETION/ENHANCEMENT
MODE DEVICEST (SUBSTRATE
EXTERNALLY
(SUBSTRATE
AVAILABLE)
INTERNALLY
CONNECTED TO
SOURCE)

DEPLETION/ENHANCEMENT
a. n-channel MOSFET MODE DEVICES b. p-channel MOSFET
ECE 301 194

a. n-channel DUAL-GATE MOSFET b. p-channel DUAL-GATE MOSFET

ENHANCEMENT-
MODE DEVICES

a. n-channel E-MOSFET b. p-channel E-MOSFET

Figure 5-1. Field-effect transistor schematic symbols.

A MOSFET Is also known as an insulated gate FET (IGFET).

In a MOSFET, the gate is physically and electrically insulated from the device channel.
A MOSFET does not draw gate current for either polarity (+ or -) of bias voltage.
When the polarity of the required gate-to-source bias causes a reduction In channel
current, the MOSFET operates In the depletion mode.
Depletion mode devices are considered to be on until they are depleted, or turned off.
When the polarity of the required gate-to-source bias causes an Increase in channel
current, the MOSFET operates in the enhancement mode.
Enhancement mode devices are considered to be off until they are enhanced, or turned
on.
Some MOSFETs can be operated In both the depletion and enhancement modes.
A MOSFET has higher Input Impedance and lower input capacitance than does a
JFET.

MOSFETs usually require some form of gate protection to prevent damage

from static charge.
Figure 5-2 shows the construction of a typical N-channel depletion mode
MOSFET.

SOURCE
DRAIN
CHANNEL

SUBSTRATE

SOURCE
N-CHANNEL
DEPLETION MODE

Figure 5-2. Typical construction of an N-channel depletion mode MOSFET

The gate does not contact the channel due to a layer of silicon dioxide (SiO2), a
glass-like material with excellent Insulation properties.
ECE 301 195

The channel Is continuous from source to drain and is embedded in an oppositely

doped semiconductor base material called the substrate.
In some devices, the substrate Is brought out of the case by a separate lead. In Figure
5-2, the substrate Is internally connected to the source terminal.
Figure 5-3 shows the construction of a typical N-channel enhancement mode
MOSFET.
METAL

SOURCE

DRAIN

INSULATOR
(SiO2

BIAS INDUCED
CHANNEL

SOURCE
SUBSTRATE

N-CHANNEL
ENHANCEMENT

Figure 5-3 Typical construction of an N-channel enhancement mode

The device Is normally off; therefore, there is no complete channel from the source-
to-draln terminal. A voltage across the drain and source terminals will not result in
drain current.
An N-channel induced by the application of a proper charge or bias voltage to the
gate terminal. A positive gate with respect to the source forms an induced channel
and drain current flows.
In Figure 5-3. the dashed lines making up the channel of the schematic representation
signify that the channel Is not complete; the device is normally off until the proper gate
bias Is applied.
The gate does not contact the channel due to a layer of silicon dioxide (SiO2).

NEW TERMS AND WORDS

 Channel - a part of a MOSFET that is continuous from drain to source and is
embedded In oppositely doped substrate material.
 IGFET - insulated gate field-effect transistor.
 Induced channel - current path formed by the application of a bias voltage.
 MOSFET- metal oxide semiconductor field-effect transistor.
 Silicon dioxide -like oxide insulator used between the gate and channel of a
MOSFET device.
 Substrate - major material of a MOSFET. It is oppositely doped to the channel.

IV. PROCEDURE

1. Locate the DUAL GATE MOSFET circuit block on the FET FUNDAMENTALS circuit
board. Connect the circuit shown In Figure 5-4.
ECE 301 196

2. With the signal generator connected to the powered circuit, monitor the generator output
voltage on the oscilloscope.

3. Adjust the generator controls for a 10 Vpk-pk, 100 Hz sine wave.

4. Connect the oscilloscope as shown in Figure 5-4, and .set it up for its X/Y display mode
of operation.

NOTE: Use 1 V/cm for the X input and 50 m V/cm for the
Y input. Use dc coupling for both inputs.

5. Draw the oscilloscope waveform on the graph of Figure 5-5. If you are not sure of the
proper waveform, refer to the answer section.
.

6. Based on your plotted curve, does the MOSFET exhibit an ohmic region at low values of
VDS, as does a JFET?

__________________________________________________________________

__________________________________________________________________

7. Does the MOSFET exhibit a constant current region at VDS values beyond Vp, as does a
JFET?
__________________________________________________________________
__________________________________________________________________

8. Based on your observation of the oscilloscope waveform, does the constant current
region occur in the ohmic region or in the pinch-off saturation region?
ECE 301 197

__________________________________________________________________

__________________________________________________________________
9. Is the change of drain current in the ohmic region based on the magnitude of the drain-
to-source voltage?
__________________________________________________________________

__________________________________________________________________

10. Based on your observation of the oscilloscope waveform, does the drain-to-source
voltage have a significant effect on drain current beyond pinch-off?

__________________________________________________________________

__________________________________________________________________

11. Would you say that the zero bias characteristics of a MOSFET and a JFET are closely
related?
__________________________________________________________________

__________________________________________________________________

V. EVALUATION:
1. Two of the operating regions of a MOSFET are the
a. ohmic and resistive regions.
b. ohmic and pinch-off saturation regions.
c. linear and ohmic regions.
d. non-linear and pinch-off saturation regions.

2. The characteristics of a MOSFET can be compared to a(n)

a. NPN transistor.
b. UJT.
c. reverse biased diode.
d. JFET.

3. Beyond pinch-off saturation, the drain current of a MOSFET

a. exhibits a near constant value.
b. is very dependent on the change of drain-to-source voltage.
c. is reduced to zero or cut-off.
d. is dependent on the resistance value of the ohmic region.

4. For a MOSFET device, zero biased characteristic refers to the

a. amplitude of drain-to-source signal.
b. relationship of drain current to drain voltage for a minus gate bias.
c. relationship of drain current to drain voltage for zero gate bias.
d. None of the above.

5. The MOSFET used in your exercise test circuit conducted drain current while the gates
were connected to circuit common. You conclude that the device is
a. an enhancement mode type.
b. an enhancement/depletion mode type.
c. a depletion mode type.
d. neither enhancement nor depletion type.

VI. CONCLUSION:
ECE 301 198

B. MOSFET MODES OF OPERATION

I. OBJECTIVE:
 To be able to determine the effect of bias on the operating modes of a MOSFET by
using a typical test circuit and verify the results with a multimeter and an oscilloscope.

II. APPARATUS AND MATERIALS:

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave

III. THEORY:

IGFETs (insulated gate MOSFETs) can operate with positive or negative bias
voltages.
Due to the gate-channel electrical isolation. gate current does not flow for either
polarity of gate bias voltage.
The dual gate MOSFET In this experiment can operate in both the depletion and
enhancement modes. In the depletion mode of operation, a negative bias voltage is applied to
the gate with respect to source. In the enhancement mode, a positive bias voltage Is applied
to the gate with respect to source.
Negative and positive bias voltages generate operating curves that are below and above zero
bias drain current characteristic curve.
A dual operating mode MOSFET typically requires low values of bias voltage (less than 2
Vdc).

IV. PROCEDURE:
1. Locate the DUAL GATE MOSFET circuit block on the FET FUNDAMENTALS circuit
board. Connect the circuit shown in Figure 5-6. Do not connect the oscilloscope until
after step 3.

2. Connect your multimeter as indicated in Figure 5-6. Adjust R1 (BIAS ADJUST) for a
reading of OV across R3.

3. While the signal generator is connected Into the test circuit, adjust for a 10 V pk-pk,
1000 Hz sine wave.
ECE 301 199

4. Connect the oscilloscope probes as shown In Figure 5-6. Set up the oscilloscope for
its X/Y display mode of operation.

NOTE: Use 1 V/cm for the X input and 50 mV/cm for the Y input. Use dc
coupling for both inputs

5. Draw the oscilloscope waveform on the graph of Figure 5-7.

NOTE: For this exercise, calibrated voltage and current scales are not required.

6. Does the waveform of your graph look similar to a zero bias JFET characteristic
curve?
______________________________________________________________

______________________________________________________________

7. Adjust the bias voltage (R1 of the test circuit) across R3 for various bias voltages
between -0.8 Vdc and + 0.2 Vdc. Based on your observed waveforms. does the
MOSFET conduct current for positive and negative values of gate bias voltage?

______________________________________________________________

______________________________________________________________

8. As bias voltage becomes more negative. does IDS Increase or decrease?

______________________________________________________________

______________________________________________________________

9. Copy the observed waveform onto your Figure 5-7 graph for bias voltages of +0.2
Vdc, -0.4 Vdc, and -0.8 Vdc. Is the bias polarity positive or negative when the
MOSFET operates In the depletion mode? Why?

______________________________________________________________

______________________________________________________________

10. Is the bias polarity positive or negative when the MOSFET operates In the
enhancement mode? Why?
______________________________________________________________

______________________________________________________________
ECE 301 200

11. What approximate bias voltage Is required to reduce drain current to zero?

______________________________________________________________

______________________________________________________________
12. Change the Y Input V/cm setting from 50 mV/cm to 0.2 V/cm. Adjust R1 for OV bias.
Note the position of your waveform on the oscilloscope.

13. While observing your waveform, vary the R1 bias control from end to end. For the
MOSFET In your test circuit, did a negative bias polarity enhance or deplete the
channel?
______________________________________________________________

______________________________________________________________

14. For the MOSFET In your test circuit, did a positive bias polarity enhance or deplete the
channel?
______________________________________________________________

______________________________________________________________

15. Based on your observation, which mode of MOSFET operation (depletion or

enhancement) provides greater operating range with respect to bias voltage?
______________________________________________________________

______________________________________________________________

16. Which polarity of gate bias voltage produces gate current for the MOSFET?
______________________________________________________________

______________________________________________________________

17. Based on your Figure 5-7 curves, does the IGFET generate an ohmic region or a
constant current region of operation?
______________________________________________________________

______________________________________________________________

V. EVALUATION:

1. The IGFET device used in this exercise was capable of operation as a(n)
a. depletion mode device.
b. enhancement mode device.
c. depletion or enhancement mode device.
d. None of the above.

2. In an IGFET, gate current

a. flows for positive bias voltage.
b. does not flow.
c. flows for negative bias voltage.
d. is equal to drain to source current.

3. When compared to the zero bias characteristic, an increase in drain current

a. means that a channel is enhanced.
b. has no effect on device channel.
c. means that a channel is depleted.
d. will damage the channel.

4. The IGFET does not draw gate current because

a. the gate diode has a high avalanche breakdown voltage.
b. the gate PN junction has a silicon dioxide barrier.
c. bias voltage is always lower than 0.7 Vdc.
d. its gate terminal is isolated from the channel.
ECE 301 201

5. A dual gate MOSFET

a. provides low input impedance.
b. can operate as a single gate device.
c. requires two PN junctions.
d. draws gate current for one of its gates.

VI. CONCLUSION:
ECE 301 202

C. MOSFET VOLTAGE AMPLIFIER

I. OBJECTIVE:
 To be able to determine the ac operating characteristics of a MOSFET amplifier by
using a typical test circuit and verify the results with an oscilloscope.

II. EQUIPMENTS AND APPARATUS:

 F.A.C.E.T. Base Unit
 FET FUNDAMENTALS Circuit Board
 Power supply, 15 Vdc (2 required)
 Multimeter
 Oscilloscope, dual trace
 Generator, sine wave
III. THEORY:
MOSFET amplifiers must be biased correctly In order to stabilize the circuit against
variations In transistors of the same type.
Source resistor self bias provides some correction for variations In characterIstics among
transistors of the same type.
Degenerative ac feedback, which Is caused by source bias, can be reduced or eliminated
by a source resistor bypass capacitor.
Voltage gain In a MOSFET Is a function of gm (transconductance) and the load Impedance.
The MOSFET common source amplifier Inverts the Input signal at Its drain terminal.
Voltage generated across the source resistor of a common source amplifier Is In phase with
the circuit Input signal.

IV. PROCEDURE:
1. Locate the DUAL GATE MOSFET circuit block of the FET FUNDAMENTALS circuit
board. Connect the circuit shown In Figure 5-8. Ensure that the output of the signal
generator (or GENERATOR BUFFER) Is connected to the circuit B Input.

2. Connect channel 1 of your oscilloscope to the signal generator (circuit point B). Adjust
the signal generator for a 1000 Hz, 1 Vpk-pk sine wave.

3. With your multimeter, monitor the drain voltage (with respect to circuit common). Adjust
R1 for a reading of approximately 7.5 Vdc at the drain terminal.

4. With your multimeter, measure and record the gate dc voltage with respect to circuit
common. Observe proper meter polarity. Indicate the voltage polarity for this step.

NOTE: Your result will vary depending on the MOSFET

characteristics in your circuit.
ECE 301 203

VG = ___________Vdc

5. What is the result of steps 3 and 4 with respect to the circuit gain?
______________________________________________________________

______________________________________________________________

6. Monitor the output signal (drain terminal) on channel 2 of the oscilloscope. What is the
ac voltage gain of the circuit?

NOTE: Gain = Vout / Vin (both in peak-to-peak)

Voltage gain = __________

7. Is the circuit output signal in phase or out of phase with the circuit input signal?
______________________________________________________________

______________________________________________________________

8. As you observe the circuit output signal (channel 2 of the oscilloscope), slowly vary R1
from end to end. Based on your observation, what effect does the bias voltage have on
gain and on output signal distortion?
______________________________________________________________

______________________________________________________________

9. Varying R1 alters the MOSFET gate bias voltage. However, the oscilloscope shows an
output voltage signal as the biaj voltage goes from negative to positive volts dc. Does
this mean that the MOSFET can operate in both the depletion and enhancement modes
of operation?

______________________________________________________________

______________________________________________________________

10. Slowly adjust R1 for maximum output voltage on channel 2 of the oscilloscope.
Compare the gate voltage to the gate voltage recorded in step 4. Are they about the
same?
______________________________________________________________

______________________________________________________________

11. Based on your observations, does the maximum gain occur when Q1 drain voltage
equals about half of the circuit supply voltage?
______________________________________________________________

______________________________________________________________

12. Move channel 2 of the oscilloscope to the source terminal. Is this signal degenerative or
regenerative with respect to the input signal of the circuit?

______________________________________________________________

______________________________________________________________

13. With a two-post connector, place C4 into the circuit. What is the effect of this capacitor
on the ac source voltage waveform?
______________________________________________________________

______________________________________________________________

14. With C4 in place, use channel 2 of the oscilloscope to monitor the drain voltage. Has
circuit gain changed?
NOTE: The results of steps 13 and 14 should agree.
ECE 301 204

______________________________________________________________

______________________________________________________________
15. Is the performance of this circuit similar to that of a JFET voltage amplifier?
______________________________________________________________

______________________________________________________________

V. EVALUATION:

1. In a common source MOSFET voltage amplifier, source bias produces

a. Regenerative bias
b. Zero bias
c. Degenerative bias
d. Gate 1 or gate 2 current

2. For the common source MOSFET amplifier, maximum gain

a. Requires a bias voltage to set the device operating point
b. Is not dependent on bias voltage
c. Cannot be developed due to source resistor
d. Requires large input signal levels

3. In a common source amplifier, the output signal is

a. In phase with the circuit input signal
b. A distorted version of the circuit input peak
c. Out of phase with the signal developed across the source resistor
d. None of the above

4. Degenerative source bias voltage

a. Increases circuit gain
b. Has no effect on circuit gain
c. Reduces circuit gain
d. Is maximum when the source resistor is bypassed

5. Excessive bias voltage in a common source amplifier circuit

a. Generates distortion or circuit cut-off, depending on the bias polarity and level
b. Has no effect on circuit operation because the MOSFET can operate depeleted
or enhanced
c. Allows gate current to flow
d. Ensures that gate current does not flow when the input signal is excessive

VI. CONCLUSION: