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Write Levelling On DDR3

DDR3 write and read leveling is used to compensate for unbalanced loading on the memory board that can cause delays in signals arriving at memory devices. For write leveling, the memory controller adjusts the DQS signal in small increments until it is aligned with the clock. For read leveling, the memory controller puts the memory into a mode where it outputs a test pattern, and then adjusts the DQS delay to optimally capture the read data. These compensation values are stored for future memory accesses.

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125 views

Write Levelling On DDR3

DDR3 write and read leveling is used to compensate for unbalanced loading on the memory board that can cause delays in signals arriving at memory devices. For write leveling, the memory controller adjusts the DQS signal in small increments until it is aligned with the clock. For read leveling, the memory controller puts the memory into a mode where it outputs a test pattern, and then adjusts the DQS delay to optimally capture the read data. These compensation values are stored for future memory accesses.

Uploaded by

sarav d
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Understanding DDR3 Write Leveling and

Read Leveling
https://daffy1108.wordpress.com/2010/09/02/understanding-ddr3-write-leveling-and-read-
leveling/

Understanding DDR3 Write Leveling and Read Leveling

DDR3 Write and Read Leveling is to allow some mechanism for the memory controller to
adjust internal DQS to compensate for unbalanced loading on the board for write and read
operations. This will not compensate on a per bit basis, only on a byte or DQS basis.

DDR3 Write Leveling


With DDR3 the memory signals can be allowed to driven to each bank of memory or DIMM on
a fly-by basis. This allows for easier routing on the board and single termination. Below, you
can see that the CMD/ADDR/CLK drive every memory device. Whereas, the DQ/DQM/DQS
drive “each” memory device. This means the CMD/ADDR/CLK are more heavily loaded than
the DQ/DQM/DQS but the actual delay is due to the board routing delays and thus the signals
arrive later at the destination device. See below for the rough timing diagram.

DDR3_FLY_BY_TECHNOLOGY

TIMING DIAGRAM WRITE LEVELING


To compensate for this mismatched loading on the write cycle, the memory controller outputs
a special command to the DDR3 memory devices to put it into a special write leveling state.
See below for MR1 register definition and write leveling bit.

MR1 REGISTER DEFINITION

Basically, the DQS will be used to repeatedly delayed in small increments by the memory
controller and sample the CLK until the rising edge of CLK is detected. During this protocol,
each set of DQ (8 bits) is output with a “0” until the rising edge is detected by the DQS at
which time the DQ will be output with a “1”. The memory controller will detect these “1” on
the DQ bus and then knows the correct DQS compensation to align the DQS and CLK on the
write path. Once all DQS have been adjusted, these compensation values will be stored for
each DQS for future usage. Then the memory controller sends another MRS command to exit
the write level mode.

DDR3 Read Leveling

As DDR3 Write Leveling manages the DQS/DQ on write data, the DDR3 Read Leveling
manages the DQS/DQ on read data. DDR3 Read Leveling is to compensate the imbalanced
loading on the read path. First the memory controller puts the DDR3 memory devices into a
special mode by writing to the MR3 register MPR bit. See MR3 defintion below for details of
the MR3 register. This puts the DDR3 memory devices into the read leveling mode which
outputs a stream of “01010101” in a burst length of 8 bits with a regular memory read
command. Imagine this as a read training sequence. The diagram below shows the MPR
bypassing the memory array to output the known data stream onto the DQ bus. Since the
memory controller knows that data stream is consistently outputting on the DQ bus, it will
adjust the internal DQS delay mechanisms on the read data path to create a proper window
of the best capture window for the DQ using DQS. Once these internal compensations are
created for each DQS, the values will be stored for future usage. And MR3 is set back to
normal DDR3 operational mode.
MR3 REGISTER DEFINITION

READ LEVELING

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