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A Differential Double Pass Transistor Logic Unit

Article  in  International Journal of Computer Science Issues · March 2012

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IJCSI International Journal of Computer Science Issues, Vol. 9, Issue 2, No 1, March 2012
ISSN (Online): 1694-0814
www.IJCSI.org 351

A Differential Double Pass Transistor Logic Unit

Chiraz Khedhiri1, Mouna Karmani1 & Belgacem Hamdi1, 2
1
Electronic & Microelectronics Laboratory.
Monastir – Tunisia

2
ISSAT, Sousse – Tunisia

Abstract There are two main pass-transistor circuit styles: those that
In this paper we present a new differential logic unit with use NMOS only pass-transistor circuits, like CPL [4], and
duplicated functional outputs. The logic functions as well as their those that use both NMOS and PMOS pass-transistors,
inverses are implemented within a single Logic Unit (LU) cell. like DPL [5] and DVL [6].
The hardware overhead for the implementation of the proposed
LU is lower than the hardware overhead required for standard LU
implemented with standard CMOS logic style. This new
Recently, several researchers have attempted to use
implementation is attractive as fewer transistors are required to Complementary pass transistor logic (CPL) to realize
implement important logic functions. The proposed differential static and high performance designs in different digital
logic unit can perform 8 Boolean logical operations by using only systems [4–7].
16 transistors.
Spice simulations using a 32nm technology was utilized to However, since only NMOS transistors are used in CPL
evaluate the performance of the proposed circuit. gates, the voltage swing at the end of a pass transistor
Keywords: differential logic unit, double pass transistor logic, network has a swing from 0 to VDD - VTH; therefore PMOS
CMOS technology. transistors at the following static gates are not completely
off resulting in static power dissipation.
1. Introduction This problem is usually solved by a PMOS level restorer
transistor to pull up the node to VDD. The level restorer
Conventional static CMOS has been a technique of
adds hysteresis to the gate and degrades the performance.
choice in most processor design [1]. Alternatively,
Also, the delay of pass transistor networks increases
static pass transistor circuits have also been
quadratically with the number of stages and as a result,
suggested for low-power applications [2].
some intermediate buffers should be used to make strong
VDD and ground. All these problems arise from the fact
Indeed, designing high-speed low-power circuits with
that NMOS transistors can not pass VDD faithfully to the
CMOS technology has been a major research problem for
other side. The solution is using a complementary PMOS
many years. Several logic families have been proposed
transistor in parallel with NMOS to generate a strong VDD
and used to improve circuit performance beyond that of
at the output [8]. This structure is double pass transistor
conventional static CMOS family.
logic (DPL).
In addition, due to technology scaling and the increasing
DPL uses both PMOS and NMOS devices in the pass-
number of transistors on chip, the performance of static
transistor network to avoid non full swing problems [9].
CMOS circuits comes at substantial area/power dissipation
Double pass-transistor logic is shown to improve circuit
costs that may be critical, especially for portable
performance at reduced supply voltage. Its symmetrical
appliances. New logic families that address the power and
arrangement and double-transmission characteristics
performance challenges must be therefore, explored [3].
improve the gate speed without increasing the input
capacitance [5].
The Pass-Transistor Logic (PTL) is a better way to
implement circuits designed for low power applications.
In this paper, we propose a differential logic unit
The advantage is that one pass-transistor network (either
implemented in CMOS double pass transistor logic. The
PMOS or NMOS) is sufficient to implement the logic
proposed logic unit (LU) is low power and small number
function, which results in smaller number of transistors
of transistors design. It performs 8 logic functions with
and smaller input load.
only 16 transistors.

Copyright (c) 2012 International Journal of Computer Science Issues. All Rights Reserved.
IJCSI International Journal of Computer Science Issues, Vol. 9, Issue 2, No 1, March 2012
ISSN (Online): 1694-0814
www.IJCSI.org 352

The paper is organized as follows. Section II describes the B B

proposed design. In section III, we present the simulation
results. Conclusions are given in section VI. S0

2. Proposed Design A A
O ut A O ut
ALU stands for the Arithmetic logic unit and it is an
internal part of the processor which is used for all the B B
mathematical and logical operations. The operations of
the ALU include arithmetic operations such as addition, S1
subtraction, multiplication and division of the binary
values. It also, performs some logical operations such as
AND, OR and XOR, integer arithmetic operations and Bit- A A
shifting operations etc. ALU is the fundamental building
block of the processor. Fig. 1. The proposed differential logic unit

Today, modern computers contain very complex ALU for Fig. 1 shows a differential logic unit which consists of
performing the complex calculations and logical double pass transistors and inverter gates. Inputs A, S0
operations inside the computer. The data or the operands and S1 control the “ON” and “OFF” switching of the pass
are the input of the ALU and it generates the output as the transistors.
result of the computation.
Such obtained logic is differential as every variable is
In some of the computers the ALU is divided into two represented in its true and complement form.
units: Arithmetic unit and Logic unit. Output inverters are added to ensure the drivability and
outputs restoration.
Logic units are the building blocks of many important
computational operations likes arithmetic, multiplexer- The functions performed by the circuit of Fig. 1 are
demultiplexer, parity checker, sum generator, etc... resumed in table I.
Multifunctional logic operation is very much essential in
this respect. Table 1 : The Logic Unit truth table

In this paper, a differential logic unit is proposed that can Control Logic operation
perform 8 Boolean logical operations by using only 16 SO S1 Out Outb
transistors. The circuit is implemented using the double 0 0 XOR XNOR
pass transistor logic (DPL). 0 1 OR NOR
1 0 NAND AND
The bit slice of the proposed differential logic unit
performing XOR, XNOR OR, NOR, AND, NAND, VDD 1 1 0 (VSS) 1 (VDD)
and VSS is given in Fig. 1. It performs: XOR/XNOR for
(SO,S1) = (0, 0) , OR/NOR for (SO,S1) = (0, 1) , The logic functions as well as their inverses are
NAND/AND for (SO,S1) = (1, 0) and VDD/VSS for implemented within a single LU cell which is a
(SO,S1) = (1, 1). multiplexer (Fig. 2).
x
Sel

x 0
S el out
Out
y 1

Fig. 2. The basic logic unit cell

Copyright (c) 2012 International Journal of Computer Science Issues. All Rights Reserved.
IJCSI International Journal of Computer Science Issues, Vol. 9, Issue 2, No 1, March 2012
ISSN (Online): 1694-0814
www.IJCSI.org 353

A circuit that generates an output that exactly reflects state

of one of a number of data inputs, based on value of one
or more control inputs is called “multiplexer” [10].

Multiplexer is an important part in implementation of

signal control systems and memory circuits, since it allows
us to choose one of the inputs and transfer it to the output.
The functionality of multiplexer is shown in (1). x and y
are the two inputs and Sel is used to select one between
the two inputs [11].

Out  x .Sel  y .Sel (1)

The proposed logic unit is implemented using the double Fig. 3. Layout of the logic unit in CMOS 32nm Double Pass Transistor
Logic
pass transistor logic. This structure uses only 16
transistors.
Fig. 4, 5, 6 and 7 illustrates a SPICE simulation of the
circuit of Fig. 3.
3. Simulation Results
Before implementing the whole circuit, a gate-level A
schematic in DSCH3 is generated. DSCH3 program is a
B
logic editor and simulator used to validate the architecture
of logical circuit, before microelectronics started. It S0
provides user friendly environment for hierarchical logic
design and fast simulation with delay analysis, which S1
allows design and validation of complex logic structures.
out
After successful simulation we implemented the above
designs of the logic unit with different components using out
Microwind 3.1 layout tool [12] for its ease of use and
availability. Fig. 4. The dual rail XOR/XNOR function for (S0, S1) = (0,0)

The differential logic unit of the Fig. 1 is implemented in The above simulation show that when (SO,S1) = (0,0), out
full-custom 32nm CMOS technology at 0.8V power
= XOR and out = XNOR.
supply [12]. SPICE simulations of the circuit extracted
from the layout, including parasitic, are used to
demonstrate that this circuit has an acceptable electrical A
behavior. The layout of the differential logic unit with the
two restoring inverters is as shown in Fig.3. It occupies an B
area of 0.93×1.185µm2.
S0

S1

out

out

Fig. 5. The dual rail OR/NOR function for (S0, S1) = (0,1)

When (SO,S1) = (0,1), out = OR and out = NOR.

Copyright (c) 2012 International Journal of Computer Science Issues. All Rights Reserved.
IJCSI International Journal of Computer Science Issues, Vol. 9, Issue 2, No 1, March 2012
ISSN (Online): 1694-0814
www.IJCSI.org 354

evaluate the usefulness of the proposed scheme, one bit

A Logic Unit was implemented and simulated. The proposed
Logic Unit can operate at low voltages, yet giving quite a
B
good speed.
S0
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