Laboratory 1

Inverter Design
Manual
 Inverter Design Manual Outline

• Basic (For Beginner in Xstart)

• Part 1: Schematic
• Part 2: Symbol
• Part 3: Test Bench
• Part 4: Layout
• Part 5: Layout Verification
• Part 6: Post Simulation

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Basic: Run Xstart

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Basic: Run cdesigner
You can directly run cdesigner if
your library is just on the home
folder of your account. In this
case, it is in the TSMC18UM
folder.

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 Create New Library

Right Click on the Libraries Column. Select

New. Then Name a New Library.

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 Add Technology to the Library

Edit the Technology as shown. Attach the

tsmc18rf technology to the Library.

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 Add New Cell Category

Right Click.

Right Click on the Cell Categories.

Create a new Cell Category.
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 Part 1: Schematic
Add New Cell and View

Right Click.

Select.

Right Click on the Views and add a New

Cellview. Select a view name and editor.
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 Add Instance from Library
Click i

Click I to add instance. Select the

Library.
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Choose PMOS Cell from tsmc18rf
Library

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Choose NMOS Cell from tsmc18rf
Library

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Choose GND Cell from analog Library

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Choose VDD Cell from analog Library

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Adjust the sizes of the MOS Devices
Click Q to view the
Property Window

Adjust L, M and
Multiplier according
to design.

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Adjust the sizes of the MOS Devices
Click Q to view the
Property Window

Adjust L and M
according to design.

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 Complete connections.

Click W to add
wire.

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 Add PINS for input.

Right Click to
Rotate Pin.

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 Add PINS for output.

Right Click to
Rotate Pin.

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Click Y to create a symbol from the
schematic.

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 Part 2: Create Symbol

Delete unnecessary
shapes.

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Rename Symbol

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Draw the shape of the symbol

Select the poly

line.

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Draw the shape of the symbol

Select the circle.

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Draw the shape of the symbol

Adjust by
Moving. Click M.

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Save the Symbol

Click Ctrl + S.

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Part 3: Test Bench
Create another cell for the Test Bench

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Add device.

Click i. Then Select the Library

where your inverter design is
located. Select desired cell.

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 Inverter Test Bench
Add instances and construct the circuit. Click Q to edit
properties.

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 Test Bench Simulation

Click Tools on the Menu Bar

and select SAE.

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 Add Model File
SAE window pop up. Click M to add Model File.

To open model file.

Path:
account/TSMC0180UM/models/hspice
Select rf018.l

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Select Process Corner TT

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 Add Analyses
Click A to add. For Inverter, .dc and and .tran analyses.

Edit parameters for desired

analysis.
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SAE Set-Up

Add Nets by clicking and

selecting the corresponding
wire on the schematic.

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Run Simulation
Ctrl + S for shortcut.

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 WaveView Window
You can Click File on the Menu and then open a waveform.
Click Ctrl + O to open.

Select the generated

hspice.tr0

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 Wave Form

Output Waveform

Input Waveform

Click Ctrl+H to open

Output View Window.

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 Measurement Tool
Select the desired measurement tool. For Inverter, select the Rise/Fall Time.

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Input Vs Output Rise/Fall Time

Drag the Measuring tool to

desired wave.

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 Update Waveform
You can always edit the sizes of the MOS Devices if you are not satisfied with the output. Just
simulate again and update the waveform by clicking the green arrow then Apply all changes.
No need to close the WaveView Window. Else, proceed to the Layout.

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 Part 4: Layout
Create the layout view in the same cell with the schematic and symbol.

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 Layout Tips!
• Be familiar with the shortcut keys and minima Rule.
Practice a lot!
• Select Assist on the SmartDRD option. This will guide you
for the minimum rule.
• Always have 45° (diagonal) cut on metal corners and
when there is a change in metal width or height.
• Schematic: MOS W = Layout: Diffusion H (Height)
• Schematic: MOS L = Layout: Poly W (Width)
• Always Check DRC even if you’re halfway your layout
process so you can check minor errors ahead. Refer to
DRC Verification Part of this manual for the DRC settings.
• On this manual, refer to the property window for the
layer and size.

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 PMOS:
Diffusion Layer

Click R to create a rectangle. Don’t

mind the size yet you can edit it. Refer
to the next slide.

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Diffusion

As mentioned, Diffusion Height is the MOS W.

Don’t mind the width for the mean time.

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Polysilicon Layer

As mentioned, Poly Width is the MOS L. Extend the

height width 0.22um compared to the Diff height.

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Contacts

Add Contact Layers with the minima rule as

shown.

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Metal 1 Layer

Add Metal 1 Layer with the minima rule as

shown.

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Metal 1 Layer

Extend Metal 1 Layer covering all the contacts.

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Multiples

In case of having multiples, select the

poly, contacts and metal 1 then copy
(Click C ) and align in the same
diffusion. Extend the diffusion by
adjusting the width or by stretching
(Click S).

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Add Label

You can add text to label.

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Add Poly Dummy

You can add Poly Dummy Layers.

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Polysilicon Gate

On the polysilicon gate layer, extend or add a poly

rectangle. Then chop (Click Ctrl+C) to form 45° diagonal
when shifting from wider layer to smaller width.

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Polysilicon

Chopped Polysilicon. Delete the

unnecessary part.

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Metal 1 – Poly Contact

Add the Metal 1-Poly Contacts to the Gate.

Make sure the Poly is attached or overlapped.

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 NMOS:
Diffusion Layer

Follow the same procedure with the

PMOS.

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 NMOS
Label

Label the Drain and Source

connection.

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 NMOS

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NMOS Gate Connection

Connect the gates by adding metal 1

layer.

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PMOS Gate Connection

Connect the gates by adding metal 1

layer.

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Gates Connection

Connect the PMOS and NMOS gates by

adding metal 1-metal 2 contact then
connect with metal 2 layer.

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 Routing

Route metals to connect the PMOS and

NMOS Device based on the schematic
connections.

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PMOS: P Implant Layer

Add P implant Layer to the PMOS.

Observe Minima Rule.

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NMOS: N Implant Layer

Add N implant Layer to the NMOS.

Observe Minima Rule.

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Inverter Design

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Guard Ring

You can create guard ring manually or

using via. Just adjust the Column and
Row number.

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Guard Ring

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VDD to Source Connection

The guard ring of the PMOS serves as

the VDD. Connect the Source to the
Guard ring.

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PMOS with Guard Ring

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PMOS: NWELL Layer

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NMOS with Guard Ring

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NMOS Source to GND

The guard ring of the NMOS serves as

the GND. Connect the Source to the
Guard ring.

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Guard Ring

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Add Metal Route for the Input and
Output Pins

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Add PINS

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 Vin Pin

Make sure metal pin is the same with

the layer. Name is the same with the
schematic.

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Vout Pin

Make sure metal pin is the same with

the layer. Name is the same with the
schematic.

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 Vdd Pin

Make sure metal pin is the same with

the layer. Name is the same with the
schematic.

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 Gnd Pin

Make sure metal pin is the same with

the layer. Name is the same with the
schematic.

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Inverter Design

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 Part 5: Verification
DRC Verification
This is to verify that the design has complied with the minima rule.

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DRC Setup

Add Runset file.

Path: /home/documents/TSMC_018um/hercules/drc
Then Click OK.

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DRC Result

You must only this kind of error on the DRC Errors

Tab. This is just fine for this Laboratory.

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 LVS Verification
This is to verify that the layout design matches the schematic design.

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LVS Setup P.1

Add Runset file.

Path: /home/documents/TSMC_018um/hercules/lvs

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LVS Setup P.2

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LVS Setup P.3

Select layer map.

Path: account/TSMC018UM/tsmc18rf/
Then RUN LVS.

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 LVS Result
This is verifies that the layout design matches the schematic design.
If not, debug the errors.

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 LPE Verification
This is to verify whether the parasitic value of the layout is tolerable that it does not affect
the output of the device.

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LPE Setup P.1

Select Runset file.

Path: /home/documents/TSMC_018um/hercules/starrc

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LPE Setup P.2

Select MilkyWay XTR View. Go to the lvs folder from the

LVS verification.
Path: /home/account/TSMC018UM/Inverter/hercules_lvs

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LPE Setup P.3

Select Mapping file.

Path: /home/documents/TSMC_018um/hercules/starrc

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LPE Setup P.4

Select GRD file.

Path: /home/documents/TSMC_018um/hercules/starrc

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LPE Setup P.5

Select Output Runset Path.

Path: /home/account/TSMC018UM/EE270/Lab1_Inverter/
Create new Folder Output.

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LPE Setup P.6

On the Output Folder, create filename, output.spf

then save and Run LPE.

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 LPE Result
Refer to the Custom Designer Console of This is verifies that the layout design has no errors
in terms of the parasitic extraction.

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 LPE Result
LPE output can be viewed on gedit. Go back to xtart terminal window, type gedit & then
Click Enter. It will open a new window of gedit. Click Open to open the file: output.spf.

1 2

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HSPICE Generated Output

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 Part 6: Post Simulation

Open on gedit the pre-simulation hspice code on the

simulation folder.
Path: /home/account/simulation/EE270/Inverter_TestBench/
Schematic/HSPICE/nominal/netlist
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 Post Simulation P.1

Open on gedit the post-simulation hspice code on the output

folder.
Path:
/home/account/TSMC018UM/EE270/Lab1_Inverter/output

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 Post Simulation P.2

Copy all the output.spf code to a new document or you can

simply save as a new document where the file is saved as
an .sp file. Take note in which folder you saved the file.

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 Post Simulation P.3

From the input.sp, copy the highlighted

code to the post.sp file just below the
comments line or the line before the
the Subckt.

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 Post Simulation P.4

From the input.sp, copy the highlighted code to the post.sp file at the bottom part or
after the Subckt code.
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 Post Simulation P.5

In the post.sp file, rename the Inverter pins in sequenced with the pinning of the
Subckt.
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 Post Simulation P.6

Click Replace. Rename the <space>P<space>

with <space>PCH<space> and
<space>N<space> with <space>NCH<space>

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 Post Simulation P.7
Go back to terminal, go to the folder
where the post.sp file is located.
Run Hspice.
Type hspice filename.sp then Enter.

If there are no
errors, job is
concluded.
Type wv & then a
waveview window
pops up.

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Post Simulation: Waveform

Open the File

filename.tr0. Click Ctrl+O
to open waveform files
window.

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 Post Simulation: Waveform

Click the vin and vout

to open waveforms.

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 Pre-Simulation: Waveform

Open the pre-sim file. Path:

/home/account/simulation/EE270/
Inverter_TestBench/schematic/HSPICE/nominal/results
Select the hspice.tr0 file.

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Measurement Tool

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 Pre-Sim vs Post-Sim

It is good if your post-simulation is equal to or better than the pre-simulation result. If not,
you can check your layout to improve your output.
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 Done!

Congratulations!

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