TECH 158 - Digital Electronics (winter 2020)

Lab #11: Digital-to-Analog and Analog-to-Digital Converter

Part A: DUE DATE & TIME: Wed. April 15, 2020

OBJECTIVES: 12:00 NOON
 Understand the operation of a R/2R ladder DAC Submission by Email
 Design an R/2R ladder DAC with a 4-bit binary counter or Course Message

MATERIALS:
[1] LM741 Op Amp [1] 74LS93 binary counter [1] Resistors package

INFORMATION:
Many physical quantities in nature are stored and processed in the digital domain by digital systems such as a
microcontroller. The final result of the signal processing is then converted back to analog. This is when a digital-to-analog
converter is required. Common DAC types include binary-weighted DAC’s and R/2R ladder DAC’s. In the former type,
resistors are used to set a proper weighting factor for each bit of a binary input. Since each bit is connected to a resistor
of different resistance, a high resolution DAC requires resistors of various resistors, which place a severe limitation in IC
fabrication. The R/2R ladder type is more suitable, since it uses only two different resistors. In this lab, we are going to
build an R/2R ladder DAC and test its functionality by using a 4-bit binary counter.
An R/2R ladder DAC consists of an operation amplifier and an R/2R ladder as shown in the figure below. It is easy to show
that the total resistance of the ladder is R, and the reference current (Iref) becomes Vref/R. Iref is divided into each rung of
the ladder depending on the binary input: if D3 is 1, the current in the first rung (I3) is Iref/2; if D3 = 0 then I3 = 0. Similarly, if
D2 = 1 then I2 = Iref/4. If D1 = 1 then I1 = Iref/8. I0 = Iref/16 in case when D0 = 1. Current from each rung is summed, and the
total current flows through the feedback resistor, which is 2R. Then, the output voltage is given by
𝐷3 𝐷2 𝐷1 𝐷0 𝐷3 𝐷2 𝐷1 𝐷0
𝑉𝑜𝑢𝑡 = −2𝑅 ∙ 𝐼𝑟𝑒𝑓 ∙ ( + + + ) = −2𝑉𝑟𝑒𝑓 ∙ ( + + + )
2 4 8 16 2 4 8 16
𝑉𝑟𝑒𝑓
= − (8 ∗ 𝐷3 + 4 ∗ 𝐷2 + 2 ∗ 𝐷1 + 𝐷0 )
8
𝑉𝑟𝑒𝑓
∴ 𝑉𝑜𝑢𝑡 = − (𝑑𝑒𝑐𝑖𝑚𝑎𝑙 𝑒𝑞𝑢𝑖𝑣𝑒𝑛𝑡 𝑜𝑓 𝑡ℎ𝑒 𝑑𝑖𝑔𝑖𝑡𝑎𝑙 𝑖𝑛𝑝𝑢𝑡)
8

In this lab, we are going to use an LM741 Op Amp, three 10 k resistors, and six 20 k resistors to build an R/2R ladder
DAC. To provide a binary input, we are going to use a 4-bit binary counter. As the counter counts from 0 to 15, the output
voltage should increases in steps. As the counter output increases from 0 to 15, the negative output analog voltage is
expected to drop to its minimum value. Thus, the analog output voltage should display a saw-tooth pattern with a saw-
tooth consists of a 16 step staircase.

1
TECH 158 - Digital Electronics (winter 2020)
Lab #11: Digital-to-Analog and Analog-to-Digital Converter

Lab Assignments:
1. Calculate Vout in the circuit shown below for Ri of 10 k and RF of 50 k. The gain (Av) is defined by Vout/Vin. What is the
gain of the circuit? Show your work!

Vout = ______________ V

Av = ________________

2. Shown below is an R/2R ladder DAC constructed by using an LM741 op-amp and a 74LS93 binary counter.

2.1 Based on the DAC circuit and the equations, calculate the output voltage (Vout) for the following digital inputs:

2.1.1 D3D2D1D0 = 1001

Vout =

2.1.2 D3D2D1D0 = 0011

Vout =
2
TECH 158 - Digital Electronics (winter 2020)
Lab #11: Digital-to-Analog and Analog-to-Digital Converter

2.2 The binary counter operates at 5 V, whereas the op-amp requires two power supplies: +12 V and – 12 V. Thus, the
DC power supply in the lab should be used in the series mode to connect channel 1 and channel 2 in series. Explain how
you can supply +12 V, -12 V, +5 V, GND to your circuit. (Hint: As you put the power supply to the series mode, the +
terminal of Channel 2 (CH2) is internally connected to the – terminal of Channel 1 (CH1). Note that all three power sources
(+12 V, -12 V, and +5 V) should share a commond GND with your circuit. You will need five alligator-to-banana test leads
in total.)

3
TECH 158 - Digital Electronics (winter 2020)
Lab #11: Digital-to-Analog and Analog-to-Digital Converter

Part B:
OBJECTIVES:
 Understand the operation of a ADC
 Build, troubleshoot, and verify 8-bit ADC in both single and continuous operation mode

MATERIALS:
[1] ADC0804 8-bit analog-to-digital converter

INFORMATION:
Most physical quantities in nature are stored and processed in the digital domain by digital systems such as a
microcontroller. This lab is about conversion of an analog signal into a digital signal. Among many algorithms for analog-
to-digital conversion, the successive-approximation and sigma-delta modulation are most commonly used. In this lab, we
will work with an 8-bit ADC, which is based on successive-approximation algorithm.
Major components of a successive-approximation type ADC include a successive-approximation register (SAR), a digital-
to-analog converter (DAC), and a comparator. The basic operation principle is as follows:

1. Conversion starts by resetting SAR to 0.

2. Test each bit of SAR starting from the MSB
1) Set the bit to logic HIGH.
2) The SAR output (a binary number) is converted to an analog value by the DAC.
3) The comparator compares the analog output from the DAC (VDAC) to the analog input (Vin).
4) If Vin is smaller than VDAC, then clear the bit to 0; else leave the bit set.
* Once modified, test of this bit is complete. This bit should remain unchanged after its test.
3. Repeat step 2 until the LSB of the SAR is tested.
4. Once the LSB is tested, conversion is done, and SAR holds the binary equivalent of Vin.

The figure on the right shows the pin diagram of ADC0804. Conversion is initiated by
momentarily pulling both CS’ and WR’ LOW. Typically, CS’ is permanently grounded, and a
logic LOW is applied to WR’. A reference voltage can be connected to Vref/2 input or it can
be left unconnected, in which case the reference voltage is VCC. Differential analog inputs are
connected to Vin(+) and Vin(-). In case of single-ended applications as is our case, the input
signal is connected to Vin(+), and Vin(-) is grounded. A high-to-low transition on INTR’ output
indicates the end of conversion. It is called INTR (interrupt), for it is typically used as an
interrupt request input to a microprocessor so that it can run an interrupt service routine
(ISR), which reads the digital output from the ADC and subsequently processes it. INTR’ can
also be connected to WR’ for continuous conversion. The chip has two ground pins, namely, AGND and DGDND. This is to
reduce the effects of noise in the digital part of the circuit on the analog part, which is much more vulnerable to noise.

4
TECH 158 - Digital Electronics (winter 2020)
Lab #11: Digital-to-Analog and Analog-to-Digital Converter

When we discussed 4-bit R/2R ladder DAC, we learnt that the analog output (VOUT) is given by

decimal value of digital input

VOUT  (Vref  )
2 n 1
where n is the number of bits. In case of ADC’s, we can modify the above equation to relate the analog Input (V IN) to the
decimal value of a digital output by noting that the DAC inside an ADC has an op-amp circuit whose voltage gain is unity.
Thus, it is given by:

V IN
decimal value of digitaloutput
input or decimal value of digital output = ∙ 2n
VIN  (Vref  n
) Vref
2

Lab Assignments:
(Optional) Write a C program to simulate a 4-bit successive-approximation ADC. The program does the following:

- display a message asking for an analog voltage (VIN): 0 V ≤ VIN < 5 V.

- use either a ‘for’ or a ‘while’ loop to describe the successive-approximation process.

- assume a 4-bit R/2R ladder DAC with the voltage gain of 1; Vref = 5 V, and the analog output (Vout) is given by

decimal value of digital input

VOUT  (Vref  )
2 nn 1 where n is the number of bits.

- print the analog input to and the digital output from the ADC: try at least 5 different input voltages.

1. Use the equation above (eq. in the 3rd green box) to calculate the decimal value of the digital output for each input
voltage, Vin(+), in the table below. Record the calculated decimal value in binary format in the table. Vref = 5V. If the
calculated decimal value is a fraction, ignore digits below the decimal point.

Vin(+) Q7Q6Q5Q4 Q3Q2Q1Q0 Vin(+) Q7Q6Q5Q4 Q3Q2Q1Q0

(V) (calculated) (V) (calculated)
0.0 3.0
0.5 3.5
1.0 4.0
1.5 4.5
2.0 4.9
2.5

Name: Student No.: