TPS548A29

SLVSE78D – MARCH 2020 – REVISED JULY 2021

TPS548A29 2.7-V to 16-V Input, 15-A Synchronous Buck Converter

With Remote Sense, 4.5-V Internal LDO and Hiccup Current Limit

1 Features 2 Applications
• 4-V to 16-V input range up to 15-A without external • Rack servers and blade servers
bias • Hardware accelerator and add-in cards
• 3-V to 16-V input range up to 12-A without external • Data center switches
bias • Industrial PC
• 2.7-V to 16-V input range up to 15 A with external
bias ranging from 4.75 V to 5.3 V
3 Description
• Output voltage range: 0.6 V to 5.5 V The TPS548A29 device is a small high-efficiency
• Integrated 8.4-mΩ and 2.6-mΩ MOSFETs synchronous buck converter with an adaptive on-time
• D-CAP3™ with ultra fast load-step response D-CAP3 control mode. Since external compensation
• Supports all ceramic output capacitors is not required, the device is easy to use and requires
• Differential remote sense with 0.6-V ±1% VREF for few external components. The device is well-suited for
–40°C to +125°C junction temperature space-constrained data center applications.
• Auto-skip Eco-mode™ for high light-load efficiency
The TPS548A29 device has differential remote
• Programmable current limit with RTRIP
sense, high-performance integrated MOSFETs, and
• Pin-selectable switching frequency: 600 kHz, 800
an accurate ±1%, 0.6-V reference over the full
kHz, 1 MHz
operating junction temperature range. The device
• Programmable soft-start time
features fast load-transient response, accurate load
• External reference input for tracking
regulation and line regulation, Skip-mode or FCCM
• Prebiased startup capability
operation, and programmable soft-start.
• Open-drain power-good output
• Hiccup for OC and UV faults, latch-off for OV Fault The TPS548A29 device is a lead-free device. It is fully
• 4-mm × 3-mm, 21-pin QFN package RoHS compliant without exemption.
• Pin compatible with 12-A TPS54JA20
Device Information
• Fully RoHS compliant without exemption
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
TPS548A29 VQFN-HR (21) 4.00 mm × 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
100
VIN
10 VIN BOOT 1 95
21 VIN 90
VOUT
8 EN SW 20 85
TPS548A29 80
Efficiency (%)

75
19 VCC Vosns+
70
FB 7 Vout = 0.6 V
9 PGOOD 65 Vout = 1.0 V
Vin = 12 V
60 800 kHz Vout = 1.2 V
4 MODE Vosns- VCC = Int Vout = 1.8 V
55 Vout = 2.5 V
800 nH
VSNS- 6 50 FCCM Vout = 3.3 V
3 TRIP
Vout = 5.0 V
SS/ 45
5
2 AGND REFIN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PGND Net-tie Output Current (A) D034

Efficiency Graph

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 25
2 Applications..................................................................... 1 8.1 Application Information............................................. 25
3 Description.......................................................................1 8.2 Typical Application.................................................... 25
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................38
5 Pin Configuration and Functions...................................3 10 Layout...........................................................................39
6 Specifications.................................................................. 5 10.1 Layout Guidelines................................................... 39
6.1 Absolute Maximum Ratings........................................ 5 10.2 Layout Example...................................................... 40
6.2 ESD Ratings............................................................... 5 11 Device and Documentation Support..........................42
6.3 Recommended Operating Conditions.........................5 11.1 Documentation Support.......................................... 42
6.4 Thermal Information ...................................................6 11.2 Receiving Notification of Documentation Updates.. 42
6.5 Electrical Characteristics.............................................6 11.3 Support Resources................................................. 42
6.6 Typical Characteristics................................................ 9 11.4 Trademarks............................................................. 42
7 Detailed Description......................................................12 11.5 Electrostatic Discharge Caution.............................. 42
7.1 Overview................................................................... 12 11.6 Glossary.................................................................. 42
7.2 Functional Block Diagram......................................... 12 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................13 Information.................................................................... 43
7.4 Device Functional Modes..........................................21

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (June 2020) to Revision D (July 2021) Page
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
• Added links to applications................................................................................................................................. 1
• VIN-SW: Transient changed from 10ns to 20ns, Changed Min from -1.5V to -4V..............................................5
• VIN-PGND: Transient changed from 10ns to 20ns.............................................................................................5
• Updated Switching Frequency minimum and maximum values......................................................................... 6
• Corrected VINTREF vs Junction Temperature ......................................................................................................9
• Clarified how a device enters into a fault, and how the fault is cleared ........................................................... 20
• Fixed cross references for Equation 10 through Equation 17 and corrected equation errors.......................... 27
• Added RTRIP value to paragraph.......................................................................................................................27
• Updated typical valley current in the text from 16.8 A to 13.66 A to match Equation 14 ................................. 27
• Added "Round up to use a valley current limit of 15 A."................................................................................... 27
• Updated Switching Frequency vs Output Voltage graph.................................................................................. 32

Changes from Revision B (June 2020) to Revision C (June 2020) Page

• Deleted redundant LDO specification................................................................................................................. 6

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5 Pin Configuration and Functions

VIN SW SW VIN
21 20 20 21
BOOT 1 19 VCC VCC 19 1 BOOT

AGND 2 18 PGND PGND 18 2 AGND

TRIP 3 17 PGND PGND 17 3 TRIP

MODE 4 16 PGND PGND 16 4 MODE

SS/REFIN 5 15 PGND PGND 15 5 SS/REFIN

VSNS- 6 14 PGND PGND 14 6 VSNS-

FB 7 13 PGND PGND 13 7 FB

EN 8 12 PGND PGND 12 8 EN

PGOOD 9 11 PGND PGND 11 9 PGOOD

10 10
VIN VIN
Figure 5-1. RWW Package 21-Pin VQFN-HR Top Figure 5-2. RWW Package 21-Pin VQFN-HR Bottom
View View

Table 5-1. Pin Functions

NO. NAME I/O(1) DESCRIPTION
Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap
1 BOOT I/O
capacitor from this pin to SW node.
2 AGND G Ground pin, reference point for the internal control circuits
Current limit setting pin. Connect a resistor to AGND to set the current limit trip
3 TRIP I/O point. A ±1% tolerance resistor is highly recommended. See Section 7.3.9 for
details on OCL setting.
The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-
mode operation. It also selects the operating frequency by connecting a resistor
4 MODE I
from the MODE pin to the AGND pin. ±1% tolerance resistor is recommended.
See Table 7-1 for details.
Dual-function pin. Soft-start function: Connecting a capacitor to VSNS– pin
programs soft-start time. Minimum soft-start time (1.5 ms) is fixed internally. A
minimum 1-nF capacitor is required for this pin to avoid overshoot during the
5 SS/REFIN I/O charge of soft-start capacitor.
REFIN function: The device always looks at the voltage on this SS/REFIN pin
as the reference for the control loop. The internal reference voltage can be
overridden by an external DC voltage source on this pin for tracking application.
The return connection for a remote voltage sensing configuration. It is also
6 VSNS– I used as ground for the internal reference. Short to AGND for single-end sense
configuration.
Output voltage feedback input. A resistor divider from the VOUT to VSNS– (tapped
7 FB I
to FB pin) sets the output voltage.
Enable pin. The enable pin turns the DC/DC switching converter on or off.
Floating EN pin before start-up disables the converter. The recommended
8 EN I
operating condition for EN pin is maximum 5.5 V. Do not connect EN pin to VIN
pin directly.
Open-drain power-good status signal. When the FB voltage moves outside the
9 PGOOD O
specified limits, PGOOD goes low after 2-µs delay.
Power-supply input pins for both integrated power MOSFET pair and the internal
10, 21 VIN P LDO. Place the decoupling input capacitors from VIN pins to PGND pins as close
as possible.

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Table 5-1. Pin Functions (continued)

NO. NAME I/O(1) DESCRIPTION
Power ground of internal low-side MOSFET. At least six PGND vias are required
11, 12, 13, 14,
PGND G to be placed as close as possible to the PGND pins. This minimizes parasitic
15, 16, 17, 18
impedance and also lowers thermal resistance.
Internal 4.5-V LDO output. An external bias with 5.0-V can be connected to this
pin to save the power losses on the internal LDO. The voltage source on this
19 VCC I/O pin powers both the internal circuitry and gate driver. Requires a 2.2-µF, at least
6.3-V rating ceramic capacitor from the VCC pin to PGND pins as the decoupling
capacitor and the placement is required to be as close as possible.
Output switching terminal of the power converter. Connect this pin to the output
20 SW O
inductor.

(1) I = Input, O = Output, P = Supply, G = Ground

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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Pin voltage VIN –0.3 18 V
Pin voltage VIN – SW, DC –0.3 18 V
Pin voltage VIN – SW, < 20 ns transient –4 25 V
Pin voltage SW – PGND, DC –0.3 18 V
Pin voltage SW – PGND, < 20 ns transient –5 21.5 V
Pin voltage BOOT – PGND –0.3 24 V
Pin voltage BOOT – SW –0.3 6 V
Pin voltage VCC –0.3 6 V
Pin voltage EN, PGOOD –0.3 6 V
Pin voltage MODE –0.3 6 V
Pin voltage TRIP, SS/REFIN, FB –0.3 3 V
Pin voltage VSNS– –0.3 0.3 V
Sinking current Power Good sinking current capability 10 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
±2000
JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification
±500
JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage range when VCC pin is powered by a valid external bias 2.7 16 V
VIN Input voltage range when using the internal VCC LDO 3.0 16 V
VIN Minimum VIN before enabling the converter when using the internal VCC LDO 3.0 V
VOUT Output voltage range 0.6 5.5 V
Pin voltage External VCC bias 4.75 5.3 V
Pin voltage BOOT to SW –0.1 5.3 V
Pin voltage EN, PGOOD –0.1 5.5 V
Pin voltage MODE –0.1 VCC V
Pin voltage TRIP, SS/REFIN, FB –0.1 1.5 V
Pin voltage VSNS– (refer to AGND) –50 50 mV
IPG Power Good input current capability 0 10 mA
ILPEAK Maximum peak inductor current 25 A
Minimum RTRIP 4.0 kΩ
TJ Operating junction temperature –40 125 °C

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6.4 Thermal Information

TPS548A29
THERMAL METRIC(1) RWW (QFN, JEDEC) RWW (QFN, TI EVM) UNIT
21 PINS 21 PINS
RθJA Junction-to-ambient thermal resistance 49.5 26.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.2 Not applicable (2) °C/W
RθJB Junction-to-board thermal resistance 11.2 Not applicable (2) °C/W
ψJT Junction-to-top characterization parameter 0.6 0.5 °C/W
ψJB Junction-to-board characterization parameter 11.2 9.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Not applicable to an EVM layout.

6.5 Electrical Characteristics

TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN = 12 V, VEN = 2 V, VFB = VINTREF +
IQ(VIN) VIN quiescent current 50mV (non-switching), no external bias on 680 850 µA
VCC pin
VIN = 12 V, VEN = 0 V, no external bias on
ISD(VIN) VIN shutdown supply current 9.5 20 µA
VCC pin
TJ = 25°C, VIN = 12 V, VEN = 2 V, VFB
IQ(VCC) VCC quiescent current = VINTREF + 50mV (non-switching), 5.0V 680 820 µA
external bias on VCC pin
5.0 V external bias on VCC pin, regular
switching. TJ = 25°C, VIN = 12 V, VEN = 2 10 mA
V, RMODE = 0 Ω to AGND
5.0 V external bias on VCC pin, regular
IVCC VCC external bias current (1) switching. TJ = 25°C, VIN = 12 V, VEN = 2 13.5 mA
V, RMODE = 30.1 kΩ to AGND
5.0 V external bias on VCC pin, regular
switching. TJ = 25°C, VIN = 12 V, VEN = 2 16 mA
V, RMODE = 60.4 kΩ to AGND
VEN = 0 V, VIN=0 V, 5.0 V external bias on
ISD(VCC) VCC shutdown current 75 90 µA
VCC pin
UVLO
VINUVLO(R) VIN UVLO rising threshold VIN rising, VCC = 5.0V external bias 2.1 2.4 2.7 V
VINUVLO(F) VIN UVLO falling threshold VIN falling, VCC = 5.0V external bias 1.55 1.85 2.15 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.17 1.22 1.27 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.97 1.02 1.07 V
VEN(H) EN voltage hysteresis 0.2 V
IEN(LKG) EN input leakage current VEN = 3.3 V 0.5 5 µA
EN internal pull-down resistance EN pin to AGND 6500 kΩ
INTERNAL LDO (VCC PIN)
Internal LDO output voltage VIN = 12 V, ILOAD(VCC) = 2 mA 4.32 4.5 4.68 V
VCCUVLO(R) VCC UVLO rising threshold VCC rising 2.80 2.87 2.94
V
VCCUVLO(F) VCC UVLO falling threshold VCC falling 2.62 2.70 2.77
VCCUVLO(H) VCC UVLO hysteresis 0.17 V
TJ = 25°C, VIN = 3.0 V, IVCC_LOAD = 2 mA,
VCC LDO dropout voltage 27 mV
non-switching
VCC LDO short-circuit current limit VIN = 12 V, all temperature 52 105 158 mA
REFERENCE VOLTAGE
VINTREF Internal voltage reference TJ = 25°C 600 mV
Internal voltage reference range TJ = 0°C to 85°C 597 603 mV

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TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal voltage reference range TJ = –40°C to 125°C 594 606 mV
IFB(LKG) Input leakage current into FB pin VFB = VINTREF 1 40 nA
TJ = -40°C to 125°C, VSS/REFIN = 0.6 V,
SS/REFIN-to-FB Accuracy –0.6% 0.6%
VSNS- = AGND, refer to VINTREF
SWITCHING FREQUENCY
TJ = 25°C, VIN = 12 V, VOUT=1.2V, No load,
0.54 0.62 0.70
RMODE = 0 Ω to AGND
TJ = 25°C, VIN = 12 V, VOUT=1.2V, No load,
fSW SW switching frequency, FCCM operation 0.72 0.8 0.88 MHz
RMODE = 30.1 kΩ to AGND
TJ = 25°C, VIN = 12 V, VOUT=1.2V, No load,
0.82 0.97 1.1
RMODE = 60.4 kΩ to AGND
STARTUP
The delay from EN goes high to the first SW
EN to first switching delay, internal LDO rising edge with internal LDO configuration. 0.93 2 ms
CVCC = 2.2 µF. CSS/REFIN = 220 nF.
The delay from EN goes high to the
first SW rising edge with external VCC
EN to first switching delay, external VCC
bias configuration. VCC bias should reach 550 900 µs
bias
regulation before EN ramp up. CSS/REFIN =
220 nF.
VO rising from 0 V to 95% of final setpoint,
tSS Internal fixed Soft-start time 1 1.5 ms
CSS/REFIN = 1nF
SS/REFIN sourcing current VSS/REFIN = 0 V 36 µA
SS/REFIN sinking current VSS/REFIN = 1 V 12 µA
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C, BOOT–SW = 4.5 V 8.4 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C, VCC = 4.5 V 2.6 mΩ
tON(min) Minimum on-time TJ = 25°C, VCC = Internal LDO 70 85 ns
TJ = 25°C, VCC = Internal LDO, IO=1.5A,
tOFF(min) Minimum off-time VFB = VINTREF – 20 mV, SW falling edge to 220 ns
rising edge
BOOT CIRCUIT
IBOOT(LKG) BOOT leakage current TJ = 25°C, VBOOT-SW = 5.0 V 35 50 µA
VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold TJ = 25°C, VIN = 12 V, VBOOT-SW falling 2.0 V
OVERCURRENT PROTECTION
RTRIP TRIP pin resistance range 4.0 14.7 kΩ
Valley current on LS FET, 0 Ω ≤ RTRIP ≤ 3.32
Current limit clamp 14.8 18.4 21.7 A
kΩ
KOCL Constant KOCL for RTRIP equation 60000 A×Ω
KOCL Constant KOCL tolerance RTRIP = 4.02 kΩ –19.5% 19.5%
KOCL Constant KOCL tolerance 4.99 kΩ ≤ RTRIP ≤ 6.04 kΩ –17.5% 17.5%
KOCL Constant KOCL tolerance RTRIP = 7.5 kΩ –22.5% 22.5%
KOCL Constant KOCL tolerance RTRIP = 10 kΩ –35% 35%
INOCL Negative current limit threshold All VINs –12 –10 –8 A
Zero-cross detection current threshold, open
IZC VIN = 12 V, VCC = Internal LDO 400 mA
loop
OUTPUT OVP AND UVP
Output Overvoltage-protection (OVP)
VOVP 113% 116% 119%
threshold voltage
tOVP(delay) Output OVP response delay With 100-mV overdrive 400 ns
Output Undervoltage-protection (UVP)
VUVP 77% 80% 83%
threshold voltage
tUVP(delay) Output UVP filter delay 68 µs
POWER GOOD

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TJ = –40°C to +125°C, VCC = 3 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FB rising, PGOOD low to high 89% 92.5% 95%
VPGTH PGOOD threshold FB rising, PGOOD high to low 113% 116% 119%
FB falling, PGOOD high to low 77% 80% 83%
OOB (Out-Of-Bounds) threshold FB rising, PGOOD stays high 103% 105.5% 108%
VPGOOD = 0.4 V, VIN = 12 V, VCC = Internal
IPG PGOOD sink current 10 mA
LDO
IPGOOD = 5.5 mA, VIN = 12 V, VCC = Internal
VPG(low) PGOOD low-level output voltage 400 mV
LDO
tPGDLY(R) Delay for PGOOD from low to high During startup only 1.06 1.40 ms
tPGDLY(F) Delay for PGOOD from high to low 0.5 5 µs
IPG(LKG) PGOOD leakage current when pulled high TJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF 5 µA
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD
710 850 mV
pulled up to 3.3 V through a 100-kΩ resistor
PGOOD clamp low-level output voltage
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD
850 1000 mV
pulled up to 3.3 V through a 10-kΩ resistor
VIN = 0 V, VEN = 0 V, PGOOD pulled up to
Minimum VCC for valid PGOOD output 3.3 V through a 100-kΩ resistor, VPGOOD ≤ 1.5 V
0.4 V
OUTPUT DISCHARGE
VIN = 12 V, VCC = Internal LDO, VSW = 0.5
RDischg Output discharge resistance 70 Ω
V, power conversion disabled
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold (1) Temperature rising 150 165 °C
THYST Thermal shutdown hysteresis (1) 30 °C

(1) Specified by design. Not production tested.

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6.6 Typical Characteristics

100 100
95 95
90 90
85 85
80 80
Efficiency (%)

Efficiency (%)
75 75
70 70
Vout = 0.6 V Vout = 0.6 V
65 Vout = 1.0 V 65 Vout = 1.0 V
Vin = 12 V Vin = 12 V
60 800 kHz Vout = 1.2 V 60 800 kHz Vout = 1.2 V
VCC = Int Vout = 1.8 V VCC = Int Vout = 1.8 V
55 Vout = 2.5 V 55 Vout = 2.5 V
800 nH 800 nH
50 Skip Vout = 3.3 V 50 FCCM Vout = 3.3 V
Vout = 5.0 V Vout = 5.0 V
45 45
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Output Current (A) D036
Output Current (A) D034

Figure 6-1. Efficiency vs Output Current, Skip- Figure 6-2. Efficiency vs Output Current, FCCM,
mode, Internal VCC LDO Internal VCC LDO
115 115
110 110
105 105
Ambient Temperature (oC)

Ambient Temperature (oC)

100 100
95 95
90 90
85 85
80 Vin = 12 V 80 Vin = 12 V
Nat Conv Vout = 1.0 V Nat Conv Vout = 1.0 V
75 100 LFM VCC = Int 75 100 LFM VCC = 5.0 V
200 LFM 800 nH 200 LFM 800 nH
70 70
400 LFM 800 kHz 400 LFM 800 kHz
65 65
0 3 6 9 12 15 0 3 6 9 12 15
Output Current (A) 8A29
Output Current (A) 8A29

Figure 6-3. Safe Operating Area, VOUT = 1.0 V Figure 6-4. Safe Operating Area, VOUT = 1.0 V
130 130
120 120
110 110
Ambient Temperature (oC)

Ambient Temperature (oC)

100 100
90 90
80 80
70 70
60 Vin = 12 V 60 Vin = 12 V
Nat Conv Vout = 5.0 V Nat Conv Vout = 5.0 V
50 100 LFM VCC = Int 50 100 LFM VCC = 5.0 V
200 LFM 800 nH 200 LFM 800 nH
40 40
400 LFM 800 kHz 400 LFM 800 kHz
30 30
0 3 6 9 12 15 0 3 6 9 12 15
Output Current (A) 8A29
Output Current (A) 8A29

Figure 6-5. Safe Operating Area, VOUT = 5 V Figure 6-6. Safe Operating Area, VOUT = 5 V

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800 20

750 15

ISD(VIN) (PA)
IQ(VIN) (PA)

700 10

650 5

600 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (qC) D013
Junction Temperature (qC) D014

Figure 6-7. IQ(VIN) vs Junction Temperature VIN = 12 V VEN = 0 V Internal VCC LDO

Figure 6-8. ISD(VIN) vs Junction Temperature

3.04 0.603

0.602
3.03

0.601
VCC LDO (V)

VINTREF (V)
3.02
0.6

3.01
0.599

3 0.598

2.99 0.597
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (qC) Junction Temperature (°C)
D015

VIN = 12 V IVCC = 2 mA VIN = 12 V

Figure 6-9. VCC LDO vs Junction Temperature Figure 6-10. VINTREF vs Junction Temperature
1200 40

1100 39

1000 38
ISS/REFIN(source) (PA)
Frequency (kHz)

900 37

800 36

700 35

600 34

500 33

400 32
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (qC) D017
Junction Temperature (qC) D020

VIN = 12 V VIN = 12 V

Figure 6-11. Switching Frequency vs Junction Figure 6-12. ISS(source) vs Junction Temperature
Temperature

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140 140

130 130

120 120
RDSON(HS) ( )

RDSON(LS) ( )
110 110

100 100

90 90

80 80

70 VBOOT-SW=4.5V 70 VCC=4.5V
VBOOT-SW=5.0V VCC=5.0V
60 60
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (RC) D041
Junction Temperature (RC) D042

VIN = 12 V VIN = 12 V

Figure 6-13. RDSON(HS) vs Junction Temperature Figure 6-14. RDSON(LS) vs Junction Temperature

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7 Detailed Description
7.1 Overview
The TPS548A29 device is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The
device suits low output voltage point-of-load applications with 15-A or lower output current in server, storage,
and similar computing applications. The TPS548A29 features proprietary D-CAP3 mode control combined with
adaptive on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response
DC/DC converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input
voltage ranges from 2.7 V to 16 V, and the VCC input voltage ranges from 4.75 V to 5.3 V. The D-CAP3 mode
uses emulated current information to control the modulation. An advantage of this control scheme is that it does
not require a phase-compensation network outside which makes the device easy to use and also allows low
external component count. Further advantage of this control scheme is that it supports stable operation with
all low-ESR output capacitors (such as ceramic capacitor and low-ESR polymer capacitor). Adaptive on-time
control tracks the preset switching frequency over a wide range of input and output voltages while increasing
switching frequency as needed during load-step transient.
7.2 Functional Block Diagram

SS/ Soft-start PGOOD

PG Falling
REFIN generator Threshold
+
UV
Internal
Soft-start VIN
PGOOD Driver
EN LDO
+
Reference VCC OV
generator
VCC
PG Rising
FB Threshold
BOOT
REG
PGOOD +
+ VCCOK
VCC UVLO BOOT
VSNS-
Control Logic
+ VIN
PWM VINOK VIN

+
VIN UVLO
x tON generator
Internal x Minimum On/Off
Ramp x Light Load
x FCCM/Skip
x VCC UVLO SW
EN x VIN UVLO XCON
EN + Enable x Output OVP/UVP
x Thermal Shutdown
1.22V / 1.02V

SW
Valley Current OC
TRIP Limit & ZCD Limit PGND

MODE Fsw &

MODE +
Selection Mode ThermalOK 165°C /
135°C
AGND Output Soft
Discharge

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7.3 Feature Description

7.3.1 Internal VCC LDO And Using External Bias On VCC Pin
The TPS548A29 has an internal 4.5-V LDO featuring input from VIN and output to VCC. When the EN voltage
rises above the enable threshold (typically 1.22 V), the internal LDO is enabled and starts regulating output
voltage on the VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also
provides the supply voltage for the gate drives.
The VCC pin needs to be bypassed with a 2.2-µF, at least 6.3-V rating ceramic capacitor. An external bias that is
above the output voltage of the internal LDO can override the internal LDO. This enhances the efficiency of the
converter because the VCC current now runs off this external bias instead of the internal linear regulator.
The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the
VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of
the device.
The following are considerations when using an external bias on the VCC pin:
• When the external bias is applied on the VCC pin early enough (for example, before EN signal comes in), the
internal LDO will be always forced off and the internal analog circuits will have a stable power supply rail at
their power enable.
• (Not recommended) When the external bias is applied on the VCC pin late (for example, after EN signal
comes in), any power-up and power-down sequencing can be applied as long as there is no excess current
pulled out of the VCC pin. It is important to understand that an external discharge path on the VCC pin, which
can pull a current higher than the current limit of the internal LDO from the VCC pin and can potentially turn
off VCC LDO thereby shutting down the converter output.
• A good power-up sequence is at least one of VIN UVLO rising threshold or EN rising threshold is satisfied
later than VCC UVLO rising threshold. For example, a practical power-up sequence is: VIN applied first, then
the external bias applied, and then EN signal goes high.
7.3.2 Enable
When the EN pin voltage rises above the enable threshold voltage (typically 1.22 V) and VIN rises above the
VIN UVLO rising threshold, the device enters its internal power-up sequence. The EN to first switching delay is
specified in the Start-up section of the Electrical Characteristics.
When using the internal VCC LDO, the internal power-up sequence includes three sequential steps. During
the first period, the VCC voltage is charged up on a VCC bypass capacitor by an 11-mA current source. The
length of this VCC LDO start-up time varies with the capacitance on the VCC pin. However, if the VIN voltage
ramps up very slowly, the VCC LDO output voltage will be limited by the VIN voltage level, thus the VCC LDO
start-up time can be extended longer. Since the VCC LDO start-up time is relatively long, the internal VINTREF
build-up happens and finishes during this period. Once the VCC voltage crosses above the VCC UVLO rising
threshold (typically 2.87 V), the device moves to the second step, power-on delay. The MODE pin setting
detection, SS/REFIN pin detection, and control loop initialization are finished within this 285-μs delay. A soft-start
ramp starts when the 285-μs power-on delay finishes. During the soft-start ramp power stage, switching does
not happen until the SS/REFIN pin voltage reaches 50 mV. This introduced a SS delay which varies with the
external capacitance on the SS/REFIN pin.
Figure 7-1 shows an example where the VIN UVLO rising threshold is satisfied earlier than the EN rising
threshold. In this scenario, the VCC UVLO rising threshold becomes the gating signal to start the internal
power-up sequence, and the sequence between VIN and EN does not matter.
When using an external bias on the VCC pin, the internal power-up sequence still includes three sequential
steps. The first period is much shorter since VCC voltage is built up already. A 100-µs period allows the internal
references to start up and reach regulation points. This 100-µs period includes not only the 0.6-V VINTREF,
but also all of the other reference voltages for various functions. The device then moves to the second step,
power-on delay. The MODE pin setting detection, SS/REFIN pin detection, and control loop initialization are
finished within this 285-μs delay. A soft-start ramp starts when the 285-μs power-on delay finishes. During the
soft-start ramp power stage, switching does not happen until the SS/REFIN pin voltage reaches 50 mV. This
introduced a SS delay which varies with the external capacitance on SS/REFIN pin.

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Figure 7-2 shows an example where both the VIN UVLO rising threshold and EN rising threshold are satisfied
later than the VCC UVLO rising threshold. In this scenario, the VIN UVLO rising threshold or EN rising threshold,
whichever is satisfied later, becomes the gating signal to start the internal power-up sequence.

2.4V
VIN

1.22V
EN
2.87V

VCC LDO
VCC LDO Power-on
Startup delay

SS/REFIN 50mV

SS delay
FB
SW pulses are omitted to
simplify the illustration
««
SW

Figure 7-1. Internal Power-up Sequence Using Internal LDO

2.87V
VCC
External
3.3V Bias

2.4V
VIN

1.22V
EN
Power-on
VREF delay
SS/REFIN Build-up
50mV

SS delay
FB
SW pulses are omitted to
simplify the illustration
««
SW

Figure 7-2. Internal Power-up Sequence Using External Bias

The EN pin has an internal filter to avoid unexpected ON or OFF due to small glitches. The time constant of this
RC filter is 5 µs. For example, when applying a 3.3-V voltage source on the EN pin, which jumps from 0 V to
3.3 V with ideal rising edge, the internal EN signal will reach 2.086 V after 5 µs, which is 63.2% of applied 3.3-V
voltage level.
A internal pulldown resistor is implemented between the EN pin and AGND pin. To avoid impact to the EN
rising/falling threshold, this internal pulldown resistor is set to 6.5 MΩ. With this pulldown resistor, floating the
EN pin before start-up keeps the TPS548A29 device under disabled state. During nominal operation when the
power stage switches, this large internal pulldown resistor may not have enough noise immunity to hold EN pin
low.
The recommended operating condition for EN pin is maximum 5.5 V. Do not connect the EN pin to the VIN pin
directly.

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7.3.3 Output Voltage Setting

The output voltage is programmed by the voltage divider resistors, RFB_HS and RFB_LS. Connect RFB_HS between
the FB pin and the positive node of the load, and connect RFB_LS between the FB pin and VSNS– pin. The
recommended RFB_LS value is 10 kΩ, ranging from 1 kΩ to 20 kΩ. Determine RFB_HS by using Equation 1.

VO VINTREF
RFB _ HS u RFB _ LS
VINTREF (1)

The FB accuracy is determined by two elements. The first element is the accuracy of the internal 600-mV
reference, which will be applied to the SS/REFIN pin unless an external VREF is applied. The TPS548A29 device
offers ±0.5% VINTREF accuracy from 0°C to 85°C, and ±1.0% VINTREF accuracy from -40°C to 125°C. The second
element is the SS/REFIN-to-FB accuracy, which tells you how accurately the control loop regulates FB node
to SS/REFIN pin. The TPS548A29 device offers ±0.6% SS/REFIN-to-FB accuracy from -40°C to 125°C. For
example, when operating from 0°C to 85°C, the total FB accuracy is ±1.1% which includes the impact from chip
junction temperature and also the variation from part to part.
To improve the overall VOUT accuracy, using ±1% accuracy or better resistor for the FB voltage divider is highly
recommended.
Regardless of remote sensing or single-end sensing connection, the FB voltage divider, RFB_HS and RFB_LS,
should be always placed as close as possible to the device.
7.3.3.1 Remote Sense
The TPS548A29 device offers remote sense function through the FB and VSNS– pins. Remote sense function
compensates a potential voltage drop on the PCB traces, thus helps maintain VOUT tolerance under steady state
operation and load transient event. Connecting the FB voltage divider resistors to the remote location allows
sensing the output voltage at a remote location. The connections from the FB voltage divider resistors to the
remote location should be a pair of PCB traces with at least 12-mil trace width, and should implement Kelvin
sensing across a high bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal
must be connected to the VSNS– pin. The VOUT connection of the remote sensing signal must be connected to
the feedback resistor divider with the lower feedback resistor, RFB_LS, terminated at the VSNS– pin. To maintain
stable output voltage and minimize the ripple, the pair of remote sensing lines should stay away from any noise
sources such as inductor and SW nodes, or high frequency clock lines. It is recommended to shield the pair of
remote sensing lines with ground planes above and below.
Single-ended Vo sensing is often used for local sensing. For this configuration, connect the higher FB resistor,
RFB_HS, to a high-frequency local bypass capacitor of 0.1 μF or higher, and short VSNS– to AGND.
The recommended VSNS– operating range (refer to AGND pin) is –50 mV to +50 mV.
7.3.4 Internal Fixed Soft Start and External Adjustable Soft Start
The TPS548A29 implements a circuit to allow both internal fixed soft start and external adjustable soft start.
The internal soft-start time is typically 1.5 ms. The soft-start time can be increased by adding a soft-start (SS)
capacitor between the SS/REFIN and VSNS– pins. The total SS capacitor value can be determined by Equation
2. The device follows the longer SS ramp among the internal SS time and the SS time determined by the
external SS capacitors. The recommended maximum SS capacitor is 1 µF. A minimum 1-nF SS capacitor is
required.
The device does not require a capacitor from the SS/REFIN pin to AGND, thus it is not recommenced to place a
capacitor from the SS/REFIN pin to AGND. If both CSS/REFIN-to-VSNS– and CSS/REFIN-to-AGND capacitors exist,
place CSS/REFIN-to-VSNS– more closely with shortest trace back to the VSNS– pin.
The SS/REFIN pin is discharged internally during the internal power-on delay to make sure the soft-start ramp
always starts from zero.

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t SS ( ms ) u 36( PA )
CSS (nF)=
VINTREF ( V ) (2)

7.3.5 External REFIN For Output Voltage Tracking

The TPS548A29 provides an analog input pin (SS/REFIN) to accept an external reference (that is, a DC
voltage source). The device always looks at the voltage on this SS/REFIN pin as the reference for the control
loop. When an external voltage reference is applied between the SS/REFIN pin and VSNS– pin, it acts as
the reference voltage, thus the FB voltage follows this external voltage reference exactly. The same ±0.6%
SS/REFIN-to-FB accuracy from -40°C to 125°C applies here too.
In the middle of internal power-on delay, a detection circuit senses the voltage on the SS/REFIN pin to tell
you whether an active DC voltage source is applied. Before the detection happens, the SS/REFIN pin tries to
discharge any energy on the SS/REFIN capacitors through an internal 120-Ω resistor to AGND. This discharge
lasts for 125 µs. Then, within a 32-µs window, the detection circuit compares the SS/REFIN pin voltage with
an internal reference equal to 89% of VINTREF. This discharge operation ensures a SS capacitor with left-over
energy will not be wrongly detected as a voltage reference. If the external voltage reference fails to supply
sufficient current and hold voltage level higher than 89% of VINTREF, the SS/REFIN detection circuit will provide a
wrong detection result.
If the detection result is that the SS/REFIN pin voltage falls below 89% of VINTREF which tells you no external
reference is connected, the device first uses the internal fixed VINTREF as the reference for the PGOOD
threshold, VOUT OVP, and VOUT UVP threshold. On this configuration, given the SS/REFIN pin sees a soft-start
ramp on this pin, the slower ramp among the internal fixed soft start and the external soft start determines the
start-up of FB. Once both the internal and external soft-start ramp finishes, the power-good signal becomes high
after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start
done signal goes high when FB reaches a threshold equal to VINTREF – 50 mV. The device waits for the PGOOD
status transition from low to high, then starts using the SS/REFIN pin voltage instead of the internal VINTREF as
the reference for PGOOD threshold, VOUT OVP, and VOUT UVP threshold.
If the detection result is that the SS/REFIN pin voltage holds higher than 89% of VINTREF which tells you an
active DC voltage source is used as an external reference, the device always uses the SS/REFIN pin voltage,
instead of the internal VINTREF, as the reference for PGOOD threshold, VOUT OVP, and VOUT UVP threshold. On
this configuration, since the SS/REFIN pin sees a DC voltage and no soft-start ramp on this pin, the internal fixed
soft start is used for start-up. Once the internal soft-start ramp finishes, the power-good signal becomes high
after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish because the soft-start ramp
goes beyond VINTREF.
On this external REFIN configuration, applying a stabilized DC external reference to the SS/REFIN pin before
EN high signal is recommended. During the internal power-on delay, the external reference should be capable
to hold the SS/REFIN pin equal to or higher than 89% of VINTREF, so that the device can correctly detect the
external reference and choose the right thresholds for Power Good, VOUT OVP, and VOUT UVP. After the Power
Good status transits from low to high, the external reference can be set in a range of 0.5 V to 1.2 V. To overdrive
the SS/REFIN pin during nominal operation, the external reference has to be able to sink more than 36-µA
current if the external reference is lower than the internal VINTREF, or source more than 12-µA current if the
external reference is higher than the internal VINTREF. When driving the SS/REFIN pin by an external reference
through a resistor divider, the resistance of the divider should be low enough to provide the sinking or sourcing
current capability.
The configuration of applying the EN high signal first, then applying an external ramp on the SS/REFIN pin as
a tracking reference can be achieved, as long as design considerations for Power Good, VOUT OVP, and VOUT
UVP have been taken. Please contact Texas Instruments for detailed information about this configuration.
If the external voltage source must transition up and down between any two voltage levels, the slew rate must be
no more than 1 mV/μs.

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7.3.6 Frequency and Operation Mode Selection

The TPS548A29 provides forced CCM operation for tight output ripple application and auto-skip Eco-mode for
high light-load efficiency. The TPS548A29 allows users to select the switching frequency and operation mode
by connecting a resistor from the MODE pin to AGND pin. Table 7-1 lists the resistor values for the switching
frequency and operation mode selection. TI recommends ±1% tolerance resistors with a typical temperature
coefficient of ±100 ppm/°C.
The MODE state will be set and latched during the internal power-on delay period. Changing the MODE pin
resistance after the power-on delay will not change the status of the device. The internal circuit will set the
MODE pin status to 600 kHz / skip mode if the MODE pin is left open during the power-on delay period.
To make sure the internal circuit detects the desired option correctly, do not place any capacitor on the MODE
pin.
Table 7-1. MODE Pin Selection
MODE PIN OPERATION MODE UNDER LIGHT SWITCHING FREQUENCY
CONNECTIONS LOAD (fSW) (kHz)
Short to VCC Skip-mode 600
243-kΩ ± 10% to AGND Skip-mode 800
121-kΩ ± 10% to AGND Skip-mode 1000
60.4-kΩ ±10% to AGND Forced CCM 1000
30.1-kΩ ±10% to AGND Forced CCM 800
Short to AGND Forced CCM 600

7.3.7 D-CAP3 Control

The TPS548A29 uses D-CAP3 mode control to achieve the fast load transient while maintaining the ease-of-use
feature. The D-CAP3 control architecture includes an internal ripple generation network, enabling the use of very
low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low-ESR polymer capacitors.
No external current sensing network or voltage compensators are required with D-CAP3 control architecture.
The role of the internal ripple generation network is to emulate the ripple component of the inductor current
information and then combine it with the voltage feedback signal to regulate the loop operation. The amplitude of
the ramp is determined by VIN, VOUT, operating frequency, and the R-C time-constant of the internal ramp circuit.
At different switching frequency settings (see Table 7-1), the R-C time-constant varies to maintain relatively
constant ramp amplitude. Also, the device utilizes internal circuitry to cancel the dc offset caused by injected
ramp and significantly reduce the dc offset caused by the output ripple voltage, especially under light load
condition.
For any control topologies that do not support external compensation design, there is a minimum range of
the output filter, maximum range of the output filter, or both, it can support. The output filter used with the
TPS548A29 is a low-pass L-C circuit. This L-C filter has double pole that is described in Equation 3.

1
fP =
2 ´ p ´ LOUT ´ COUT (3)

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS548A29. The low frequency L-C double pole has a 180-degree drop in-phase. At the output
filter frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40-dB to –20-dB per
decade and increases the phase by 90 degrees per decade above the zero frequency.
After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 15% and 40% of the maximum output current.
The inductor and capacitor selected for the output filter must be such that the double pole of Equation 3 is
located no higher than 1/30 of operating frequency. Choose very small output capacitance leads to relative high

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frequency L-C double pole which allows that overall loop gain stays high until the L-C double frequency. Given
the zero from the internal ripple generation network is relatively high frequency as well, the loop with very small
output capacitance can have too high of crossover frequency which is not desired. Use Table 7-2 to help locate
the internal zero based on the selected switching frequency.
Table 7-2. Locating the Zero
SWITCHING
FREQUENCIES ZERO (fZ) LOCATION (kHz)
(fSW) (kHz)
600 84.5
800 84.5
1000 106

In general, where reasonable (or smaller) output capacitance is desired, the output ripple requirement and load
transient requirement can be used to determine the necessary output capacitance for stable operation.
For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C
double pole frequency is no less than 1/100 of operating frequency. With this starting point, verify the small
signal response on the board using the following one criteria:
• Phase margin at the loop crossover is greater than 50 degrees
The actual maximum output capacitance can go higher as long as phase margin is greater than 50 degrees.
However, small signal measurement (bode plot) should be done to confirm the design.
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10 µF, X5R, and 6.3 V, the derating by DC bias and
AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this
case, is 40% and 4 µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be
used in the system/applications.
For higher output voltage at or above 2 V, additional phase boost can be required to secure sufficient phase
margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed-on-time topology
based operation. A feedforward capacitor placing in parallel with RFB_HS is found to be very effective to boost the
phase margin at loop crossover. Refer to the Optimizing Transient Response of Internally Compensated dc-dc
Converters With Feedforward Capacitor application report for details.
Besides boost the phase, a feedforward capacitor feeds more VOUT node information into the FB node by AC
coupling. This feedforward during load transient event enables the control loop to a faster response to VOUT
deviation. However, this feedforward during steady state operation also feeds more VOUT ripple and noise into
FB. High ripple and noise on FB usually leads to more jitter, or even double pulse behavior. To determine the
final feedforward capacitor value, impacts to phase margin, load transient performance and ripple, and noise on
FB should be all considered. Using Frequency Analysis equipment to measure the crossover frequency and the
phase margin is recommended.
7.3.8 Low-side FET Zero-Crossing
The TPS548A29 uses a zero-crossing circuit to perform the zero inductor-current detection during skip-mode
operation. The function compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C
detection circuit. The zero-crossing threshold is set to a positive value to avoid negative inductor current. As a
result, the device delivers better light-load efficiency.
7.3.9 Current Sense and Positive Overcurrent Protection
For a buck converter, during the on-time of the high-side FET, the switch current increases at a linear rate
determined by input voltage, output voltage, the on-time, and the output inductor value. During the on-time of the
low-side FET, this current decreases linearly. The average value of the switch current equals to the load current.
The output overcurrent limit (OCL) in the TPS548A29 device is implemented using a cycle-by-cycle valley
current detect control circuit. The inductor current is monitored during the on-time of the low-side FET by

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measuring the low-side FET drain-to-source current. If the measured drain-to-source current of the low-side FET
is above the current limit threshold, the low-side FET stays ON until the current level becomes lower than the
current limit threshold. This type of behavior reduces the average output current sourced by the device. During
an overcurrent condition, the current to the load exceeds the current to the output capacitors. Thus, the output
voltage tends to decrease. Eventually, when the output voltage falls below the undervoltage-protection threshold
(80%), the UVP comparator detects it and shuts down the device after a wait time of 68 µs. The device then
enters a hiccup sleep period for approximately 14 ms. After this waiting period, the device attempts to start up
again. Figure 7-3 shows the cycle-by-cycle valley current limit behavior as well as the wait time before the device
shuts down.
If an OCL condition happens during start-up, the device still has cycle-by-cycle current limit based on low-side
valley current. After soft start is finished, the UV event, which is caused by the OC event, shuts down the device
and enters hiccup mode with a wait time of 68 µs.
The resistor, RTRIP, connected from the TRIP pin to AGND sets current limit threshold. A ±1% tolerance resistor
is highly recommended because a worse tolerance resistor provides less accurate OCL threshold. Equation
4 calculates the RTRIP for a given overcurrent limit threshold on the device. To simplify the calculation, use a
constant, KOCL, to replace the value of 6x104. Equation 5 calculates the overcurrent limit threshold for a given
RTRIP value. The tolerance of KOCL is listed in the Electrical Characteristics to help you analyze the tolerance of
the overcurrent limit threshold.
To protect the device from unexpected connection on TRIP pin, an internal fixed OCL clamp is implemented.
This internal OCL clamp limits the maximum valley current on LS FET when the TRIP pin has too small
resistance to AGND, or is accidently shorted to ground.

6 u 104 K OCL
RTRIP
1 VIN -VO u VO 1 1 VIN -VO u VO 1
I OCLIM u u I OCLIM u u
2 VIN L u fSW 2 VIN L u fSW (4)

where
• IOCLIM is overcurrent limit threshold for load current in A
• RTRIP is TRIP resistor value in Ω
• KOCL is a constant for the calculation
• VIN is input voltage value in V
• VO is output voltage value in V
• L is output inductor value in µH
• fSW is switching frequency in MHz

K OCL 1 VIN -VO u VO 1

I OCLIM u u
RTRIP 2 VIN L u fSW (5)

where
• IOCLIM is overcurrent limit threshold for load current in A
• RTRIP is TRIP resistor value in Ω
• KOCL is a constant for the calculation
• VIN is input voltage value in V
• VO is output voltage value in V
• L is output inductor value in µH
• fSW is switching frequency in MHz

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Figure 7-3. Overcurrent Protection

7.3.10 Low-side FET Negative Current Limit

The device has a fixed, cycle-by-cycle negative current limit. Similar with the positive overcurrent limit, the
inductor current is monitored during the on-time of the low-side FET. To prevent too large of negative current
flowing through the low-side FET, when the low-side FET detects –10-A current (typical threshold), the device
turns off the low-side FET and then turns on the high-side FET for a proper on-time (determined by VIN/VO/fSW).
After the high-side FET on-time expires, the low-side FET turns on again.
The device should not trigger the –10-A negative current limit threshold during nominal operation unless too
small inductor value is chosen or the inductor becomes saturated. This negative current limit is utilized to
discharge output capacitors during an output OVP or an OOB event. See Section 7.3.12 and Section 7.3.13 for
details.
7.3.11 Power Good
The device has power-good output that indicates high when the converter output is within the target. The
power-good output is an open-drain output and must be pulled up to VCC pin or an external voltage source (<5.5
V) through a pullup resistor (typically 30.1 kΩ). The recommended power good pullup resistor value is 1 kΩ to
100 kΩ.
Once both the internal and external soft-start ramp finishes, the power-good signal becomes high after a
1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal
goes high when FB reaches a threshold equal to VINTREF – 50 mV. If the FB voltage drops to 80% of the VINTREF
voltage or exceeds 116% of the VINTREF voltage, the power-good signal latches low after a 2-µs internal delay.
The power-good signal can only be pulled high again after re-toggling EN or a reset of VIN.
If the input supply fails to power up the device, for example VIN and VCC both stay at zero volt, the power-good
pin clamps low by itself when this pin is pulled up through an external resistor.
Once the VCC voltage level rises above the minimum VCC threshold for valid PGOOD output (maximum 1.5
V), an internal power-good circuit is enabled to hold the PGOOD pin to the default status. By default, PGOOD
is pulled low and this low-level output voltage is no more than 400 mV with 5.5-mA sinking current. The
power-good function is fully activated after the soft start operation is completed.
7.3.12 Overvoltage and Undervoltage Protection
The device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage events. When
the FB voltage becomes lower than 80% of the VINTREF voltage, the UVP comparator detects and an internal
UVP delay counter begins counting. After the 68-µs UVP delay time, the device enters hiccup mode and
re-starts with a sleep time of 14 ms. The UVP function enables after the soft start period is complete.
When the FB voltage becomes higher than 116% of the VINTREF voltage, the OVP comparator detects and the
circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until it reaches a negative
current limit, INOCL. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again, for the on-time determined by VIN, VOUT, and fSW. The device operates in this cycle until

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the output voltage is pulled below the UVP threshold voltage for 68 µs. After the 68 µs UVP delay time, both the
high-side FET and the low-side FET are latched OFF. The fault is cleared with a reset of VIN or by re-toggling
the EN pin.
During the 68-μs UVP delay time, if output voltage becomes higher than UV threshold, thus is not qualified for
UV event, the timer will be reset to zero. When the output voltage triggers the UV threshold again, the timer of
the 68 μs re-starts.
7.3.13 Out-Of-Bounds (OOB) Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 5% above the VINTREF voltage. OOB protection does not trigger an overvoltage fault, so
the device is on non-latch mode after an OOB event. OOB protection operates as an early no-fault overvoltage-
protection mechanism. During the OOB operation, the controller operates in forced CCM mode. Turning on the
low-side FET beyond the zero inductor current quickly discharges the output capacitor thus helps the output
voltage to fall quickly towards the setpoint. During the operation, the cycle-by-cycle negative current limit is also
activated to ensure the safe operation of the internal FETs.
7.3.14 Output Voltage Discharge
When the device is disabled through EN, it enables the output voltage discharge mode. This mode forces both
high-side and low-side FETs to latch off, but turns on the discharge FET, which is connected from SW to PGND,
to discharge the output voltage. Once the FB voltage drops below 90 mV, the discharge FET is turned off.
The output voltage discharge mode is activated by any of the following fault events:
1. EN pin goes low to disable the converter.
2. Thermal shutdown (OTP) is triggered.
3. VCC UVLO (falling) is triggered.
4. VIN UVLO (falling) is triggered.
7.3.15 UVLO Protection
The device monitors the voltage on both the VIN and the VCC pins. If the VCC pin voltage is lower than the
VCCUVLO falling threshold voltage, the device shuts off. If the VCC voltage increases beyond the VCCUVLO rising
threshold voltage, the device turns back on. VCC UVLO is a non-latch protection.
When the VIN pin voltage is lower than the VINUVLO falling threshold voltage but VCC pin voltage is still higher
than VCCUVLO rising threshold voltage, the device stops switching and discharges the SS/REFIN pin. Once the
VIN voltage increases beyond the VINUVLO rising threshold voltage, the device re-initiates the soft start and
switches again. VIN UVLO is a non-latch protection.
7.3.16 Thermal Shutdown
The device monitors internal junction temperature. If the temperature exceeds the threshold value (typically
165°C), the device stops switching and discharges the SS/REFIN pin. When the temperature falls approximately
30°C below the threshold value, the device turns back on with a re-initiated soft start. Thermal shutdown is a
non-latch protection.
7.4 Device Functional Modes
7.4.1 Auto-Skip Eco-mode Light Load Operation
While the MODE pin is pulled to VCC directly or connected to the AGND pin through a resistor larger than 121
kΩ, the device automatically reduces the switching frequency at light-load conditions to maintain high efficiency.
This section describes the operation in detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on-time is maintained to a level approximately the same as during continuous-conduction mode operation
so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires

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more time. The transition point to the light-load operation IO(LL) (for example, the threshold between continuous-
and discontinuous-conduction mode) is calculated as shown in Equation 6.

IOUT(LL ) =
1
´
(VIN - VOUT )´ VOUT
2 ´ L ´ fSW VIN (6)

where
• fSW is the switching frequency
Using only ceramic capacitors is recommended for skip mode.
7.4.2 Forced Continuous-Conduction Mode
When the MODE pin is tied to the AGND pin through a resistor less than 60.4 kΩ, the controller operates
in continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency
maintained to an almost constant level over the entire load range which is suitable for applications requiring
tight control of the switching frequency at the cost of lower efficiency.
7.4.3 Powering The Device From A 12-V Bus
The device works well when powering from a 12-V bus with a single VIN configuration. As a single VIN
configuration, the internal LDO is powered by a 12-V bus and generates 4.5-V output to bias the internal analog
circuitry and also powers up the gate drives. The VIN input range under this configuration is 4 V to 16 V for up to
15-A load current. The VIN range can be extended down to 3 V if the desired load current is no more than 12 A.
Figure 7-4 shows an example for this single VIN configuration.
VIN and EN are the two signals to enable the part. For start-up sequence, any sequence between the VIN and EN
signals can power the device up correctly.
VIN: 4V ± 16V CBOOT
10 VIN BOOT 1
CIN 21 VIN
LOUT VOUT
SW 20
EN
8 EN
CFF, Optional
PGOOD
9 PGOOD Vosns+
RPG_pullup
FB 7
19 VCC COUT
CVCC RFB_HS
RMODE
RFB_LS
4 MODE Vosns-
RTRIP
VSNS- 6
3 TRIP
CSS
SS/
5
2 AGND REFIN
PGND

Figure 7-4. Single VIN Configuration With 12-V Bus

7.4.4 Powering The Device From A 3.3-V Bus

The device can also work for up to 15-A load current when powering from a 3.3-V bus with a single VIN
configuration. To ensure the internal analog circuitry and the gate drives are powered up properly, the VCC pin
should be shorted to VIN pins with low impedance trace. A trace with at least 24-mil width is recommended.
A 2.2-µF, at least 6.3-V rating VCC-to-PGND decoupling capacitor is still recommended to be placed as close
as possible to VCC pin. Due to the maximum rating limit on the VCC pin, the VIN input range under this

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configuration is 3 V to 5.3 V. The input voltage must stay higher than both VIN UVLO and VCC UVLO, otherwise
the device will shut down immediately. Figure 7-5 shows an example for this single VIN configuration.
VIN and EN are the two signals to enable the part. For start-up sequence, any sequence between the VIN and EN
signals can power the device up correctly.
VIN: 3.3V bus CBOOT
10 VIN BOOT 1
CIN 21 VIN
LOUT VOUT
SW 20
EN
8 EN
CFF, Optional
PGOOD
9 PGOOD Vosns+
RPG_pullup
FB 7
19 VCC COUT
CVCC RFB_HS
RMODE
RFB_LS
4 MODE Vosns-
RTRIP
VSNS- 6
3 TRIP
CSS
SS/
5
2 AGND REFIN
PGND

Figure 7-5. Single VIN Configuration With 3.3-V Bus

7.4.5 Powering The Device From A Split-rail Configuration

When an external bias, which is at a different level from the main VIN bus, is applied onto the VCC pin, the
device can be configured to split-rail by utilizing both the main VIN bus and VCC bias. Connecting a valid VCC
bias to VCC pin overrides the internal LDO, thus saves power loss on that linear regulator. This configuration
helps to improve overall system level efficiency but requires a valid VCC bias. 3.3-V or 5.0-V rail is the common
choice as VCC bias. With a stable VCC bias, the VIN input range under this configuration can be as low as 2.7 V
and up to 16 V.
The noise of the external bias affects the internal analog circuitry. To ensure a proper operation, a clean,
low-noise external bias, and good local decoupling capacitor from the VCC pin to PGND pin are required. Figure
7-6 shows an example for this split rail configuration.
The VCC external bias current during nominal operation varies with the bias voltage level and also the operating
frequency. For example, by setting the device to skip mode, the VCC pins draw less and less current from the
external bias when the frequency decreases under light load condition. The typical VCC external bias current
under FCCM operation is listed in the Electrical Characteristics to help you prepare the capacity of the external
bias.
Under split rail configuration, VIN, VCC bias, and EN are the signals to enable the part. For start-up sequence,
it is recommended that at least one of VIN UVLO rising threshold and EN rising threshold is satisfied later than
VCC UVLO rising threshold. A practical start-up sequence example is VIN applied first, then the external bias
applied, and then EN signal goes high.

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VIN: 2.7V ± 16V CBOOT

10 VIN BOOT 1
CIN 21 VIN
LOUT VOUT
SW 20
EN
8 EN
CFF, Optional
PGOOD 9 PGOOD Vosns+
RPG_pullup
VCC bias
FB 7
19 VCC COUT
RFB_HS
RMODE
CVCC RFB_LS
4 MODE Vosns-
RTRIP
VSNS- 6
3 TRIP
CSS
SS/
5
2 AGND REFIN
PGND

Figure 7-6. Split Rail Configuration With External VCC Bias

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The TPS548A29 device is a high-efficiency, single-channel, small-sized, synchronous-buck converter. The
device suits low output voltage point-of-load applications with 15-A or lower output current in server, storage,
and similar computing applications. The TPS548A29 features proprietary D-CAP3 mode control combined with
adaptive on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response
DC/DC converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input
voltage ranges from 2.7 V to 16 V, and the VCC input voltage ranges from 4.75 V to 5.3 V. The D-CAP3 mode
uses emulated current information to control the modulation. An advantage of this control scheme is that it does
not require an external phase-compensation network, which makes the device easy-to-use and also allows for a
low external component count. Another advantage of this control scheme is that it supports stable operation with
all low-ESR output capacitors (such as ceramic capacitor and low-ESR polymer capacitor). Adaptive on-time
control tracks the preset switching frequency over a wide range of input and output voltages while increasing
switching frequency as needed during a load-step transient.
8.2 Typical Application
The schematic shows a typical application for TPS548A29. This example describes the design procedure of
converting an input voltage range of 4-V to 16-V down to 2.5-V with a maximum output current of 15 A.

Figure 8-1. TPS548A29Application Circuit Diagram

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8.2.1 Design Requirements

This design uses the parameters listed in Table 8-1.
Table 8-1. Design Example Specifications
DESIGN PARAMETER CONDITION MIN TYP MAX UNIT
VIN Voltage range 4 12 16 V
VOUT Output voltage 2.5 V
ILOAD Output load current 15 A
VRIPPLE Output voltage ripple VIN = 12 V, IOUT = 12 A 10 mVPP
V TRANS Output voltage undershoot and IOUT = 25% to 75% step, 2 A/µs slew rate
50 mV
overshoot after load step
IOVER Output overcurrent 15 A
tSS Soft-start time 5.5 ms
fSW Switching frequency 0.8 MHz
Operating mode Skip-
mode
TA Operating temperature 25 °C

8.2.2 Detailed Design Procedure

The external component selection is a simple process using D-CAP3 mode. Select the external components
using the following steps.
8.2.2.1 Output Voltage Setting Point
The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in Equation 7. Connect
R1 between the FB pin and the output, and connect R2 between the FB pin and VSNS–. The recommended R2
value is 10 kΩ, but it can also be set to another value between the range of 1 kΩ to 20 kΩ. Determine R1 for
TPS548A29 by using Equation 7.

VOUT VINTREF 2.5V 0.6V

R1 u R2 u 10k: 31.7 k:
VINTREF 0.6V (7)

8.2.2.2 Choose the Switching Frequency and the Operation Mode

The switching frequency and operation mode are configured by the resistor on MODE pin. Select one of three
switching frequencies: 600 kHz, 800 kHz, or 1 MHz. Refer to Table 7-1 for the relationship between the switching
frequency, operation mode and RMODE.
Switching frequency selection is a tradeoff between higher efficiency and smaller system solution size. Lower
switching frequency yields higher overall efficiency but relatively bigger external components. Higher switching
frequencies cause additional switching losses which impact efficiency and thermal performance. For this design,
a 243-kΩ resistor is chosen for MODE pin to set the switching frequency to 0.8 MHz and set operation mode as
skip mode.
When selecting the switching frequency of a buck converter, the minimum on-time and minimum off-time must
be considered. Equation 8 calculates the maximum fSW before being limited by the minimum on-time. When
hitting the minimum on-time limits of a converter with D-CAP3 control, the effective switching frequency will
change to keep the output voltage regulated. This calculation ignores resistive drops in the converter to give a
worst case estimation.

VOUT 1 2.5 V 1
fSW max u u 1838 kHz
VIN max tON _ MIN max 16 V 85 ns (8)

Equation 8 calculates the maximum fSW before being limited by the minimum off-time. When hitting the minimum
off-time limits of a converter with D-CAP3 control, the operating duty cycle will max out and the output voltage

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will begin to drop with the input voltage. This equation requires the DC resistance of the inductor, RDCR,
selected in the following step so this preliminary calculation assumes a resistance of 2.2 mΩ. If operating near
the maximum fSW limited by the minimum off-time, the variation in resistance across temperature must be
considered when using Equation 9. The selected fSW of 800 kHz is below the two calculated maximum values.

VIN min VOUT IOUT max u RDCR RDS ON _ HS

fSW max
t OFF _ MIN max u VIN min IOUT max u RDS ON _ HS RDS ON _ LS

8 V 2.5 V 15 A u 2.2 m: 8.2 m:

fSW max 3011 kHz
220 ns u 8 V 15 A u 8.2 m : 2.6 m : (9)

8.2.2.3 Choose the Inductor

To calculate the value of the output inductor (LOUT), use Equation 10. The output capacitor filters the inductor-
ripple current (IIND(ripple)). Therefore, selecting a high inductor-ripple current impacts the selection of the output
capacitor because the output capacitor must have a ripple-current rating equal to or greater than the inductor-
ripple current. On the other hand, larger ripple current increases output ripple voltage, but improves signal-to-
noise ratio and helps to stabilize operation. Generally speaking, the inductance value should set the ripple
current at approximately 15% to 40% of the maximum output current for a balanced performance.
For this design, the inductor-ripple current is set to 30% of 15-A output current. With a 0.8-MHz switching
frequency, 16 V as maximum VIN, and 2.5 V as the output voltage, the Equation 10 calculated inductance is
0.586 µH. A nearest standard value of 0.80 µH is chosen.

VIN max VOUT u VOUT 16 V 2.5 V u 2.5 V

L 0.586 +
IRIPPLE u VIN max u fSW 0.3 u 15A u 16 V u 800 kHz (10)

The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above
peak inductor current before saturation. The peak inductor current is estimated using Equation 12. For this
design, by selecting 4.02 kΩ as the RTRIP, IOC(valley) is set to 14.9 A, thus peak inductor current under maximum
VIN is calculated as 16.65 A.

VIN max VOUT u VOUT 16 V 2.5 V u 2.5 V

IRIPPLE 3.3 A
L u VIN max u fSW 0.8 + u 9u N+] (11)

IRIPPLE 3.3 A
IL PEAK IOUT 15 A 16.65 A
2 2 (12)

IRIPPLE2 3.3 A 2
IL RMS IOUT 2 15 A 2 15.03 A
12 12 (13)

The selected inductance is a XAL7070-801MEB. This has a saturation current rating of 37.8 A, RMS current
rating of 20.8 A and a DCR of 2.29 mΩ max. This inductor was selected for its low DCR to get high efficiency.
8.2.2.4 Set the Current Limit (TRIP)
The RTRIP resistor sets the valley current limit. Equation 14 calculates the recommended current limit target. This
includes the tolerance of the inductor and a factor of 0.85 for the tolerance of the current limit threshold. Equation
15 calculates the RTRIP resistor to set the current limit. The typical valley current limit target is 13.66 A. Round up
to use a valley current limit of 15 A. The closest standard value for RTRIP is 4.02 kΩ.

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1 VIN min VOUT u VOUT

ILIM _ VALLEY IOUT u
2 L u 1 L TOL u VIN min u fSW
1 8 V 2.5 V u 2.5 V
ILIM _ VALLEY 15 A u 13.66 A
2 0.8 µH u 1 0.2 u 8 V u 800 kHz (14)

60000 60000
RTRIP 4.0 k:
ILIM _ VALLEY 15 A (15)

With the current limit set, Equation 16 calculates the typical maximum output current at current limit. Equation 17
calculates the typical peak current at current limit. As mentioned in Section 8.2.2.3, the saturation behavior of the
inductor at the peak current during current limit must be considered. For worst case calculations, the tolerance of
the inductance and the current limit must be included.

1 VIN min VOUT u VOUT 1 8 V 2.5 V u 2.5 V

IOUT _ LIM min ILIM _ VALLEY u 15 A u 16.34 A
2 L u VIN min u fSW 2 0.8 µH u 8 V u 800 kHz (16)

VIN max VOUT u VOUT 16 V 2.5 V u 2.5 V

IL PEAK ILIM _ VALLEY 15 A 18.30 A
L u VIN max u fSW 0.8 µH u 16 V u 800 kHz (17)

8.2.2.5 Choose the Output Capacitor

There are three considerations for selecting the value of the output capacitor.
1. Stability
2. Steady state output voltage ripple
3. Regulator transient response to a change load current
First, the minimum output capacitance should be calculated based on these three requirements. Equation 18
calculates the minimum capacitance to keep the LC double pole below 1/30th the fSW in order to meet stability
requirements. This requirement helps to keep the LC double pole close to the internal zero. Equation 19
calculates the minimum capacitance to meet the steady state output voltage ripple requirement of 10 mV. This
calculation is for CCM operation and does not include the portion of the output voltage ripple caused by the ESR
or ESL of the output capacitors.

2 2
§ 30 · 1 § 30 · 1
COUT _ STABILITY !¨ ¸ u ¨ 2S u 800 kHz ¸ u 0.8 µH 44.5 µF
© 2S u fSW ¹ L © ¹ (18)

IRIPPLE 4.12 A
COUT _ RIPPLE ! 64.4 µF
8 u VRIPPLE u fSW 8 u 10 mV u 800 kHz (19)

Equation 20 and Equation 21 calculate the minimum capacitance to meet the transient response requirement of
75 mV with a 7-A step. These equations calculate the necessary output capacitance to hold the output voltage
steady while the inductor current ramps up or ramps down after a load step.

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§ VOUT ·
L u ISTEP2 u ¨¨ t OFF _ MIN max ¸¸
COUT _ UNDERSHOOT ! © VIN min u fSW ¹
§ VIN min VOUT ·
2 u VTRANS u VOUT u ¨¨ t OFF _ MIN max ¸¸
© VIN min u fSW ¹
§ 2.5 V ·
0.8 µH u 7 A 2 u ¨ 220 ns ¸
© 8 V u 800 kHz ¹
COUT _ UNDERSHOOT ! 99.8 µF
§ 8 V 2.5 V ·
2 u 75 mV u 2.5 V u ¨ 220 ns ¸
© 8 V u 800 kHz ¹ (20)

L u ISTEP2 0.8 µH u 7A 2
COUT _ OVERSHOOT ! 104.5 µF
2 u VTRANS u VOUT 2 u 75 mV u 2.5 V (21)

The output capacitance needed to meet the overshoot requirement is the highest value so this sets the
required minimum output capacitance for this example. Stability requirements can also limit the maximum output
capacitance and Equation 22 calculates the recommended maximum output capacitance. This calculation keeps
the LC double pole above 1/100th the fSW. It is possible to use more output capacitance but the stability must be
checked through a bode plot or transient response measurement. The selected output capacitance is 4 x 47-µF,
6.3-V ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC and AC
bias effects. The selected capacitors derate to 60% their nominal value giving an effective total capacitance of
112.8 µF. This effective capacitance meets the minimum and maximum requirements.

2 2
§ 50 · 1 § 50 · 1
COUT _ STABILITY ¨ ¸ u ¨ S u 800 kHz ¸ u 0.8 µH 494 µF
© S u fSW ¹ L © ¹ (22)

This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored.
If you are using non-ceramic capacitors, as a starting point, the ESR should be below the values calculated
in Equation 23 to meet the ripple requirement and Equation 24 to meet the transient requirement. For more
accurate calculations or if using mixed output capacitors, the impedance of the output capacitors should be used
to determine if the ripple and transient requirements can be met.

VRIPPLE 10 mV
RESR _ RIPPLE 2.5 m:
IRIPPLE 4.1 A (23)

VTRANS 75 mV
RESR _ TRANS 10.7 m:
ISTEP 7A (24)

8.2.2.6 Choose the Input Capacitors (CIN)

The device requires input bypass capacitors between the VIN and PGND pins to bypass the power-stage. The
bypass capacitors must be placed as close as possible to the pins of the IC as the layout will allow. At least 10
µF of ceramic capacitance and 1-µF high frequency ceramic bypass capacitors are required. A 1-μF, 16-V X6S
size 0402 ceramic capacitor on VIN pin 21 is required. A 1-μF, 16-V X6S ceramic capacitor on VIN pin 10 is
required. A 1-μF 16-V X6S ceramic capacitor on the bottom layer is recommended for high current applications.
The high frequency bypass capacitor minimizes high frequency voltage overshoot across the power-stage. The
ceramic capacitors must be high-quality dielectric of X6S or better for their high capacitance-to-volume ratio and
stable characteristics across temperature. In addition to this, more bulk capacitance can be needed on the input
depending on the application to minimize variations on the input voltage during transient conditions.
The input capacitance required to meet a specific input ripple target can be calculated with Equation 25.
A recommended target input voltage ripple is 5% the minimum input voltage, 400 mV in this example. The
calculated input capacitance is 10.07 µF and the minimum input capacitance of 10 µF exceeds this. This
example meets these two requirements with 4 x 22-µF ceramic capacitors.

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§ VOUT · § 2.5 ·
VOUT u IOUT u ¨¨ 1 ¸ 2.5 V u 15 A u ¨ 1
© VIN min ¸¹ © 8 ¸¹
CIN ! 10.07 )
fSW u VIN min u VIN _ RIPPLE 800 kHz u 8 V u 400 mV (25)

The capacitor must also have an RMS current rating greater than the maximum input RMS current in the
application. The input RMS current the input capacitors must support is calculated by Equation 25 and is 6.96 A
in this example. The ceramic input capacitors have a current rating greater than this.

VOUT § VIN min VOUT Iripple2 ·

ICIN RMS u¨ u IOUT 2 ¸
VIN min ¨© VIN min 12 ¸¹

2.5 V § 8 V 2.5 V 4.122 ·

ICIN RMS u¨ u 152 ¸ 6.96 A
8V © ¨ 8V 12 ¸¹
(26)

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high
current, the selection process in the How To Select Input Capacitors For A Buck Converter technical brief is
recommended.
8.2.2.7 Soft Start Capacitor (SS/REFIN Pin)
The capacitor placed on the SS/REFIN pin can be used to extend the soft start time past the internal 1.5-ms soft
start. This example uses a 1.7-ms soft start time and the required external capacitance can be calculated with
Equation 27. In this example, a 100-nF capacitor is used.

ISS u tSS 36 µA u 2.5 ms

CSS 100 nF
VREF 0.6 V (27)

A minimum capacitor value of 1 nF is required at the SS/REFIN pin. The SS/REFIN capacitor must use the
VSNS– pin for its ground.
8.2.2.8 EN Pin Resistor Divider
A resistor divider on the EN pin can be used to increase the input voltage the converter begins its start-up
sequence. To set the start voltage, first select the bottom resistor (REN_B). The recommended value is between 1
kΩ and 100 kΩ. There is an internal pulldown resistance with a nominal value of 6 MΩ and this must be included
for the most accurate calculations. This is especially important when the bottom resistor is a higher value, near
100 kΩ. This example uses a 10-kΩ resistor and this combined with the internal resistance in parallel, results in
an equivalent bottom resistance of 9.98 kΩ. The top resistor value for the target start voltage is calculated with
Equation 28. In this example, the nearest standard value of 20 kΩ is selected for REN_T. When selecting a start
voltage in a wide input range application, be cautious that the EN pin absolute maximum voltage of 6 V is not
exceeded.

REN _ B u VSTART 10 k: u 3.7 V

REN _ T REN _ B 10 k: 20 k:
VENH 1.22 V (28)

The start and stop voltages with the selected EN resistor divider can be calculated with Equation 29 and
Equation 30.

REN _ B REN _ T 10 k: 20 k:
VSTART VENH u 1.22 V u 3.66V
REN _ B 10 k: (29)

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REN _ B REN _ T 10 k: 20 k:
VSTOP VENL u 1.02 V u 3.06 V
REN _ B 10 k: (30)

8.2.2.9 VCC Bypass Capacitor

At a minimum, a 2.2-µF, at least 6.3-V rating, X5R ceramic bypass capacitor is needed on VCC pin located as
close to the pin as the layout will allow.
8.2.2.10 BOOT Capacitor
At a minimum, a 0.1-µF 10-V X5R ceramic bypass capacitor is needed between the BOOT and SW pins located
as close to the pin as the layout will allow. It is good practice to use a 0-Ω resistor in series with BOOT capacitor.
8.2.2.11 PGOOD Pullup Resistor
The PGOOD pin is open-drain so a pullup resistor is required when using this pin. The recommended value is
between 1 kΩ and 100 kΩ.

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8.2.3 Application Curves

100 100

95 95
90
90
85
85
Efficiency (%)

80

Efficiency (%)
80 75
75 70
Vin = 12 V Vout = 0.6 V Vout = 0.6 V
70 800 kHz Vout = 1.0 V 65 Vout = 1.0 V
Vin = 12 V
VCC = 5 V Vout = 1.2 V Vout = 1.2 V
60 800 kHz
65 800 nH Vout = 1.8 V Vout = 1.8 V
FCCM
VCC = 5 V
Vout = 2.5 V 55 Vout = 2.5 V
800 nH
60 Vout = 3.3 V Vout = 3.3 V
50 Skip
Vout = 5.0 V Vout = 5.0 V
55 45
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Output Current (A) D033 Output Current (A) D035
Figure 8-2. Efficiency vs Output Current, VCC = Figure 8-3. Efficiency vs Output Current, VCC =
5.0V External VCC Bias 5.0V External VCC Bias

1050 1050

950 950
Switching Frequency (kHz)

Switching Frequency (kHz)

850 850

750 750

650 650

550 VIN = 12 V 550 Vout = 2.5 V

Vout = 2.5 V 800 nH
450 800 nH 450 VCC = Int
VCC = Int 600 kHz FCCM 600 kHz
350 FCCM 800 kHz 350 Iout = 3 A 800 kHz
1000 kHz 1000 kHz
250 250
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 5 6 7 8 9 10 11 12 13 14 15 16
Output Current (A) D028
Input Voltage (V) D013

Figure 8-4. Switching Frequency vs Output Current Figure 8-5. Switching Frequency vs Input Voltage
1200 2.502
2.498 Vin = 8 V
1100 Vin = 12 V
2.494 Vin = 16 V
1000
Switching Frequency (kHz)

2.49
2.486
Output Voltage (V)

900
2.482
800
2.478
700 2.474
600 2.47
VIN = 12 V 2.466
500
Iout = 3 A 2.462 800 nH
400 800 nH 800 kHz
600 kHz 2.458 VCC = Int
VCC = Int
300 800 kHz 2.454 Skip
FCCM
1000 kHz 2.45
200 0 2 4 6 8 10 12 14 15
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Output Current (A) D010
Output Voltage (V)
Figure 8-6. Switching Frequency vs Output Voltage Figure 8-7. Output Voltage vs Output Current

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2.502 2.502
2.498 Vin = 8 V 2.498 Vin = 8 V
Vin = 12 V Vin = 12 V
2.494 Vin = 16 V 2.494 Vin = 16 V
2.49 2.49
2.486 2.486
Output Voltage (V)

Output Voltage (V)

2.482 2.482
2.478 2.478
2.474 2.474
2.47 2.47
2.466 2.466
2.462 800 nH 2.462 800 nH
800 kHz 800 kHz
2.458 VCC = Int 2.458 VCC = 5 V
2.454 FCCM 2.454 Skip
2.45 2.45
0 2 4 6 8 10 12 14 15 0 2 4 6 8 10 12 14 15
Output Current (A) D039
Output Current (A) D040

Figure 8-8. Output Voltage vs Output Current Figure 8-9. Output Voltage vs Output Current, VCC
= 5.0V External Bias
2.5 2.503
Vin = 8 V Skip 0.1 A
2.496 800 kHz
Vin = 12 V 2.499 FCCM 0.1 A
VCC = Int
2.492 Vin = 16 V FCCM 6 A
800 nH
FCCM 7 A
2.488 2.495
Output Voltage (V)

2.484 Output Voltage (V) 2.491

2.48
2.487
2.476
2.472 2.483
800 nH
2.468 800 kHz
VCC = 5 V 2.479
2.464
FCCM
2.46 2.475
0 2 4 6 8 10 12 14 15 3 5 7 9 11 13 15 16
Output Current (A) D038
Input Voltage (V) D012

Figure 8-10. Output Voltage vs Output Current, Figure 8-11. Output Voltage vs Input Voltage VCC =
VCC = 5.0V External Bias Int
2.5 0.018
Skip 0.1 A
800 kHz FCCM 0.1 A 0.016
VCC = 5 V FCCM 6 A
2.496 800 nH 0.014
FCCM 7 A
Output Voltage (V)

VCC Current (A)

0.012
2.492
0.01

0.008
2.488
0.006
VIN = 12 V
0.004 Vout = 2.5 V
2.484 Iout = 6 A 600 kHz
0.002 800 nH 800 kHz
1000 kHz
2.48 0
3 5 7 9 11 13 15 16 4.55 4.65 4.75 4.85 4.95 5.05 5.15 5.25
Input Voltage (V) VCC Voltage (V) D037
D011

Figure 8-12. Output Voltage vs Input Voltage VCC = Figure 8-13. ICC Current vs External VCC Voltage
5.0V External Bias

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Figure 8-14. Enable Start-Up, Full Load Figure 8-15. Enable Power Down Full Load

Figure 8-16. Enable to Power Up Iout = 0.1 A Figure 8-17. Enable Power Down Iout = 0 A

Figure 8-18. Enable Start-Up, Prebias Figure 8-19. Prebias Power Up

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Figure 8-20. Enable Power Up, Skip Figure 8-21. Enable Power Down, Skip

Figure 8-22. Enable Power Up into Pre-bias, Skip Figure 8-23. Enable Power Down with Pre-bias,
Skip

Figure 8-24. FCCM Mode Load Transient Figure 8-25. Unload Transient

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Figure 8-26. Output Voltage Ripple Figure 8-27. Output Voltage Ripple

Figure 8-28. Output Voltage Ripple Figure 8-29. Output Voltage Ripple

Figure 8-30. Output Voltage Ripple, Skip Figure 8-31. Output Voltage Ripple, Skip

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Figure 8-32. Overcurrent Protection Figure 8-33. Enabled into Overcurrent

80 400
70 Gain 350
Phase
60 300
50 250

Phase (Degrees)
40 200
Gain (dB)

30 150
20 100
10 50
0 0
-10 -50
-20 Vin = 12 V, Vout = 2.5 V, Iout = 15 A -100
-30 800 nH, 800 kHz, VCC = Int -150
-40 -200
1000 2000 5000 10000 100000 1000000
Frequency (Hz) D023

Figure 8-34. Frequency Response, 15-A Load

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9 Power Supply Recommendations

The device is designed to operate from a wide input voltage supply range between 2.7 V and 16 V when the
VCC pin is powered by external bias ranging from 4.75 V to 5.3 V. Both input supplies (VIN and VCC bias) must
be well regulated. Proper bypassing of input supplies (VIN and VCC bias) is also critical for noise performance,
as are PCB layout and grounding scheme. See the recommendations in Section 10.

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10 Layout
10.1 Layout Guidelines
Before beginning a design using the device, consider the following:
• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side
of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid
ground inner plane.
• VIN decoupling capacitors are important for FET robustness. A 1-μF/25-V/X6S/0402 ceramic capacitor on VIN
pin 21 is required. The PGND vias for this decoupling capacitor should be placed so that the decoupling
capacitor is closer to IC than the PGND vias. To lower ESL from via connection, two 8-mil vias are
recommended for the PGND connection to inner PGND plane.
• A 1-μF/25-V/X6S/0402 ceramic capacitor on VIN pin 10 is highly recommended. If this 0402 size capacitor is
not used, the bigger size VIN decoupling capacitors (0603 or 0805 size) are required to be placed as close as
possible to IC pin 10 and pin 11.
• Two 1-μF/25-V/X6S/0402 ceramic capacitors on the bottom layer are recommended for high current
applications (IOUT > 13 A). One of these two capacitors should be centered between VIN pin 10 and pin
21. To have good connection for this capacitor, a VIN copper on the bottom layer and two VIN vias are
needed. The other one can be placed close to IC package just like a mirrored copy to the 0402 capacitor on
top layer.
• At least six PGND vias are required to be placed as close as possible to the PGND pins (pin 11 to pin 15).
This minimizes parasitic impedance and also lowers thermal resistance.
• Place the VCC decoupling capacitor (2.2-μF/6.3-V/X6S/0402 or 2.2-μF/6.3-V/X7R/0603) as close as possible
to the device. Ensure the VCC decoupling loop is smallest.
• Place a BOOT capacitor as close as possible to the BOOT and SW pins. Use traces with a width of 12 mil or
wider to route the connection. TI recommends using a 0.1-µF to 1-µF bootstrap capacitor with a 10-V rating.
• The PCB trace, which connects the SW pin and high-voltage side of the inductor, is defined as switch node.
The switch node must be as short and wide as possible.
• Always place the feedback resistors near the device to minimize the FB trace distance, no matter single-end
sensing or remote sensing.
– For remote sensing, the connections from the FB voltage divider resistors to the remote location should
be a pair of PCB traces with at least 12-mil trace width, and should implement Kelvin sensing across a
high bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must be
connected to VSNS– pin. The VOUT connection of the remote sensing signal must be connected to the
feedback resistor divider with the lower feedback resistor terminated at VSNS– pin. To maintain stable
output voltage and minimize the ripple, the pair of remote sensing lines should stay away from any noise
sources such as inductor and SW nodes, or high frequency clock lines. It is recommended to shield the
pair of remote sensing lines with ground planes above and below.
– For single-end sensing, connect the higher FB resistor to a high-frequency local bypass capacitor of 0.1
μF or higher, and short VSNS– to AGND with shortest trace.
• This device does not require a capacitor from rgw SS/REFIN pin to AGND, thus it is not recommenced
to place a capacitor from SS/REFIN pin to AGND. If both CSS/REFIN-to-VSNS– and CSS/REFIN-to-AGND
capacitors exist, place CSS/REFIN-to-VSNS– more closely with shortest trace to VSNS– pin.
• Pin 2 (AGND pin) must be connected to a solid PGND plane on inner layer. Use the common AGND via to
connect the resistors to the inner ground plane if applicable.
• See Figure 10-1 for the layout recommendation.

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10.2 Layout Example

Vosns+

Vosns-

0402

0402

0402
8/20
Via down to connect to solid
8/20
0402 PGND plane on inner layer
0402

SS/REFIN
8/20
8/20

PGOOD

VSNS-

MODE

0603
AGND
2x VIN-to-PGND decoupling

BOOT
TRIP
capacitors on bottom layer

EN
FB
8/20

PGND

1
8/20

0402
8/20 8/20 8/20 8/20 8/20
SW
VIN VIN
10

21
SW

20
8/20 8/20
0402
0402

0402
0805

0805

PGND 11

PGND 12
PGND 13
PGND 14
PGND 15
PGND 16
PGND 17
PGND 18

VCC 19
8/20 8/20 8/20 8/20

8/20 8/20 8/20 8/20 8/20

0603 LOUT
8/20 8/20 8/20 8/20

8/20 8/20 8/20 8/20 8/20

0402
8/20 8/20

PGND 8/20 8/20

0805
8/20 8/20

8/20 8/20

VOUT
0805
8/20 8/20

Figure 10-1. Layout Recommendation

10.2.1 Thermal Performance On TI EVM

Test conditions:
fSW = 800 kHz, VIN = 12 V, VCC = Int LDO, VOUT = 1 V, IOUT = 15 A, Inductor LOUT = 0.8 µH (2.29 mΩ typ), COUT
= 6 × 22 µF (1206/6.3 V/X7R), no RBOOT, no RC Snubber
SP1 (IC): 68.1°C, SP2 (Inductor): 49.3°C

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Figure 10-2. Thermal Image At 25°C Ambient

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11 Device and Documentation Support

11.1 Documentation Support
11.1.1 Related Documentation
• Texas Instruments, Optimizing transient response of internally compensated dc-dc converters with
feedforward capacitor
• Texas Instruments, Non-isolated point-of-load solutions for VR13.HC in rack server and datacenter
applications
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
D-CAP3™ and Eco-mode™ are trademarks of TI.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 43

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 PACKAGE OPTION ADDENDUM

www.ti.com 14-Feb-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS548A29RWWR ACTIVE VQFN-HR RWW 21 3000 RoHS & Green Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 T548A29

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Nov-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS548A29RWWR VQFN- RWW 21 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q1
HR

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Nov-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS548A29RWWR VQFN-HR RWW 21 3000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RWW0021A VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
B 3.1 A
2.9

PIN 1 4.1
INDEX AREA 3.9

C0.15
PIN 1 IDENTIFICATION
(OPTIONAL)

1 MAX C

SEATING PLANE
0.05 PKG
0.00 0.08 C
0.4
0.3
3X 0.35
0.25
REF 0.15
10 (0.2) TYP
9
11
12X 0.4
8
3X 1.8
1.6

3.25
2X 3.05
3.4 2X
PKG 14X 0.25
0.15
2.4 0.1 C A B
0.05 C

2 18
4X 0.5
1
19

21 20
4X 0.35
0.25
PIN 1 ID
3X 0.3
(OPTIONAL) 0.1 C A B
18X 0.6
0.4 0.05 C 4223950/C 04/2019
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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 EXAMPLE BOARD LAYOUT
RWW0021A VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD
(2.7)

3X (0.3)
21 20 18X (0.7)
4X (0.3)

1
19
14X (0.2)
4X (0.5)
2
18

EXPOSED METAL

PKG
2X 2X
(3.4) (2.4)

12 3X
8 (1.9)
12X (0.4)
11
9
(0.35)
(R0.05) TYP
10
3X (0.3)

PKG

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED
SCALE: 20X

0.05 MAX 0.05 MAX

EXPOSED METAL
ALL AROUND EXPOSED METAL ALL AROUND

SOLDER MASK METAL UNDER SOLDER MASK

METAL EDGE
OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4223950/C 04/2019

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
RWW0021A VQFN-HR - 1 mm max height
PLASTIC QUAD FLAT-NO LEAD

(2.7)

PKG

21 20 18X (0.7)
4X (0.3)

1
19
4X (0.5)
2
18

14X (0.2)

2X 2X PKG
(3.4) (2.4)
3X
(0.73)

12 3X
8 (1.05)
12X (0.4)
11
9
(0.35)
(R0.05) TYP
10 6X
(0.85)
6X (0.3)

(0.3)

SOLDER PASTE EXAMPLE

BASED ON 0.1mm THICK STENCIL

EXPOSED PAD
89% PRINTED COVERAGE BY AREA
SCALE: 20X

4223950/C 04/2019

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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