OCR ‘Odor Cambdge ard 88 Ae OCR enddoeted teatbook OCR AS and A Level Computer Science 1. PG ONLINEOCR AS and A Level Computer Science P.M. Heathcote R.S.U. Heathcote Published by PG Online Limited The Old Coach House 36 Main Road Tolpuddle Dorset pT2 7EW United Kingdom eS [email protected] www. pgonline.co.uk PG ONLINE 2016Acknowledgements We are grateful to the OCR (Oxford Cambridge and RSA Examinations) for permission to use ‘questions from past papers, ‘The answers in the Teacher's Supplement are the sole Fesponsibility of the authors and have neither been provided nor approved by the examination board. ‘We would also like to thank the following for permission to reproduce copyright photographs: Screenshots of Arriva Bus App © Arriva PLC Colossus photograph © The Nationel Archives Google Maps ‘StreetView’ © Google 2015 ‘Screenshot from Raboform website © Roboform Alan Turing © By kind permission of the Provost and Fellows, King's College, Cambridge from Archives Centre, King's College, Cambridge. AMT/K/7/12 ‘Trans-continental Internet connections © Telegeography Internet registries map © Ripe NCC thetrainline.com screenshot © by kind permission of thetrainline.com ‘Other photographic images © Shutterstock Graphics: PG Online Ltd Cover picture © ‘Away Day’ 2015 Mixed media on canvas 61x61¢m Reproduced with the kind permission of Hilary Tumbull www hilaryturnbull.co.uk Cover design and artwork by PG Online Ltd ‘Typeset by PG Online Ltd First edition 2016, reprinted April 2017, June 2017 ‘A catalogue entry or this book is available from the British Library ISBN: 978. 1-910523-05-6 Copyright © PM.Heathcote and A.S.UMeathecte 2016, All cights reserved No part of this publication may be reproduced, stored in a retrieval system, or transmitted In any form or by any means without the prior written permission af the copyright owner Printed on FSC? certiied paper Printed in Great Britain by Pen 0rd Press Limited ‘Sound in Great Britain by Camtaian Printers LimitedPreface The aim of this book is to provide detailed coverage of the topics in the new OCR AS and A Level Computer Science specification. ‘The book is divided into twelve sections and within each section, each chapter covers material that can comfortably be taught in one or two lessons. Material that is applicable only to the second year of the full A Level is clearly marked. Sometimes this may include an entire chapter and at other times, just a small part of a chapter. Each chapter contains exercises and questions, some new and some from past examination questions. Answers to all these are available to teachers only in a free Teacher's Pack which can be ordered from ‘our website www.pgontine.co.uk. This book has been written to cover the topics which will be examined in the written papers at both AS and A Level. Sections 10, 11 and 12 relate principally to problem solving skills, with programming techniques covered in sufficient depth to allow students to answer questions in Component 02. Pseudocode, rather than any specific programming language, is used in the algorithms given in the text. Sample Python programs which implement many of the algorithms are included in a folder with the ‘Teacher's Pack. This resource is endorsed by OCR for use with specifications HO46/H446 AS Level Computer Science and A Level Computer Science. In order to gain OCR endorsement, this resource has undergone an independent quality check. Any references to assessment and/or assessment preparation are the publisher's interpretation of the specification requirements and are not endorsed by OCR. OCR recommends that a range of teaching and learning resources are used in preparing learners for assessment. OCR has not paid for the production of this resource nor does OCR receive any royalties from its sale. For more information about the endorsement process, please visit the OCR website, www.ocr.org.uk.Contents Section 1 ‘Components of a computer 1 Chapter 1 = Processor components 2 Chapter 2 Processor performance 7 Chapter 3 = Types of processor 10 Chapter 4 Input devices 16 Chapter5 Output devices 20 Chapter6 Storage devices 25 Section 2 Systems software 29 Chapter 7 — Functions of an operating system 30 Chapter 8 — Types of operating system 36 Chapter9 = The nature of applications 39 Chapter 10 Programming language translators 44 Section 3 Software development 51 ‘Chapter 11. Systems analysis methods 62 ‘Chapter 12 Writing and following algorithms 57 Chapter 13 Programming paradigms 64 Chapter 14 Assembly language 69 Section 4 Exchanging data 74 Chapter 15 Compression, encryption and hashing 75 Chapter 16 Database concepts 82 Chapter 17 Relational databases and normalisation 88 Chapter 18 Introduction to SQL 95 Chapter 19 Defining and updating tables using SQL 101 Chapter 20 Transaction processing 106Section 5 Networks and web technologies 110 Chapter 21 Structure of the Internet 1 Chapter 22 Internet communication 119 Chapter 23 Network security and threats 126 Chapter 24 HTML and CSS 130 Chapter 25 Web forms and JavaScript 136 Chapter 26 Search engine indexing 142 Chapter 27 Client-server and peer-to-peer 147 Section 6 Data types 154 Chapter 28 Primitive data types, binary and hexadecimal 165 Chapter 29 ASCII and Unicode 159 Chapter 30 Binary arithmetic 162 Chapter 31 Floating point arithmetic 167 Chapter 32 Bitwise manipulation and masks 174 Section 7 Data structures. 178 Chapter 33 Arrays, tuples and records 179 Chapter 34 Queues 184 Chapter 35 _Lists and linked lists 190 Chapter 36 Stacks 200 Chapter 37 Hash tables 204 Chapter 38 Graphs 209 Chapter 39 Trees 214Section 8 Boolean algebra 222 Chapter 40 Logic gates and truth tables 223 Chapter 41 Simplifying Boolean expressions 228 Chapter 42 Karnaugh maps. 233 Chapter 43 Adders and D-type flip-flops 238 Section9 Legal, moral, ethical and cultural issues 242 Chapter 44 Computing related legislation 243 Chapter 45 Ethical, moral and cultural issues 249 Chapter 46 Privacy and censorship 255 Section 10 ‘Computational thinking 259 Chapter 47 Thinking abstractly 260 Chapter 48 = Thinking ahead 265 Chapter 49 Thinking procedurally 268 Chapter 50 = Thinking logically, thinking concurrently 272 Chapter 51 Problem recognition 277 Chapter 52 Problem solving 282Section 11 Programming techniques 287 Chapter 53 Programming basics 288 Chapter 54 = Selaction 294 Chapter 55 Iteration 299 Chapter 56 Subroutines and recursion 303 Chapter 57 Use of an IDE 313 Chapter 58 Use of object-oriented techniques 319 Section 12 Algorithms. 327 Chapter 59 Analysis and design of algorithms 328 Chapter 60 Searching algorithms 334 Chapter 61 Bubble sort and insertion sort 340 Chapter 62 Merge sort and quick sort 345, Chapter 63 Graph traversal algorithms 361 Chapter 64 Optimisation algorithms 358 Index 364 vilvillSection 1 Components of a computer In this section: Chapter 1 Processor components Chapter 2 Processor performance Chapter 3 Types of processor Chapter 4 Input devices Chapter 5 Output devices Chapter 6 Storage devices 20 25‘SECTION 1 - GOMPONENTS OF A COMPUTER Chapter 1 — processor components Objectives * Describe the function of the ALU and Control Unit * Describe the Fetch-Execute cycle and the role of the following registers: Program Counter Accumulator Memory Address Register Memory Data Register Current Instruction Register 20000 The Central Processing Unit (CPU) The CPU, also known simply as the processor, has a number of different components which enable it to carry out its task of executing instructions. These components include: * control unit ° buses © arithmetic/logic unit (ALU) * dedicated registers Control Unit The Control Unit controls and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices. It accepts the next instruction, decodes it into several sequential steps such as fetching addresses and data from memory, manages its execution and stores the resulting data back in memory of registers. A bus is a set of parallel wires connecting two or more components of a computer. It typically consists of 8, 16, 32 oF 64 lines. The processor is connected to main memory by three separate buses. When the CPU wishes to access particular main memory location, it sends this address to memory on the address bus. The data in that location is then returned to the CPU on the data bus. Control signals are sent along the control bus. In the figure below, you can see that data, address and control buses connect the processor, memory and I/O controllers. These three buses are known collectively as the system bus. Each bus is a shared transmission medium, so that only one device can transmit along a bus at any one time. Data and control signals travel in both directions between the processor, memory and I/O controllers. Addresses, on the other hand, travel only one way along the address bus: the processor sends the address of an instruction, or of data to be stored or retrieved, to memory or to an /O controller.CHAPTER 1 - PROCESSOR COMPONENTS Direction of transmission along the buses Control bus The control bus is a bi-directional bus, meaning that signals can be carried in both directions. The data and address buses are shared by all components of the system. Control lines must therefore be provided to ensure that access to and use of the data and address buses by the different components of the system does not lead to conflict. The purpose of the control bus is to transmit command, timing and specific status information between Ee system components Control lines include: * Bus Request: indicates that a device is requesting the use of the data bus * Bus Grant: indicates that the CPU has granted access to the data bus * Memory Write: causes data on the data bus to be written into the addressed location * Memory Read: causes data from the addressed location to be placed on the data bus ‘* Interrupt request: indicates that a device is requesting access to the CPU * Clock: used to synchronise operations Data bus ‘The data bus, typically consisting of 8, 16, 32 or 64 separate lines, provides a bi-directional path for moving data and instructions between system components. Address bus Memory is divided up internally into units called words. A word is a fixed size group of digits, typically 16, 82 or 64 bits, which is handled as a unit by the processor, and different types of processor have different word sizes. Each word in memory has its own specific address. The address bus transmits the memory addresses of words that are used as operands in program instructions, so that the data can be retrieved and sent back to the processor. When an instruction has been performed and the result is to be stored at a particular memory location, it is transmitted via the data bus.‘SECTION 1 - COMPONENTS OF A COMPUTER Arithmetic-Logic Unit (ALU) ‘The ALU performs arithmetic and logical operations on the data. It can perform instructions such as ADD, SUBTRACT, MULTIPLY, DIVIDE on fixed cr floating point numbers. It can also perform shift operations, shifting bits to the left or right within a register. It can carry out Boolean logic operations, comparing two values and using operators such as AND, OR, NOT, XOR. Registers Registers are special memory cells that operate at very high speed. All arithmetic, logical or shift operations take place in registers and there are typically up to 16 general purpose registers in the CPU. However, although most modern computers have many registers, some special-purpose processors still use a single accumulator, in order to simplify the design. The accumulator takes the place of the general purpose registers. For simpticity, we will assume that all calculations take place in a single register called the accumulator. Carrying out instructions one after the other requires many different pieces of information to be held. As well as the accumulator, there are several other special-purpose registers: * the program counter (PC), which holds the address of the next instruction to be executed. ‘This may be the next instruction in a sequence of instructions, or, if the current instruction is a branch or jump instruction, the address to jump to, copied from the current instruction register (CIR) to the PC. * the current instruction register (CIR), which holds the current instruction being executed, divided into operand and opcode. * the memory address register (MAR), which holds the address of the memory location from which data (or an instruction) is to be fetched or to which data is to be written. ‘the memory data register (MDR), which is used to temporarily store the data read from or written to memory. tt is also sometimes known as the memory buffer register. A simplified diagram showing the connections between these registers is shown below. ‘Special-purpose registers in the processorCHAPTER | - PROCESSOR COMPONENTS: The Fetch-Decode-Execute cycle ‘The sequence of operations involved in executing an instruction can be divided inte three phases — fetching, decoding and executing it. This cycle is repeated over and over as each instruction of the program is executed. Sa Dire How the registers are used in the Fetch-Execute cycle (Fetch phase) 4. The address of the next instruction is copied from the program counter (PC) to the memory address register (MAR). 2, The instruction held at that address is copied to the memory data register (MDA). Simultaneously, the ch content of the PC is incremented so that it holds the address of the next instruction. 3. The contents of the MDR are copied to the current instruction register (CIR). (Decode phase) 4, The instruction held in the CIR is decoded. The instruction is split into opcode and operand and the opcode is used to determine the type of instruction and what hardware to use to execute it. The operand holds either: © the address of the data to be used with the operation, which is then copied to the MAR, or * the actual data to be operated on, which will be copied to the MDR_ * the data to be operated on may be passed to the ALU/accumulator (Execute phase) 5. The appropriate instruction/opcode is carried out on the operand.SECTION 1 - COMPONENTS OF A COMPUTER Exercises 1. (a) In the context of computer architecture, explain what is meant by the term bus. 2) {b) Name three control ines used by the control bus. 8] (c) What is the data bus used for? a 2. Describe the purpose of each of the following parts of a computer. () Memory unit 13] (i) ALU (3) OCR FA451/01 Qu 5 June 2013 3. The figure below shows an incomplete diagram of the components of a processor. Coy (@) Provide full names for the components numbered 1 to 5 by completing the table below. Component number ‘Component name 1 el s a 6) (b) The figure below is an incomplete flowchart of the Fetch-Execute cycle. Describe the missing steps. 15] CHEHH J i step 5 Execute insincionCHAPTER 2 - PROCESSOR PERFORMANCE Chapter 2 — Processor performance Objectives * Describe the factors affecting the performance of the CPU: clock speed, number of cores, cache @ + Understand the use of pipelining in a processor to improve efficiency © Understand how address and data bus size relates to assembly language programs Factors affecting processor performance The main factors affecting processor performance are: * Clock speed The number of cores, or duplicate processors, linked together on a single chip * The amount and type of cache memory Clock speed ‘The system clock generates a series of signals, switching between 0 and 1 several million times per second and synchronising CPU operations. Each CPU operation starts as the clock changes from 0 to 1 {or in some systems from 1 to 0), and the CPU cannot perform operations faster than the clack cycle (the time the clock takes to go from 0 to 1 and back to 0). All processor activities begin on a clock pulse, although some activities may take more than one clock cycle to complete. One clock cycle per second = 1 Hertz (Hz), and clock speed is measured in Gigahertz (Ghz), about 1 billion cycles per second. Typical speeds for a PC are between 2 and 4 GHz. The greater ‘the clock speed, the faster instructions will be executed. Number of cores Ina traditional computer (von Neumann machine), instructions are fetched and executed one at a tine ina serial manner. However, many computers nowadays have multiple cores. A dual-core processor has two processors linked together in the same integrated circuit, and a quad-core computer has four linked processors. Each core is theoretically able to process a different instruction at the same time with its own fetch-execute cycle, making the processor two or even four times faster with a quad-core chip. However, although a dual-core processor has twice the power, it does not always perform twice as fast, because the software may not always be able to take full advantage of both processors. Amount and type of cache memory Cache is a small amount of expensive, very fast memory inside the CPU. When an instruction is fetched from main memory it is copied into the cache so if it is needed again soon after, it can be fetched from ‘cache, which is much quicker than going back to main memory. As cache fills up, unused instructions or data still being held are replaced with more recent ones. abdSECTION 1 - COMPONENTS OF A COMPUTER There are different “levels” of cache: * Level 1 cache is extremely fast but small (between 2-64KB) * Level 2 cache is fairly fast and medium-sized (256KB-2MB) * Some CPUs also have Level 3 cache : Pipelining Pipelining is a technique used by some processors to improve performance. Without pipelining, the steps in the Fetch-Execute cycle take place one after the other. While the next instruction is being fetched, the ALU, the arithmetic part of the processor, is idle. Using pipelining, the computer architecture allows the next instructions to be fetched at the same time as the processor is performing arithmetic or logic operations, holding them in a butfer close to the processor until the instruction can be performed. Processor pipelining is sometimes divided into an instruction pipeliné and an arithmetic Pipeline. ‘The instruction pipeline consists of the stages in which an instruction is moved through the processor, including its being fetched, buffered and then executed. The arithmetic pipeline represents the parts ‘of an arithmetic operation that can be broken down and overlapped as they are performed. Pipelining is now common in microprocessors used in personal computers. Intel's Pentium chip uses Pipelining to execute as many as six instructions simultaneously. ® Words and word size Address bus Each word, or group of bytes, in memory has its own specific address. When the processor wishes to read a word of data from memory, it first puts the address of the desired word on the address bus. The width of the address bus determines the maximum possible memory capacity of the system, For example. if the address bus consisted of only 8 fines, then the maximum address it could transmit would be (in binary) 11111117 or 255, giving a maximum memory capacity of 256 {including address 0). A system with a 32-bit address bus can address 2°° (4,294,967,296) memory locations giving an addressable memory space of 4GIB. (This is the memory capacity of an average PC in 2016.)‘CHAPTER 2 - PROCESSOR PERFORMANCE Data bus ‘The data bus transmits the data held in a word of memory, between processor components and memory. The largest operand (which is either an address or an actual value) that can be held in a word is therefore related to the size of the data bus. If the data bus is 16 bits wide, a word cannot hold an integer greater than 2'° -1, or more than two characters. A wider date bus can transmit larger values, or more characters ata time, or allow more bits per instruction. How this relates to assembly language The basic structure of a machine code instruction in a computer with a 16-bit word may take the format shown below: Operation code Operand{s) In assembly language, the operation code (opcode) will be expressed as a mnemonic such as ADD, SUB, LDA (load into the accumulator) etc. With only six bits for the opcode, there cannot be more than 2° different instructions. The operand has to be held in only 8 bits. This would clearly not be practical in a general purpose computer which is more likely to have a word size of 32, 64 or 128 bits. Exercises 1. Name and describe briefly three of the main factors affecting processor performance. 2. The program below is written in a fow-level language. AB2F ;Load value 2F into accumulator BCS5D ;Store contents of accumulator at address 5D E402 ;Add value 2 to accumulator BCEF ;Store contents of accumulator at address FF AC61 ;Load accumulator with contents of address 61 BC4A ;Store contents of accumulator at address 4A {a) What is the name of this language? (©) The machine for which this program is written has limited addressing capability. What are the highest and lowest memory addresses that can be addressed by this machine? (©) What is the width of the address bus in this machine? | fl 2) o]‘SECTION 1 - COMPONENTS OF A COMPUTER Chapter 3 — Types of processor ‘Objectives * Describe von Neumann, Harvard and contemporary processor architecture * Describe the differences between, and uses of, CISC and RISC processors '@ > Describe GPUs and their uses * Describe muiticore and parallal systems Memory and the stored program concept Computers as we know them were first built and developed in the 1940s and 50s, and two of the early pioneers were Alan Turing and John von Neumann. The von Neumann architecture specifies the basic components of the computer and processor in which a shared memory and bus is used for both data and instructions. ‘The stored progam concept can be defined as follows: machine code instructions are fetched and executed serially by a processor that performs arithmetic and logical operations. * Aprogram must be resident in main memory to be executed * The machine code instructions are felched from memory one at a time, decoded and executed in the processor Virtually all computers today are built on this principle, and so the general structure as shown in the figure ‘below is sometimes referred to as the von Neumann machine. The von Neumann machine Memory oO 1 2 Instruction 3 Instruction Data Data The stored program concept In a von Neumann machine, the same data bus is used to transfer both data and instructions. ‘Similarly, a single address bus is used to transfer the addresses of data and instructions. The same word length is used for all memory, whether it hoids data or instructions.‘CHAPTER 3 — TYPES OF PROCESSOR: Harvard architecture ‘The Harvard architecture is a computer architecture with physicaly separate memories for instructions. and data. Harvard architecture is used extensively with embedded Digital Signal Processing (DSP) systems, DSP applications include audio and speech signal processing, sonar and radar signal processing, biomedical signal processing, seisrric date processing and digital image processing. * The two different memories can have different characteristics; for example, in embedded systems instructions may be held in read-only memory while data memory requires read-write memory * In some systems, there is much more instruction memory than data memory so a larger word size is used for instructions * the instruction address bus may be wider than the data bus Embedded systems include special-purpose computers built into devices often operating in real time, such as those used in navigation systems, traffic lights, aircraft flight control systems and simulators. Harvard architecture can be faster than von Neumann architecture because data and instructions can be fetched in parallel instead of competing for the same bus. <> Ea Harvard architecture Comparison of von Neumann and Harvard architectures Von Neumann architecture Harvard architecture Used in conventional processors in PCs, servers and embedded systems with only control functions Used in digital signal processing and in embedded systems, mobile communication systems, audio, speech and image processing systems Data and programs share the same memory Instructions and data are held in separate memories One bus is used to transfer data and instructions Parallel data and instruction buses may be used Programs can be optimised in size Programs tend to be large sh)‘SECTION 1 - COMPONENTS OF A COMPUTER Contemporary processor architectures Modern high-performance CPU chips incorporate aspects of both von Neumann and Hervard architecture. In one design, there is one main memory for holding both data and instructions, but CPU cache memory is divided into an instruction cache and a data cache. Harvard architecture is used as the CPU accesses the cache. Some digital signal processors such as Texas Instruments TMS320 C55x have multipie parallel data buses (two write, three read) and one instruction bus. Complex Instruction Set Computers (CISC) In the older CISC architecture used by early generations of computer, a large instruction set is used to accomplish tasks in as few lines of assembly language as possible. The processor hardware is capable of understanding and executing the series of sub-tasks that make up a single instruction. Complex instructions are built into the machine's hardware, and the distinguishing feature of a CISC instruction is that it combines a “load/store” instruction with the instruction that carries out the actual calculation. For example, to multiply two values held in different memory locations A and B, storing the result in A, a processor using several general purpose registers would load each of the values into a separate register, carry out the multiplication and then store the result back in A. The assembly language instruction for a CISC processor might be written something like MULT A, B ACISC processor has in its instruction set a single instruction that will do the loading, multiplication and storing of the result. The instruction is equivalent to the high level instruction a = a * b. One advantage of CISC architecture is that the compiler has very little work to do to translate a high-level language statement into machine code. Because the code is relatively short, very litle RAM is required to ‘store the instructions. A disadvantage of CISC was that many specialised instructions had to be built into the hardware even though only about 20% of them were used in the average program. Reduced Instruction Set Computers (RISC) The opposite approach is adopted in the more modern RISC architecture. Only simple instructions, each taking one clock cycle, can be executed. Thus the multiplication instruction described above might be written: LDA RL, A LDA R2, B MULT Rl, R2 STO RL A The RISC strategy has the disadvantage that the compiler has to do more work to translate high-level code into machine code, and more RAM is required to store the machine code instructions. However, because each instructions takes the same amount of time, i.e. one clock cycle, pipelining is Possible, and the four instructions will execute at least as fast as the single CISC instruction. RISC has largely replaced CISC as a processor design, but CISC is still used for microcontrollers and embedded systems.