Dosilicon Confidential PN: FMND4GXXX3F

FMND4GXXX3F
3V/1.8V, x8/x16 4G-BIT NAND FLASH

Rev.03 (Jul 10, 2020) 1

 Dosilicon Confidential PN: FMND4GXXX3F

Documents title
4Gbit (512Mx8Bit, 256Mx16Bit) NAND FLASH

Revision History
Revision History Draft date Remark
No.
0.0 Initial Draft Nov 15, 2019 preliminary
0.1 Modify read ID tables Dec 03, 2019
0.2 Add block0 is valid block description Jan 17, 2020
0.3 Update tREA time Jul 10, 2020

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 Dosilicon Confidential PN: FMND4GXXX3F
FEATURES
■ LEGACY/ONFI 1.0 COMMAND SET
■ x8/x16 I/O BUS
■ FAST BLOCK ERASE
－ NAND Interface
－ Block size :
－ ADDRESS / DATA Multiplexing
x8 : (256K + 16K) bytes
x16: (128K+8K) words
■ SUPPLY VOLTAGE
－ Block erase time : 2ms (Typ)
－ VCC = 1.8/2.7/3.3 Volt core supply voltage for Program,
Erase and Read operations ■ MEMORY CELL ARRAY
－ x8 : (4K + 256) bytes x 64 pages x 2048 blocks
■ PAGE READ / PROGRAM
－ x16: (2K + 128) words x 64 pages x 2048 blocks
－ x8 : (4096+256 spare) byte
－ x16: (2048+128 spare) word page
■ ELECTRONIC SIGNATURE
－ Synchronous Page Read Operation
－ Manufacturer Code
－ Random access : 25us (Max)
－ Device Code
－ Serial access : 30ns (1.8V)
20ns (2.7/3.0V) ■ STATUS REGISTER
－ Page program time : 200us (Typ)
■ HARDWARE DATA PROTECTION
■ PAGE COPY BACK
－ Fast data copy without external buffering ■ DATA RETENTION
－ 100K Program / Erase cycles
■ CACHE PROGRAM － Data retention : 10 Years(4bit/512byte ECC)
－ Internal buffer to improve the program throughput － Block zero is a valid block and will be valid for at least
1K program-erase cycles with ECC

■ READ CACHE

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 Dosilicon Confidential PN: FMND4GXXX3F

Part Numbering System

FM

Dosilicon
Memory

Product Family
ND : NAND

Package Type
Density 0 : Bare Die
28 : 128Mb W : KGD
2
56 : 256Mb A : 12 x 20 mm (TSOP1 48) H-ROHS & Halogen Free
2
12 : 512Mb B : 12 x 17 mm (ULGA 52) H-ROHS & Halogen Free
2
1G : 1Gb C : 9 x 9 mm (48 FBGA) H-ROHS & Halogen Free
2G : 2Gb D
2
: 9 x 11 mm (63 FBGA) H-ROHS & Halogen Free
4G : 4Gb F
2
: 6.5 x 8 mm (67 FBGA) H-ROHS & Halogen Free
8G : 8Gb
6G : 16Gb
Temperature
C : Commercial (0°C~70°C)
Organization E : Extended (-25°C~85°C)
08 : x8 I : Industrial (-40°C~85°C)
16 : x16
Generation
F
Operation Voltage
U : 3.3V
L : 2.5V
S : 1.8V Classification
1 : SLC S/B
2 : MLC S/B
3 : SLC L/B
4 : MLC L/B

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FEATURES................................................................................................................................................................... 3
1 SUMMARY DESCRIPTION................................................................................................................................... 6
1.1 Product List .................................................................................................................................................... 6
1.2 Pin description ................................................................................................................................................ 8
1.3 Functional block diagram ............................................................................................................................... 9
1.4 Address role ................................................................................................................................................. 10
1.5 Command Set .............................................................................................................................................. 11
2 BUS OPERATION ...............................................................................................................................................12
2.1 Command Input. ........................................................................................................................................... 12
2.2 Address Input. .............................................................................................................................................. 12
2.3 Data Input. .................................................................................................................................................... 12
2.4 Data Output. ................................................................................................................................................. 12
2.5 Write Protect. ............................................................................................................................................... 12
2.6 Standby. ....................................................................................................................................................... 12
3 DEVICE OPERATION .........................................................................................................................................13
3.1 Page Read. .................................................................................................................................................. 13
3.2 Read Cache ................................................................................................................................................. 13
3.3 Page Program. ............................................................................................................................................. 13
3.4 Copy-Back Program. .................................................................................................................................... 14
3.5 Cache Program ............................................................................................................................................ 14
3.6 Block Erase. ................................................................................................................................................. 15
3.7 Read Status Register. .................................................................................................................................. 15
3.8 Read Status Register field definition ............................................................................................................ 15
3.9 Read ID. ....................................................................................................................................................... 16
3.10 Reset. ......................................................................................................................................................... 17
3.11 Read Parameter Page ............................................................................................................................... 18
3.12 Parameter Page Data Structure Definition................................................................................................. 18
4 Device Parameters ..............................................................................................................................................20
5 Timing Diagrams .................................................................................................................................................23
6 Bad Block Management ......................................................................................................................................36
7 Supported Packages ...........................................................................................................................................38

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1 SUMMARY DESCRIPTION

FMND4GXXX3F is a 512Mx8bit with spare 32Mx8 (x8), 256Mx16bit with spare 16Mx16(x16) bit capacity.
The device is offered in 3.3/1.8 Vcc Power Supply, and with x8 and x16 I/O interface.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while
old data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series
connected Flash cells.
Program operation allows the 4352-byte page writing in typical 200us and an erase operation can be performed in
typical 2 ms on a 256K-byte block.
Data in the page can be read out at 20ns cycle time per word (2.7/3V version), and at 30ns cycle time per word
(1.8V version). The I/O pins serve as the ports for address and data input/output as well as command input. This
interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of
footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data. The modify operations can be locked using the WP# input
pin.
This device supports ONFI 1.0 specification.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with
multiple memories the RB# pins can be connected all together to provide a global status signal.

The FMND4GXXX3F is available in the following packages : 48 - TSOP1 12x20 mm package, FBGA63 9x11 mm.

1.1 Product List

PART NUMBER ORGANIZATION VCC RANGE PACKAGE
FMND4G08S3F X8 1.7 – 1.95 Volt VFBGA, TSOP
FMND4G16S3F X16 1.7 – 1.95 Volt VFBGA, TSOP
FMND4G08L3F X8 2.5 – 3.0 Volt VFBGA, TSOP
FMND4G16L3F X16 2.5 – 3.0 Volt VFBGA, TSOP
FMND4G08U3F X8 2.7 – 3.6 Volt VFBGA, TSOP
FMND4G16U3F X16 2.7 – 3.6 Volt VFBGA, TSOP

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 Dosilicon Confidential PN: FMND4GXXX3F

Vcc

DQ0-DQ7 (x8)

CE#
DQ0-DQ15 (x16)
WE#
RB#
RE#

ALE
CLE

WP#

Vss

Figure 1: Logic Diagram

DQ7 - DQ0 Data Input / Outputs (x8/x16)

DQ15 – DQ8 Data Input / Outputs (x16)
CLE Command latch enable
ALE Address latch enable
CE# Chip Enable
RE# Read Enable
WE# Write Enable
WP# Write Protect
RB# Ready / Busy
Vcc Power supply
Vss Ground
NC No Connection

Table 1: signal names

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1.2 Pin description
Pin Name Description
DATA INPUTS/OUTPUTS
DQ0-DQ7(x8) The DQ pins allow to input command, address and data and to output data during read / program
DQ0-DQ15(x16) operations. The inputs are latched on the rising edge of Write Enable (WE#). The I/O buffer float to High-Z
when the device is deselected or the outputs are disabled.

COMMAND LATCH ENABLE

CLE This input activates the latching of the DQ inputs inside the Command Register on the Rising edge of Write
Enable (WE#).

ADDRESS LATCH ENABLE

ALE This input activates the latching of the DQ inputs inside the Command Register on the Rising edge of Write
Enable (WE#).

CHIP ENABLE
CE# This input controls the selection of the device. When the device is busy CE# low does not deselect the
memory.

WRITE ENABLE
WE# This input acts as clock to latch Command, Address and Data. The DQ inputs are latched on the rise edge
of WE#.

READ ENABLE
RE# The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE# which also increments the internal column address counter by one.

WRITE PROTECT
WP# The WP# pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.

RB# READY BUSY

The Ready/Busy output is an Open Drain pin that signals the state of the memory.

SUPPLY VOLTAGE
VCC The VCC supplies the power for all the operations (Read, Write, Erase). An internal lock circuit prevent the
insertion of Commands when VCC is less than VLKO
VSS GROUND
NC / DNU NOT CONNECTED / DON’T USE

Table 2 : pin description

Notes:
1. A 0.1 μF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from
the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.

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1.3 Functional block diagram

ADDRESS
REGISTER
/
COUNTER

PROGRAM
ERASE
CONTROLLER X
HV GENERATION
D
8192 Mbit + 512 Mbit E
C
NAND FLASH O
D
WE# E
MEMORY ARRAY
R
CE#
COMMAND
WP# INTERFACE
LOGIC
RE#

PAGE BUFFER
COMMAND
REGISTER
Y DECODER

DATA
REGISTER

BUFFERS

IO

Figure 2 : block description

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1.4 Address role

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

st
1 Cycle A0 A1 A2 A3 A4 A5 A6 A7
nd
2 Cycle A8 A9 A10 A11 A12 0 0 0
rd
3 Cycle A13 A14 A15 A16 A17 A18 A19 A20
th
4 Cycle A21 A22 A23 A24 A25 A26 A27 A28
th
5 Cycle (*) A29 A30 0 0 0 0 0 0
Table 3 : Address Cycle Map (x8)
(*): A30 for 8Gbit DDP.

A0 – A12 : byte (column) address in the page

A13 – A18 : page address in the block
A19 – A30 : block address

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

st
1 Cycle A0 A1 A2 A3 A4 A5 A6 A7
nd
2 Cycle A8 A9 A10 A11 0 0 0 0
rd
3 Cycle A12 A13 A14 A15 A16 A17 A18 A19
th
4 Cycle A20 A21 A22 A23 A24 A25 A26 A27
th
5 Cycle (*) A28 A29 0 0 0 0 0 0

Table 4 : Address cycle Map (x16)

(*): A29 for 8Gbit DDP.

A0 – A11 : word (column) address in the page

A12 – A17 : page address in the block
A18 – A29 : block address

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 Dosilicon Confidential PN: FMND4GXXX3F
1.5 Command Set
Acceptable
1st 2nd 3rd 4th command
FUNCTION
CYCLE CYCLE CYCLE CYCLE during
busy
READ 00h 30h - -
READ FOR COPY-BACK 00h 35h - -
READ ID 90h - - -
RESET FFh - - - Yes
PAGE PGM (start) / CACHE PGM (end) 80h 10h - -
CACHE PGM (Start/continue) 80h 15h - -
COPY BACK PGM 85h 10h - -
BLOCK ERASE 60h D0h - -
READ STATUS REGISTER 70h - - - Yes
READ STATUS ENHANCED 78h Yes
RANDOM DATA INPUT 85h - - -
RANDOM DATA OUTPUT 05h E0h - -
READ CACHE (SEQUENTIAL) 31h
READ CACHE ENHANCED (RANDOM) 00h 31h - -
READ CACHE END 3Fh - - -
READ PARAMETER PAGE ECh
EXTENDED READ STATUS F2h/F3h - - - Yes

Table 5 : Command Set

CLE ALE CE# WE# RE# WP# MODE

H L L Rising H X Command Input
Read Mode
L H L Rising H X Address Input
H L L Rising H H Command Input
Write Mode
L H L Rising H H Address Input
L L L Rising H H Data Input
(1)
L L L H Falling X Data Output (on going)
(1) (2)
X X L H H X Data Output (suspended)
L L L H H X Busy time in Read
X X X X X H Busy time in Program
X X X X X H Busy time in Erase
X X X X X L Write Protect
X X H X X 0V / VCC Stand By
Table 6 : Mode Selection

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2 BUS OPERATION

2.1 Command Input.

Command Input bus operation is used to give a command to the memory device. Command are accepted with
Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on
the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write
Protect pin must be high. See Figure 3 and Table 21 for details of the timings requirements. Command codes are
always applied on IO<7:0>, disregarding the bus configuration (X8/X16).

2.2 Address Input.

Address Input bus operation allows the insertion of the memory address. Addresses are accepted with Chip Enable
low, Address Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin
must be high. See Figure 4 and Table 21 for details of the timings requirements. Addresses are always applied on
IO<7:0>, disregarding the bus configuration (X8/X16).

2.3 Data Input.

Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low,
Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write
Enable. See Figure 5 and Table 21 for details of the timings requirements.

2.4 Data Output.

Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low,
Write Enable High, Address Latch Enable low, and Command Latch Enable low. See Figure 6,7,8 and Table 21 for
details of the timings requirements.

2.5 Write Protect.

Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the
protection even during the power up.

2.6 Standby.
In Standby the device is deselected, outputs are disabled and Power Consumption reduced.

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3 DEVICE OPERATION

3.1 Page Read.

Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and
30h to the command register along with 5 address cycles. In two consecutive read operations, the second one
does need 00h command, which four address cycles and 30h command initiates that operation. Second read
operation always requires setup command if first read operation was executed using also random data out
command.
Two types of operations are available: random read , serial page read. The random read mode is enabled when the
page address is changed. The 4352 bytes (X8 device) or 2176 words (X16 device) of data within the selected page
are transferred to the data registers in less than 25us(tR). The system controller may detect the completion of this
data transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they
may be read out in 20ns cycle time (3V version) or 30ns cycle time (1.8V version) by sequentially pulsing RE#.
The repetitive high to low transitions of the RE# clock make the device output the data starting from the selected
column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data
output command.
The column address of next data, which is going to be out, may be changed to the address which follows random
data output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
After power up, device is in read mode so 00h command cycle is not necessary to start a read operation.
Any operation other than read or random data output causes device to exit read mode.
Check Figure 10,11,12 as references.

3.2 Read Cache

The Read Cache function permits a page to be read from the page register while another page is simultaneously
read from the Flash array. A Read Page command, as defined in 3.1, shall be issued prior to the initial sequential
or random Read Cache command in a read cache sequence.
The Read Cache function may be issued after the Read function is complete (SR[6] is set to one). The host may
enter the address of the next page to be read from the Flash array. Data output always begins at column address
00h. If the host does not enter an address to retrieve, the next sequential page is read. When the Read Cache
function is issued, SR[6] is cleared to zero (busy). After the operation is begun SR[6] is set to one (ready) and the
host may begin to read the data from the previous Read or Read Cache function. Issuing an additional Read
Cache function copies the data most recently read from the array into the page register. When no more pages are
to be read, the final page is copied into the page register by issuing the 3Fh command. The host may begin to
read data from the page register when SR[6] is set to one (ready). When the 31h and 3Fh commands are issued,
SR[6] shall be cleared to zero (busy) until the page has finished being copied from the Flash array. The host shall
not issue a sequential Read Cache (31h) command after the last page of the device is read.
Figure 13 defines the Read Cache behavior and timings for the beginning of the cache operations subsequent to a
Read command being issued. SR[6] conveys whether the next selected page can be read from the page register.
Figure 14 defines the Read Cache behavior and timings for the end of cache operation.

3.3 Page Program.

The device is programmed basically by page, but it does allow multiple partial page programming of a word or
consecutive bytes up to 4352 (X8 device) or words up to 2176 (X16 device), in a single page program cycle.
A page program cycle consists of a serial data loading period in which up to 4352 bytes (X8 device) or 2176
words (X16 device) of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by 5 cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be operated
multiple times regardless of how many times it is done in a page.

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The Page Program confirm command (10h) initiates the programming process. The internal write state controller
automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system
controller for other tasks. Once the program process starts, the Read Status Register command may be entered to
read the status register. The system controller can detect the completion of a program cycle by monitoring the RB#
output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be
checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The
command register remains in Read Status command mode until another valid command is written to the command
register. Figure 15,16 detail the sequence.

3.4 Copy-Back Program.

The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system
performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the
block is also needed to be copied to the newly assigned free block. The operation for performing a copy-back
program is a sequential execution of page-read without serial access and copying-program with the address of
destination page. A read operation with "35h" command and the address of the source page moves the whole
4352byte (X8 device) or 2176word (X16 device) data into the internal data buffer. As soon as the device returns to
Ready state, optional data read-out is allowed by toggling RE#, or Copy Back command (85h) with the address
cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin the
programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed as shown in Figure 17.

3.5 Cache Program

Cache Program is an extension of the standard page program which is executed with two 4352 bytes(x8 device) or
2176 words(x16 device) registers, the data and the cache register.
In short, the cache program allows data insertion for one page while program of another page is under execution.
Cache program is available only within a block.
After the serial data input command (80h) is loaded to the command register, followed by 5 cycles of address, a full
or partial page of data is latched into the cache register.
Once the cache write command (15h) is loaded to the command register, the data in the cache register is
transferred into the data register for cell programming. At this time the device remains in Busy state for a short time
(tPCBSY). After all data of the cache register are transferred into the data register, the device returns to the Ready
state, and allows loading the next data into the cache register through another cache program command sequence
(80h-15h).
The busy time following the first sequence 80h – 15h equals the time needed to transfer the data of cache register
to the data register. Cell programming of the data of data register and loading of the next data into the cache
register is consequently processed through a pipeline model.
In case of any subsequent sequence 80h – 15h, transfer from the cache register to the data register is held off until
cell programming of current data register contents is complete; till this moment the device will stay in a busy state
(tPCBSY).
Read Status commands (70h) may be issued to check the status of the different registers, and the pass/fail status
of the cached program operations. It is represented in Figure 18.
More in detail:
a) the Cache-Busy status bit I/O<6> indicates when the cache register is ready to accept new data.
b) the status bit I/O<5> can be used to determine when the cell programming of the current data register contents
is complete
c) the cache program error bit I/O<1> can be used to identify if the previous page (page N-1) has been
successfully programmed or not in cache program operation. The latter can be polled upon I/O<6> status bit
changing to "1" .
d) the error bit I/O<0> is used to identify if any error has been detected by the program / erase controller while
programming page N. The latter can be polled upon I/O<5> status bit changing to "1".
I/O<1> may be read together with I/O<0> .
If the system monitors the progress of the operation only with R/B#, the last page of the target program sequence
must be programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used

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instead, the status bit I/O<5> must be polled to find out if the last programming is finished before starting any other
operation.

3.6 Block Erase.

The Erase operation is done on a block basis. Block address loading is accomplished in 3 cycles initiated by an
Erase Setup command (60h). The Erase Confirm command (D0h) following the block address loading initiates the
internal erasing process. This two-step sequence of setup followed by execution command ensures that memory
contents are not accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and
erase-verify.
Once the erase process starts, the Read Status Register command may be entered to read the status register. The
system controller can detect the completion of an erase by monitoring the RB# output, or the Status bit (I/O 6) of
the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress.
When the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 19 details the sequence..

3.7 Read Status Register.

The device contains a Status Register which may be read to find out whether read, program or erase operation is
completed, and whether the program or erase operation is completed successfully. After writing 70h command to
the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of
CE# or RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in
multiple memory connections even when RB# pins are common-wired. RE# or CE# does not need to be toggled for
updated status. Refer to Table 7 for specific Status Register definitions, and Figure 8 for specific timings
requirements. The command register remains in Status Read mode until further commands are issued to it.
Therefore, if the status register is read during a random read cycle, the read command (00h) should be given
before starting read cycles.
.

3.8 Read Status Register field definition

Table 7 below lists the meaning of each bit of Read Status Register and Read Status Enhanced

Cache
Page Block Cache Program/
IO Read CODING
Program Erase Read Cache
reprogram
NA Pass/Fail N page
0 Pass / Fail Pass / Fail NA
Pass: ‘0’ Fail: ‘1’
NA Pass/Fail N-1page
1 NA NA NA
Pass: ‘0’ Fail: ‘1’
NA NA -
2 NA NA NA
NA NA -
3 NA NA NA
NA NA -
4 NA NA NA
Ready /Busy Active: ‘0’
5 Ready/Busy Ready/Busy Ready/Busy Ready/Busy
Idle:’1’
Ready/Busy Data cache Read/Busy
6 Ready/Busy Ready/Busy Ready/Busy Ready/Busy
Busy: ‘0’ Ready:’1’
Write Write Write Write Write Protected: ‘0’
7
Protect Protect Protect Protect Protect Not Protected: ‘1’
Table 7 : Status Register Coding

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3.9 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h.
st nd rd th (1) th
DENSITY ORG. VCC 1 2 3 4 5
X8 3.0V F8h DCh 80h A6h 62h
X16 3.0V 00F8h CCh 80h E6h 62h
4Gbit
X8 1.8V F8h ACh 80h 26h 62h
X16 1.8V 00F8h BCh 80h 66h 62h
X8 3.0V F8h D3h C1h A6h 66h
8Gbit X16 3.0V 00F8h C3h C1h E6h 66h
DDP X8 1.8V F8h A3h C1h 26h 66h
X16 1.8V 00F8h B3h C1h 66h 66h

Table 8: Read ID for supported configurations

DEVICE IDENTIFIER BYTE DESCRIPTION

st
1 Manufacturer Code
nd
2 Device Identifier
rd
3 Internal chip number, cell type,….
th
4 Page Size, Block Size, Spare Size, Organization
th
5 Multiplane information

Table 9 : Read ID bytes meaning

Description DQ7 DQ6 DQ5-4 DQ3-2 DQ1-0

1 00
2 01
Internal Chip Number
4 10
8 11
2 Level Cell 00
Cell Type
4 Level Cell 01
8 Level Cell 10
16 Level Cell 11
1 00
Number of simultaneously
2 01
programmed pages
4 10
8 11
Interleaved program between Not Supported 0
multiple dice Supported 1
Not Supported 0
Cache Program
Supported 1
rd
Table 10 : 3 byte of Device Identifier Description

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Description DQ7 DQ6 DQ5-4 DQ3 DQ2 DQ1-0

1KB 00
Page Size 2KB 01
(Without Spare Area) 4KB 10
8KB 11
Spare Area Size 16 0
(Byte / 512 Byte) 32 1
64KB 00
Block Size 128KB 01
(Without Spare Area) 256KB 10
512KB 11
X8 0
Organization
X16 1
50ns/30ns 0 0
Serial Access Time
20ns 1 0
Reserved 0 1
Reserved 1 1
th
Table 11 : 4 Byte of Device Identifier Description

Description DQ7 DQ6-4 DQ3-2 DQ1-0

1bit/512Byte 00
2bit/512Byte 01
ECC Level
4bit/512Byte 10
8bit/512Byte 11
1 00
2 01
Plane Number
4 10
8 11
64Mb 000
128Mb 001
256Mb 010
Plane Size 512Mb 011
(Without Spare Area) 1Gb 100
2Gb 101
4Gb 110
8Gb 111

Reserved 0
th
Table 12 : 5 Byte of Device Identifier Description

To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is not
valid to enter an address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the ASCII
encoding of ‘ONFI’ where ‘O’ = 4Fh, ‘N’ = 4Eh, ‘F’ = 46h, and ‘I’ = 49h. Reading beyond four bytes yields
indeterminate values. Figure 20 shows the operation sequence .

3.10 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy
state during random read, program or erase mode, the reset operation will abort these operations. The contents of
memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command
register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP# is high.
Refer to Table 7 for device status after reset operation. If the device is already in reset state a new reset command
will not be accepted by the command register. The RB# pin transitions to low for tRST after the Reset command is
written (see Figure 22).

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3.11 Read Parameter Page
The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features,
timings and other behavioral parameters. Figure 23 defines the Read Parameter Page behavior.
Values in the parameter page are static and shall not change. The host is not required to read the parameter page
after power management events.
The Change Read Column command can be issued during execution of the Read Parameter Page to read specific
portions of the parameter page.
Read Status may be used to check the status of Read Parameter Page during execution. After completion of the
Read Status command, 00h shall be issued by the host on the command line to continue with the data output flow
for the Read Parameter Page command.
Read Status Enhanced shall not be used during execution of the Read Parameter Page command.

3.12 Parameter Page Data Structure Definition

Table 14 defines the parameter page data structure. For parameters that span multiple bytes, the least significant
byte of the parameter corresponds to the first byte.
Values are reported in the parameter page in units of bytes when referring to items related to the size of data
access (as in an 8-bit data access device). For example, the chip will return how many data bytes are in a page.
For a device that supports 16-bit data access, the host is required to convert byte values to word values for its use.
Unused fields should be cleared to 0h.
For more detailed information about Parameter Page Data bits, refer to ONFI Specification 1.0 section 5.4.1

Byte O/M Description

Revision information and features block

0-3 M Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
4-5 M Revision number
2-15 Reserved (0)
1 1 = supports ONFI version 1.0
0 Reserved (0)
6-7 M Features supported
5-15 Reserved (0)
4 1 = supports odd to even page Copyback
3 1 = supports interleaved operations
2 1 = supports non-sequential page programming
1 1 = supports multiple LUN operations
0 1 = supports 16-bit data bus width
8-9 M Optional commands supported
6-15 Reserved (0)
5 1 = supports Read Unique ID
4 1 = supports Copyback
3 1 = supports Read Status Enhanced
2 1 = supports Get Features and Set Features
1 1 = supports Read Cache 18ntegrit
0 1 = supports Page Cache Program command
10-31 Reserved (0)

Manufacturer information block

32-43 M Device manufacturer (12 ASCII characters)
44-63 M Device model (20 ASCII characters)
64 M JEDEC manufacturer ID
65-66 O Date code
67-79 Reserved (0)

Memory organization block

80-83 M Number of data bytes per page
84-85 M Number of spare bytes per page
86-89 M Number of data bytes per partial page
90-91 M Number of spare bytes per partial page

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Byte O/M Description
92-95 M Number of pages per block
96-99 M Number of blocks per logical unit (LUN)
100 M Number of logical units (LUNs)
101 M Number of address cycles
4-7 Column address cycles
0-3 Row address cycles
102 M Number of bits per cell
103-104 M Bad blocks maximum per LUN
105-106 M Block endurance
107 M Guaranteed valid blocks at beginning of target
108-109 M Block endurance for guaranteed valid blocks
110 M Number of programs per page
111 M Partial programming attributes
5-7 Reserved
4 1 = partial page layout is partial page data
followed by partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
112 M Number of bits ECC correctability
113 M Number of interleaved address bits
4-7 Reserved (0)
0-3 Number of interleaved address bits
114 O Interleaved operation attributes
4-7 Reserved (0)
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
115-127 Reserved (0)

Electrical parameters block

128 M I/O pin capacitance
129-130 M Timing mode support
6-15 Reserved (0)
5 1 = supports timing mode 5
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0, shall be 1
131-132 O Program cache timing mode support
6-15 Reserved (0)
5 1 = supports timing mode 5
4 1 = supports timing mode 4
3 1 = supports timing mode 3
2 1 = supports timing mode 2
1 1 = supports timing mode 1
0 1 = supports timing mode 0
133-134 M tPROG Maximum page program time (µs)
135-136 M tBERS Maximum block erase time (µs)
137-138 M tR Maximum page read time (µs)
139-163 Reserved (0)

Vendor block
164-165 M Vendor specific Revision number
166-253 Vendor specific
254-255 M Integrity CRC

Redundant Parameter Pages

256-511 M Value of bytes 0-255
512-767 M Value of bytes 0-255
768+ O Additional redundant parameter pages

Table 14 : Parameter page data

Note : “O” stands for Optional, “M” for Mandatory

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4 Device Parameters

Parameter Symbol Min Typ Max Unit

Valid Block Number, 4Gb NVB 2008 - 2048 Blocks

Table 15: Valid Blocks Number

The First block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime.

Value
Symbol Parameter Unit
1.8V 2.7V 3.0V
Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 0 to 70 0 to 70 °C
TA
–40 to –40 to –40 to
Ambient Operating Temperature (Temperature Range Option 6) °C
85 85 85
–50 to –50 to –50 to
TBIAS Temperature Under Bias °C
125 125 125
–65 to –65 to –65 to
TSTG Storage Temperature °C
150 150 150
(2) –0.6 to –0.6 to –0.6 to
VIO Input or Output Voltage V
2.7 4.6 4.6
–0.6 to –0.6 to –0.6 to
VCC Supply Voltage V
2.7 4.6 4.6
Table 16: Absolute maximum ratings
.

Symb 1.8Volt 2.7Volt 3.0Volt

Parameter Test Conditions Unit
ol Min Typ Max Min Typ Max Min Typ Max
Sequential tRC = 50ns, CE#=VIL,
ICC1 - 10 20 - 15 30 - 15 30 mA
Operating Read IOUT=0mA
Current
Program ICC2 - - 10 20 - 15 30 - 15 30 mA
Erase ICC3 - - 10 20 - 15 30 - 15 30 mA
CE#=VIH,
Stand-by Current (TTL) ICC4 - - 1 - 1 1 mA
WP#=0V/VCC
Stand-By Current CE#=VCC-0.2,
ICC5 - 10 50 - 10 50 10 50 uA
(CMOS) WP#=0/VCC
Input Leakage Current ILI VIN=0 to Vc (max) - - ±10 - - ±10 - ±10 uA
Output Leakage
ILO VOUT=0 to Vcc(max) - - ±10 - - ±10 - ±10 uA
Current
0.8x VCC 0.8x VCC 0.8x VCC
Input High Voltage VIH - VCC
-
+0.3 Vcc
-
+0.3 VCC
-
+0.3
V

0.2x 0.2x 0.2x

Input Low Voltage VIL - -0.3 -
VCC
-0.3 -
VCC
-0.3 -
VCC
V

VCC- VCC-
Output High Voltage IOH = -100uA 0.1
- -
0.4
- - V
VOH
Level
IOH = -400uA 2.4 - - V
Output Low Voltage IOL = 100uA - - 0.1 - - 0.4 V
VOL
Level IOL = 2.1mA - - 0.4 V
Output Low Current IOL VOL=0.1V 3 4 - 3 4 - mA
(RB#) (RB#) VOL=0.4V 8 10 - mA
Table 17: DC and Operating Characteristics

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Parameter Value
1.8Volt 2.7Volt 3.0Volt
Input Pulse Levels 0V to VCC 0V to VCC 0V to VCC
Input Rise and Fall Times 5ns 5ns 5ns
Input and Output Timing Levels VCC / 2 VCC / 2 VCC / 2
1 TTL GATE and 1 TTL GATE and 1 TTL GATE and
Output Load (1.7V – 1.95V & 2.5V - 3.6V)
CL=30pF CL=30pF CL=50pF
Table 18: AC Test Conditions

Item Symbol Test Condition Min Max Unit

Input / Output Capacitance (1) CI/O VIL = 0V - 10 pF
Input Capacitance (1) CIN VIN = 0V - 10 pF
Table 19 : Pin Capacitance (TA = 25C, f=1.0MHz)
NOTE: For the stacked devices version the Input Capacitance is 10pF x <number of stacked chips) and the I/O capacitance is 10pF x
<number of stacked chips)

Parameter Symbol Min Typ Max Unit

Program Time tPROG - 200 700 us
Cache program short busy time tPCBSY 3.5 tPROG us
Number of partial Program Main + Spare NOP - - 4 Cycle
Cycles in the same page Array
Block Erase Time tBERS - 2.0 10 ms
Read Cache busy time tRCBSY 3.5 tR us
Table 20: Program / Erase Characteristics

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1.8 Volt 2.7 Volt 3.0 Volt

Parameter Symbol Unit
Min Max Min Max
CLE Setup time tCLS 10 10 10 ns
CLE Hold time tCLH 5 5 5 ns
CE# Setup time tCS 25 15 15 ns
CE# Hold time tCH 5 5 5 ns
WE# Pulse width tWP 15 10 10 ns
ALE Setup time tALS 10 10 10 ns
ALE Hold time tALH 5 5 5 ns
Data Setup time tDS 10 7 7 ns
Data Hold time tDH 5 5 5 ns
Write Cycle time tWC 30 20 20 ns
WE# High Hold time tWH 10 7 7 ns
Address to Data Loading time tADL 100 70 70 ns
Data Transfer from Cell to
tR 25 25 25 us
Register
ALE to RE# Delay tAR 10 10 10 ns
CLE to RE# Delay tCLR 10 10 10 ns
Ready to RE# Low tRR 20 20 20 ns
RE# Pulse Width tRP 15 10 10 ns
WE# High to Busy tWB 100 100 100 ns
Read Cycle Time tRC 30 20 20 ns
RE# Access Time tREA 30 20 20 ns
CE# Access Time tCEA 45 25 25 ns
RE# High to Output Hi-Z tRHZ 100 100 100 ns
CE# High to Output Hi-Z tCHZ 30 30 30 ns
CE# High to ALE or CLE Don’t
tCSD 10 10 10 ns
care
RE# High to Output Hold tRHOH 15 15 15 ns
RE# Low to Output Hold tRLOH - 5 5 ns
CE# High to Output Hold tCOH 15 15 15 ns
RE# High Hold Time tREH 10 7 7 ns
Output Hi-Z to RE# Low tIR 0 0 0 ns
RE# High to WE# Low tRHW 100 100 100 ns
WE# High to RE# Low tWHR 60 60 60 ns
Device Resetting Time 5/10/ 5/10/ 5/10/
tRST 500 500 500 us
(Read/Program/Erase)
(1) (1) (1)
Write protection time tWW 100 100 100 ns
Table 21 : AC Timing Characteristics
NOTE:
(1) If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us

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5 Timing Diagrams

Figure 3 : Command Latch Cycle

Figure 4 : Address Latch Cycle

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Figure 5 : Input Data Latch Cycle

Figure 6 : Sequential Out Cycle after Read

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Figure 7 : Sequential Out Cycle after Read

Figure 8 : Status Read Cycle

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CLE

WE

ALE

RE

IO0-7 78h R1 R2 R3 SR

Figure 9: Read Status Enhanced cycle

Figure 10 : Read Operation (Read One Page)

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Figure 11 : Read Operation intercepted by CE#

Figure 12 : Random Data Output

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tRCBSY tRCBSY

Figure 13 : read cache timings, start of cache operation

tRCBSY tRCBSY tRCBSY

Figure 14 : read cache timings, end of cache operation

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Figure 15 : Page Program Operation

Figure 16 : Random Data In

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Figure 17 : Copy Back read with optional data readout /Copy back program with optional data input

tPCBSY

Figure 18 : cache program

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Figure 19 : Block Erase Operation (Erase One Block)

F8h

Figure 20 : READ ID Operation

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CLE

WE

ALE

RE
tWHR

IO0-7 90h 20h 4Fh 4Eh 46h 49h

Figure 21 : ONFI signature timing diagram

Figure 22 : Reset operation timing

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CLE

WE

ALE

RE

IO0-7 ECh 00h P00 P10 … P01 P11 …

tR
R/B

Figure 23 : Read Parameter Page timings

Figure 24 : tWW in Program Operation

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Figure 25 : tWW in Erase Operation

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Note : VTH = 1.5 Volt for 1.8 Volt Supply devices; 2.5 Volt for 3.0 Volt Supply devices

Figure 26 : Power on and Data Protection timings

Figure 27 : Ready/Busy Pin electrical application

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6 Bad Block Management

Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all
the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit
line and common source line by a select transistor. The devices are supplied with all the locations inside valid
blocks erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the
spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block
Information must be read before any erase is attempted as the Bad Block Information may be erased. For the
system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad
Block table following the flowchart

Figure 28 : Bad Block Management Flowchart

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Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by
copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase
them will give errors in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, the block can be
replaced by re-programming the current data and copying the rest of the replaced block to an available valid block.

Figure 29 : Block Failure

Block Replacement flow is as below

1.When an error happens in the nth page of the Block ’A’ during erase or program operation.
2.Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
3.Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
4.Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.

Figure 30 : Bad Block Replacement

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7 Supported Packages
7.1 PIN CONFIGURATION (TSOP1)

PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 – TSOP – 1220AF
Unit : mm/inch

0.472 MAX
12.40

20.00±0.20
0.787±0.008 D

#1 #48
- 0.03
+0.07
0.20

0.010
0.25
- 0.001
+0.003
- 0.03
+0.07

MAX
0.008
0.16

0.472
12.40
12.40
0.488
0.0197
0.50

#24 #25

20.00±0.20 0.05
0.787±0.008 MIN
0.002
TYP

1.20
MAX
- 0.001
+0.003
- 0.035
+0.075

0.047
0.010

18.40±0.10
0.25

0.724±0.004
0.005
0.125

0~8°

0.50
0.020

0.45±0.75
0.018±0.030

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7.2 Ball Assignment: 63-Ball FBGA (Balls Down, Top View)

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PACKAGE DIMENSIONS
63-Ball FBGA PACKAGE TYPE

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