Microprocessor term paper

ECE 212:- Microprocessor

TOPIC – Design of Handshaking mode of 8255 with

8086.

Submitted To : Ms. Kamal Preet

Submitted By : Manish Kumar
Roll No : A16
Section : B1802
Registration No : 10801901
Acknowledgement

First and foremost I would like to thank my teacher who has assigned me this
term paper to bring out my creative capabilities.

I express my gratitude to my parents for being a continuous source of

encouragement and for all their financial aid given to me.

I would like to thank to acknowledge the assistance provided to me by the library

staff of Lovely Professional University.

My heartfelt gratitude to my friends, cousins for helping me to complete my work

in time.
 Contents

1) Introduction
2) Operational mode of 8255

3) Control word Format

4) Low speed two way Handshaking

5) High speed two way Handshaking

 Introduction input/output port or as two 4-bit
input/output ports or to produce
The Intel8255 Programmable Peri
handshake signals for ports A and
pheral Interface chip is a
B.
peripheral chip originally
developed for the Intel The three ports are further
8085 microprocessor, and as such grouped as follows:
is a member of a large array of
such chips, known as the MCS-85 1. Group A consisting of port
Family. This chip was later also A and upper part of port
used with the Intel 8086 and its C.
descendants 2. Group B consisting of port
B and lower part of port
This chip is used to give the CPU
C.
access to programmable
parallel I/O, and is similar to other Eight data lines (D0 - D7) are
such chips like the Motorola 6520 available (with an 8-bit data
PIA(Peripheral Interface buffer) to read/write data into the
Adapter) . The 8255 is widely ports or control register under the
used not only in many status of the " RD" (pin 5) and 
microcomputer/microcontroller WR" (pin 36), which are active
systems especially Z-80 low signals for read and write
based, home computers such operations respectively. The
as SV-328and all MSX, but also in address lines A1 and A0 allow to
the system board of the best successively access any one of the
known original IBM-PC, PC/XT, ports or the control register as
PC/jr, etc. and clones, along with listed below:
numerous homebuilt
computer computers such as A1 A0 Function
the N8VEM.

The 8255 has 24 input/output pins 0 0 port A

in all. These are divided into three
8-bit ports. Port A and port B can
be used as 8-bit input/output ports. 0 1 port B
Port C can be used as an 8-bit
 In this mode, the ports can be used
1 0 port C
for simple input/output operations
without handshaking. If both port
1 1 control register A and B are initialized in mode 0,
the two halves of port C can be
The control signal "' CS" (pin 6) either used together as an
is used to enable the 8255 chip. It additional 8-bit port, or they can
is an active low signal, i.e., be used as individual 4-bit ports.
when  CS = '0' , the 8255 is Since the two halves of port C are
enabled. The RESET input (pin independent, they may be used
35) is connected to a system (like such that one-half is initialized as
8085, 8086, etc. ) reset line so that an input port while the other half
when the system is reset, all the is initialized as an output port. The
ports are initialised as input lines. input/output features in mode 0
The control register or the control are as follows:
logic or the command word
1. O/p are latched.
register is an 8-bit register used to
select the modes of operation and 2. I/p are buffered not
input/output designation of the latched.
ports. 3. Port do not have
handshake or interrupt
capability.
Operational modes of 8255
Mode 1
There are two main operational When we wish to use port A or
modes of 8255: port B for handshake input or
output operation, we initialize that
1. Input/output mode port in mode 1 (port A and port B
2. Bit set/reset mode can be initialized to operate in
different modes, i.e., for e.g., port
Input/output mode
A can operate in mode 0 and port
There are three types of the
B in mode 1). Some of the pins of
input/output mode which are as
port C function as handshake
follows:
lines.
Mode 0
For port B in this mode eight lines (PA0 - PA7). Pins PC3
(irrespective of whether is acting - PC7 are used as handshake lines
as an input port or output port), for port A. The remaining pins of
PC0, PC1 and PC2 pins function port C (PC0 - PC2) can be used as
as handshake lines. input/output lines if group B is
initialized in mode 0. In this mode,
If port A is initialized as mode 1
the 8255 may be used to extend
input port, then, PC3, PC4 and
the system bus to a
PC5 function as handshake
slave microprocessor or to transfer
signals. Pins PC6 and PC7 are
data bytes to and from a floppy
available for use as input/output
disk controller.
lines.
Bit set/reset (BSR) mode
The mode 1 which supports
Control word format
handshaking has following
features: Input/output mode format

1. Two ports i.e. port A and B  The figure shows the

can be use as 8-bit i/o control word format in the
port. input/output mode. This mode
2. Each port uses three lines is selected by making D7 =
of port c as handshake '1' .
signal and remaining two
 D0, D1, D3, D4 are for
signals can be function as
lower port C, port B, upper
i/o port.
port C and port A respectively.
3. Interrupt logic is When D0 or D1 or D3 or D4
supported. are "SET", the corresponding
ports act as input ports. For
4. Input and Output data are
e.g., if D0 = D4 = '1', then
latched.
lower port C and port A act as
Mode 2 input ports. If these bits
are "RESET", then the
Only group A can be initialised in
corresponding ports act as
this mode. Port A can be used
output ports. For e.g., if D1 =
for bidirectional handshake data
D3 = '0', then port B and upper
transfer. This means that data can
port C act as output ports.
be input or output on the same
 D2 is used for mode 4. Upper port C should
selection for group B (Port B also be an input port,
and Lower Port C). When D2 hence, D3 = '1'.
= '0', mode 0 is selected and 5. Port A has to operate
when D2 = '1', mode 1 is output port, hence, D4 =
selected. '0'.
6. Lower port C should
 D5, D6 are used for mode
also operate as output port,
selection for group A (Upper
hence, D0 = '0'.
Port C and Port A). The format
Applying the corresponding
is as follows:
values to the format in
input/output mode, we get the
D6 D5 mode control word as "8A (hex)"
BSR mode format
0 0 0
 The figure shows the
control word format in
0 1 1 BSR mode. This mode is
selected by
1 X 2 making D7='0'.

 D0 is used for bit set/reset.

Example: If port B and upper
When D0= '1', the port C
port C have to be initialised as
bit selected (selection of
input ports and lower port C and
a port C bit is shown in
port A as ouput ports (all in mode
the next point) is SET,
0), what is the control word?
when D0 = '0', the port C
1. Since it is an input/ouput bit is RESET.
mode, D7 = '1'.
2. Mode selection bits, D2,  D1, D2, D3 are used to
D5, D6 are all '0' for mode select a particular port C
0 operation. bit whose value may be
3. Port B should operate as altered using D0 bit as
input port, hence, D1 = '1'. mentioned above. The
selection of the port C
bits are done as follows:
 3. PC5 has to be selected,
hence, D3 = '1', D2 = '0',
D3 D2 D1 Bit/pin of port C selected D1 = '1'.
4. PC5 has to be set,
0 0 0 PC0 hence, D0 = '1'.

0 0 1 PC1

0 1 0 PC2
Low-Speed Two-Way
Handshaking
0 1 1 PC3

For this application note, low-

1 0 0 PC4 speed data transfers relate to data
that is transferred at a rate less
than 1 million samples per second
1 0 1 PC5 (1 MS/s).

8255/82C55 Mode
1 1 0 PC6
This is the most common
handshaking protocol. Common
applications include interfacing to
1 1 1 PC7 parallel digital I/O peripherals
such as BCD-compatible panel
meters and communication/control
 D4, D5, D6 are not used. of test equipment. All Lab/1200
Family, DIO-24/96, and MIO-16D
Example: If the 5th bit (PC5) boards use an 8255 or 82C55 PPI.
In this application note 8255 and
of port C has to be "SET", 82C55 PPIs will be referred to
then what is the control simply as 8255. Although the
word? 6533 Family can emulate the 8255
protocol, the following discussion
1. Since it is BSR relates to the actual 8255
mode, D7 = '0'. handshaking and not to the 8255
emulation mode of the 6533. Each
2. Since D4, D5, D6 are 8255 chip contains three 8-bit
not used, assume them to ports (PA, PB, and PC). When the
be '0'. 8255 is configured for a
handshaking operation, lines in
Port C are used to control the data
transfer operation.

8255 -- Mode 1, Strobed Input

The two control lines that are used

in strobed output operations are
ACK* and OBF*. The ACK* line
is an input controlled by the
peripheral device that is
handshaking with the 8255. The
OBF* is an output line controlled
by the 8255. The 8255 device
places a low signal on the OBF*
line to indicate that data has been
written to the port. The peripheral
A low signal in the STB* line device places a low signal on the
causes the 8255 to load data into ACK* line to indicate that the data
the input latch. The 8255 outputs a written by the 8255 has been
high signal on the IBF line to accepted. The peripheral device
indicate that data has been loaded then sets the ACK* signal back to
into the input latch. When the IBF high when it is ready to accept
lines goes back to low, the new data.
peripheral device can then place a
low signal on the STB* line to 8255 -- Mode 2, Bidirectional
load new data into the input latch Bus
of the 8255.

8255 -- Mode 1, Strobed Output

Only Port A on the 8255 PPI can

be configured for a bidirectional
mode. Two main lines of port C
are used to control handshaking of
port A -- ACK* and STB*.

When you want to configure the

port as output, both ACK* and
STB* are initially high. When the
ACK* line goes low, data will be
driven to Port A as long as the
ACK* line is low. As soon as the
ACK* line goes high again, Port
A goes back to a high impedance
mode, and thus the pattern you
just wrote will no longer be
present.
More than one digital port can be
grouped together so that more
digital data can be transferred at a
time, such as 16-bit data transfers
with two ports instead of 8-bit data
transfers with one port. For 8255-
based devices that perform
handshaking, all the STB* lines
must be connected together for
digital input. Only the IBF* line of
the last port should be connected
to the peripheral device.

Handshaking More than One

Port or More than One 8255 PPI

Figure 6. Digital Scanning Output

Group Handshaking Connections

When performing digital output

handshaking on more than one
8255 port, connect only the ACK*
and OBF* handshaking signals of Level-ACK, Leading-Edge Pulse,
the last port. Long Pulse, and Trailing-Edge
Pulse 
These protocols are recognized
High-Speed Two-Way only by the DIO-32F and the 6533
Handshaking -- Asynchronous Family DAQ devices. Two control
lines are used to handshake the
data transfers: ACK and REQ. The
There are two main categories of DAQ device (6533 or DIO-32F)
high-speed handshaking -- controls the ACK signal and the
synchronous and asynchronous. peripheral device controls the
The synchronous protocols use a REQ signal.
shared clock between transmitter
and receiver to perform the block Level-ACK Mode
transfer. High-speed handshaking
in this application note refers to
data transfers faster than 1 MS/s. In level-ACK mode, the DAQ
While the DIO-32F DAQ devices device asserts the ACK signal
implement all the following modes when ready for a transfer and
(except 8255 emulation and burst holds the ACK signal level until
mode), they cannot handshake an active-going edge occurs on the
data at high speeds. Sustained REQ line. After the REQ edge
transfer rates is typically less than occurs, the 6533 device deasserts
400 kwords/s with the driver the ACK signal until ready for
software (1 word = 16 bits). another transfer.

8255 Emulation

8255 emulation mode is available

only on 6533 devices. This mode
handshakes in a manner
compatible with the 8255 PPI. The
6533 device emulation mode is a
superset of the 8255 handshaking
protocol. The 6533 device can
perform back-to-back transfers
much faster than a true 8255-
based device. If the peripheral
device needs more time, you can
configure the 6533 device to add a
data settling delay between
transfers. The 6533 device can use
8255 emulation with 8, 16, or 32-
bit data paths.
 pulse mode, a programmable
delay is used to increase the
minimum width of the pulse rather
than delaying the ACK pulse. In
long-pulse mode you can
handshake with 8255 emulation
mode, if you set the ACK and
REQ signals to active low. If you
want to use long-pulse to
handshake with an actual 8255,
make sure to select an adequate
minimum pulse width for your
8255. A data-settling time of 500
ns is sufficient for any current
8255. 
Leading-Edge Mode
In leading-edge mode, the DAQ
device and the peripheral device
send each other pulses on the
ACK and REQ lines. The leading
edge of the ACK or REQ pulse
indicates that the DAQ device or
peripheral device is ready for a
transfer. In input mode, the DAQ
device sends an ACK pulse when
ready to receive data. After
receiving at least the leading edge
of the ACK pulse, the peripheral
devices can strobe data into the
DAQ device by asserting the REQ
signal. In output mode, the DAQ
device sends an ACK pulse after
driving output data to indicate
new, valid output data. The  Long-Pulse Mode Input
peripheral device can latch the
data on the falling or rising edge
of the ACK signal, or at any time
before returning a REQ pulse, thus
requesting additional data. 

Long-Pulse Mode
Long-pulse mode is a variant
of leading-edge mode. The only
difference is the effect of a data
settling delay, if used. In long-
 Burst Mode
The burst-mode handshaking
protocol is used only by 6533
Family DAQ devices. This
handshaking mode is a
synchronous, or clocked protocol.
Common applications include
electronic and logic testing, board
and chip verification, pattern
detection, and high-speed
communication/data transfer with
ATE (automated test equipment).
In burst mode, three control lines
are used for data transfers -- REQ,
ACK, and PCLK. The data
transmitter and receiver share a
clock signal over the PCLK
Long-Pulse Mode Output
control line. The 6533 device
controls the state of the ACK line,
Trailing-Edge Mode
and the peripheral device controls
In trailing-edge mode, the DAQ
the state of the REQ line.
device and peripheral device send
each other pulses on the ACK and
REQ lines. The trailing edge of
the ACK or REQ pulse indicates
that the DAQ device or peripheral
device is ready for a transfer.

Input Burst Mode Transfer

Example

Trailing-Edge Mode Input

High-Speed Two-Way
Handshaking -- Synchronous
Output Burst Mode Transfer
Example

When performing a burst-mode

input operation with an external
PCLK, data will be latched on the
falling edge of PCLK. With all
other data transfer functions and
PCLK directions, data is latched
on the rising edge of PCLK.