ASSIGNMENT

Section-1

1. What is DFT?
ANS:
DFT stands for Design for Testability
DFT is a process inserting the small circuit to the normal design that improves the
Controllability and Observability of the internal circuit nodes so that the circuit can be tested
more effectively.
Controllability: The ability to set or reset the internal nodes from the primary inputs.
Observability: The ability to observe the values of an internal nodes at the primary outputs.

While attempts to use these methods have substantially improved the testability of a
design and eased sequential automatic test pattern generation (ATPG), their end results at
reaching the target fault coverage goal.

2. Why is DFT required?

ANS:
DFT is required during the design test because
➢ It Reduces ATPG efforts.
➢ Generates high coverage test patterns.
➢ It reduces run time of patterns.
➢ Increases the test coverage area.
➢ DFT reduces test cost and test time.
➢ It reduces the human efforts
➢ Ensure easy, Risk Free development into design and test flow.
➢ Improves test quality.
➢ Easy to debug and Diagnosis.
➢ It reduces time to market.

3. Explain ASIC flow

ANS:
➢ ASIC(Application specific integrated circuit) is designed for a special solo purpose and
the function of the chip is the same throughout the chip life.
➢ In digital circuitry is made up of permanently connected gates and flip flops in silicon so
the logic function can't be changed.
 Asic flow design

Specifications:
In this stage the features information which is expecting new features(like low power
consumption, high speed) in the device.from the customer is collected.
Architecture design:
➢ In this stage the architecture team will design an architecture based on the specifications.
➢ The architecture is like a block diagram we can find the all the details which are using in
the design(like processors, memories) and how they are connected.
➢ This architecture team will estimate the block area, how much power is required and cost
for the design.
RTL design:
➢ Register transfer level(RTL) constructing a digital design using combinational and
sequential circuit in hardware description language like verilog or VHDL.
➢ The above architecture is converted into verilog or VHDL code.
 ➢ This code describes how data is transformed as it is passed from register to register

RTL verification:
➢ It is a functional verification of RTL design. After the RTL design by applying test cases
➢ We verify the design in the verification stage.
➢ If any mistakes are found then the design is re-sent to the RTL designing department.
➢ Performing this verification is correcting the faults.
Synthesis:
➢ It is a process of converting the RTL code into gate level netlist.
➢ In the synthesis process the design is converted into technology dependent.
➢ It is a 3 stage process.
1. Translation:- The RTL code is converted into Boolean expression.
2. Optimization:- In this stage Boolean expression is optimized by sum of product
and product of sum optimization method.
3. Mapping:- In this technology independent Boolean expression is converted into
technology dependent and generates the gate level netlist.
➢ The inputs for synthesis are RTL code, .SDC and .LIB after the synthesis the generated
outputs are gate level netlist and .SDC.
DFT:
➢ Design for testability(DFT) is a technique which facilitates a design to become testable
after production.
➢ In this stage we put extra logic along with the design logic during the implementation
process which helps the post production process.
➢ The DFT will make the testing easy at post production process.At this stage an
ATPG(automatic test pattern generator) file will be generated.
Floorplan:
➢ The floorplan is the process of determining the placement for the components.
➢ It is the process of placing blocks/macros in the chip/core area thereby determining
routing areas between them.
➢ It creates power straps and specifies pg connection.
➢ It also determines the i/o, pin/pad placement information.
Placement:
➢ Placement is the process of automatically assigning the correct position to standard cells
on the chip with no overlapping.
➢ By global placement outside of standard cells will be placed inside roughly.
➢ In the placement stage we check the congestion value by GRC map.

CTS (clock tree synthesis):

➢ In this stage we built the clock tree by using inverters and buffers.
 ➢ In the chip clock signal is essential to the flip flops, to give the clock signal from the
clock source we built the clock tree.
➢ It is the process of balancing the clock skew and minimizing insertion delay in order to
meet timing and power.
Routing:
➢ In this stage we connect all the cells physically with the metal straps.
➢ Routing is divided as two parts
1. global routing : The global routing will tell which signal which metal
layer is used. Before the detailed routing all are the logical connections
2. detailed routing : In detailed routing the physical connections are done.
Signoff:
➢ In the signoff stage all the tests are done to check the quality and performance of the
layout before tapeout.
➢ After this the design is converted into a Graphic design system (GDS II) file.
Fabrication:
By the Graphic design system (GDS II) file information we fabricate the chip.The total design is
converted into chip by the manufacturing process.
Packaging and testing:
➢ After the fabrication process we test the chip.If there is any fault in the design then we
modifies the design by repeating the steps.
➢ If there are no faults then the chip will go to packaging.

4. What are the DFT Goals and Test plans?

ANS:
DFT goals:
➢ The DFT goal is to increase the Testability of the design.
➢ To improve controllability/observability
➢ Generates the test pattern for the design.
➢ To Increase the Fault courage area.
➢ Reduce the test cost and test time.
➢ Increase the product quality.
Test plans:
➢ Insert a small circuit into design to increase the testability.
➢ Generating the test patterns of the design.
➢ Converting normal cells to Scannable cells.
➢ Inserting the control and observing points.
5. Difference between Functional testing DFT testing
ANS:
Functional testing DFT testing

● Functional testing is used for the ● DFT Testing the correctness of

correctness of the design. manufactured devices.
● Done by simulation or formal ● Two step process Test Generation and
methods, hardware emulation Test Application.
● Performed only once ● Applied to manufactured device
● Responsible for quality of design ● Responsible for the quality of the device.
● Functional vectors are more ● Test Vectors are Less
● Functional Coverage is Less ● Test Coverage is More

6. What are the DFT Approaches & Explain?

ANS:
DFT can be done in two ways:
1. Ad hoc DFT
2. Structured DFT
Ad hoc DFT:
● The ad hoc approach involves using a set of design practice and modification guidelines
for testability improvement.
● In this the test point is inserted.
● Ad hoc DFT techniques typically learned through experience.
Typical Ad hoc DFT Techniques
● Insert test points
● Avoid asynchronous set/reset for storage elements
● Avoid combinational feedback loops
● Avoid redundant logic
● Avoid asynchronous logic
● Partition a large circuit into small blocks
Test point insertion:
Insert the test point to increase the controllability and observability.
The two test points are control point and observe point.
 control points: the control points are inserted in design to check the design.
observe point : At the observe point we check if the desired output is produced or not.

Structured Approach:
In this we use the scan design.
➢ In scan design the sequential flip flops are converted to scan cells.
➢ The operation is done three modes
1. Normal mode:
All test signals are off , design operates on original functionality.(TM = 0)
2. shift mode:
In shift mode the test signal and scan enable is activated to shift the data.
(TM = 1,SE = 1)
3. captured mode:
In captured mode the scan enable is inactive to capture the combinational data.
(TM = 1, SE = 0)

7. Difference between ASIC and FPGA.

ANS:

ASIC(Application specific Integrated ckt) FPGA(Field programmable gate array)

➢ ASIC cannot be reconfigured for the ➢ FPGA can be reconfigured for different
different design. design.
➢ They contain only one design throughout ➢ They can be changed in the design.
the life cycle
➢ Design is specified by using hardware ➢ Design is specified by using hardware
descriptive language like verilog, VHDL etc descriptive language like verilog, VHDL etc
➢ In ASIC analog designs are flexible to ➢ In FPGA analog designs may not be
create. flexible.
➢ It is energy efficient and consumes less ➢ It consumes more power than the ASIC
power.
➢ ASIC can operate at the high frequency ➢ It cannot operates at high frequency
➢ It is not suitable for the area where the ➢ It is suitable for areas where the design
design needs to upgrade frequently. needs to be upgraded.
➢ It suits for high volume production. ➢ Not suits for high volume production.
➢ More cost is required to design. ➢ Less cost is required.
➢ It is built only after validating a design for ➢ It is used as a prototype and validates a
permanent use. design.
8. What is a manufacturing Test and list down the goals?
ANS:
Manufacturing test :
It is defined as the purpose of screen out the defective parts of the device before
shipping the device.
➢ Manufacturing test's goal is to reduce the fault in the chip.
➢ To reduce the short circuit open circuit faults on the chip.
➢ Increase the functionality.
➢ Increase the fault coverage.
➢ Decrease the test escapes and yield losses.

Section-2
1. What is scan?
ANS:
★ Scan is used to replace all selected normal flip flops with scan flip flops.
★ The chip will initially be taken into a special mode, called “scan mode” by setting an
input pin to an appropriate value.
★ Scan is the idea using which one can control the inputs of the various gates and flip-flops
inside the chip and also observe the outputs from the internal flops in a sequence.
★ Connect scan cells into scan chain
★ One of the primary input pins will feed the input of the first flop in this chain in the scan
mode output of the first flip flop connected to the SI pin of the next flip flop and continue
till the last flip flop. The output of the very last flop will be taken to a primary output.

2. What are the scan types?

ANS:
Scan can be defined in two types:
1. Full scan:
In full scan all the flip flop elements are replaced with the scan cells and
stitch(connect) one or more chains called scan chains.

● High fault coverage.

● More Quality assured.
● Highly Automated process.
● Ease of use.
 2. Partial scan:
In partial scan selected flip flop elements are replaced with the scan cells and
stitch(connect) one or more chains called scan chains.

● Reduces the impact of time.

● Reduces the impact of area.
● less fault coverage than full scan.
● Reduce the scan length.

3. What are the scan Styles?

ANS:
The scan styles are :
1. Muxed D scan cell
2. Clocked scan cell
3. LSSD scan cell

Muxed D scan cell:

➢ In muxed D scan cells The most widely used scan cell replacement for the D storage
element is the muxed-D scan cell. an edge triggered muxed-D scan cell design.
➢ This scan cell is composed of a D flip-flop and a multiplexer. The multiplexer uses a scan
enable (SE) input to select between the data input (DI) and the scan input (SI).
➢ In normal/capture mode, SE is set to 0. The value present at the data input DI is captured
into the internal D flip-flop when a rising clock edge is applied. In shift mode, SE is set to
1.

Clocked scan cell:

➢ An edge-triggered clocked-scan cell can also be used to replace a D flip-flop in a scan
design.
 ➢ Similar to a mixed-D scan cell, a clocked-scan cell also has a data input DI and a scan
input SI and shift clock
➢ In the clocked-scan cell, input selection is conducted using two independent clocks, data
clock (DCK) clock and shift clock (SCK).
➢ In normal/capture mode, the data clock DCK is used to capture the value present at the
data input DI into the clocked-scan cell. In shift mode, the shift clock SCK is used to shift
in new data from the scan input SI into the clocked-scan cell.
➢ The major advantage of using a clocked scan cell is that it results in no performance
degradation on the data input.
➢ The major disadvantage is that it requires additional shift clock routing.

Level sensitive scan cell:

➢ The Level sensitive scan cell (LSSD) scan cell is used for level-sensitive, latch-based
designs.
➢ This scan cell contains two latches, a master two-port D latch L1 and a slave D latch L2.
➢ Clocks C, A, and B are used to select between the data input D and the scan input I to
drive L1 and L2. In an LSSD design, either L1 or L2 can be used to drive the
combinational logic of the design.
➢ The major advantage of using an LSSD scan cell is that it allows us to insert scan into a
latch-based design and designs using LSSD are race-free.
➢ The major disadvantage is that the technique requires routing for the additional clocks,
which increases routing complexity and area due to extra latches.
4. What are the Scan Benefits?
ANS:
scan benefits are:
➢ scan increase the Testability of the design.
➢ It can be used to control the inputs of various gates and flip flops and observe the outputs.
➢ Increases the fault coverage area.
➢ Scan design is highly automated.
➢ Reduces human efforts.
➢ Reduces the impact of time.
➢ Increase the Quality of the design.
➢ Detects the manufacturing faults in the design.

5. What are the Scan design rules?

ANS:
A set of rules that must be considered during the design.
➢ Only the clocked D- flip flop must be used to implement the design.
➢ At least one primary input pin must be available for the test.
➢ All clocks and reset must be directly fed from top level to avoid the violations.
➢ There should be no gated clock.
➢ Clock signals must not feed to the data input to flip flops.

6. What is lockup latch and terminal lock up latch?

ANS:
Lockup latch:
➢ A lock-up latch is a transparent latch used to avoid large clock skew in a large uncommon
clock path.
➢ Lock-up latches are used in between the two scan flops having large hold failure
probability due to uncommon clock path so that there is no issue in closing timing in a
scan chain across domains in scan-shift mode.
Terminal lockup latch:
➢ The lock up latch is added at every end of the scan chain is called the terminal lock up
latch.
7. What is the difference between a clock buffer and a normal buffer?
ANS:
A buffer is an element which produces an output signal, which is of the same value as the
input signal.

Clock buffer Normal buffer

● The clock buffers are designed ● This buffers are designed with
with some special properties. W/L ratio.the sum of rise time and
fall time is minimum
● The clock buffer has equal rise ● It has difference in rise time and
time and fall time. fall time

● It has high drive strength. ● It has low drive strength.

● It drives long nets and higher ● It drives small chains and less
fanouts. fanouts.

● It produce overall less delay ● It produces an overall high delay.

● It consumes more power. ● It consumes less power.

8. What is slack?
ANS:
1. Slack is defined as a difference in the required time and arrival time.
2. If required time is greater than the arrival time(required time >arrival time)
a. positive slack or zero slack.
b. Indicates that it met the desired constraints.
3. if required time is less than arrival time (required time < arrival time)
a. Negative slack .
b. Indicates that it has not met the desired constraints.
c. setup and hold violations occur.

9. What is set up time and hold time?

ANS:
Setup and hold times are the most common types of timing checks used in timing verification.
These checks specify that the data input must remain stable for a specified interval before and
after the clock input changes and synchronised inputs with respect to the clock inputs.
 Setup time: The amount of time the data at the synchronous input (D) must be stable before the
active edge of the clock.
Hold time: the amount of time the data at the synchronous input (D) must be stable after the
active edge of the clock

10. What is propagation delay and clock skew?

ANS:
Propagation delay: Propagation Delay is the amount of time it takes for a signal to travel
from a source to a destination.

propagation delay
Clock skew : Clock skew (timing skew) is a phenomenon in synchronous digital circuit systems
in which the same sourced clock signal arrives at different components at different times. The
instantaneous difference between the readings of any two clocks is called their skew.
Clock skew = (Arrival time at capture clock pin) - (Arrival time at launch clock pin)
Clock skew is defined as two types:
Positive clock skew: If the clock arrival time at capture flip-flop is greater than that at launch
flip-flop, clock skew is said to be positive.
Negative clock skew: if the clock arrival time at capture flip-flop is less than the launch
flip-flop, clock skew is said to be negative.

Section-3

1. What are the input files required for scan insertion?

ANS : Input files are required for scan insertion:
1.Gate level netlist file
2. Library file
2. Write scan insertion flow?
ANS:
Scan Insertion flow involves three steps 1. setup mode 2. insertion mode 3. Analysis mode
Setup mode : read the files and assigning the values done in thi mode
Insertion mode : create and delete of the connections done in this mode.
Analysis: It is done outside the block that generates the output files.

step 1 : Read the Gate level netlist file and library file.
step 2 : > mention the clock and reset value.
> count the number of chain count (chain count = number of flip flop/max chain count)
step 3 : Design rule check.
● If there are DRC violations, we have to fix the violations and enter into analysis mode.
● If no DRC failure is there, we enter the analysis mode.
step 4 : convert Normal flip flop to scannable flip flop and stitch/connect the scan cells.
step 5 : Write the output files
the output files are:
1. scan inserted netlist
2. do files
3. test procedure file

3. Write DFT DRC Golden rules

ANS:
★ Gated clock
★ Asynchronous set/reset
★ Tri state buffer
★ Bi directional I/O
★ Combinational loop
★ Derived clock
★ Scan Chain Cross Clock Domains
★ Mixed Negative and positive edge flip flop
★ Clock Grouping
4. Explain any 2 Scan DRC Violations
ANS:
ASYNCHRONOUS RESET:
● Asynchronous set/reset signals of scan cells that are not directly controlled from
primary inputs can prevent scan chains from shifting data properly.
● To avoid this problem, it is required that these asynchronous set/reset signals be forced to
an inactive state during the shift operation.
● These asynchronous set/reset signals are typically referred to as being sequentially
controlled.
● A method for fixing this asynchronous reset problem using an OR gate with an input tied
to the test mode signal.
>> In example , the second flip flop reset is not from the primary reset it depends on the
first flip flop so it may or may not be function.
>> It can be solved by inserting the OR gate or mux with input fed from the test mode or scan
enable.

COMBINATIONAL FEEDBACK LOOP:

>> In a design combinational feedback loop , it can introduce either sequential behavior or
oscillation.
>> The value stored in the loop cannot be controlled or determined during the test, this can lead
to an increase in test generation complexity or fault coverage loss.
>> combinational feedback loops the best way to fix this problem is to rewrite the RTL code
generating the loop.
>> it can also be fixed by using a test mode signal TM. by inserting a scan cell This signal
permanently disables the loop throughout the entire shift and capture operations to break the
loop,by this we get control and observation points in the loop.

5. Explain Scan operation with diagram?

ANS:
Scan operation is done when the test mode is active (TM = 1), before scan operation the normal
flip flops are converted into scannable flip flops.
The scan operation involves three stages : 1. scan input, 2. capture mode, 3. scan output.

➢ During the scan in operation involves in shifting the data to all flip flop(TM = 1 and scan
enable = 1)
➢ During this the data flow from the output of one flip flop fed to the scan input of the next
flip flop.
➢ Once sequence is loaded, scannable is to zero and one clock cycle is required to capture
mode in which the combinational data is loaded.
➢ output is captured at end of each flip flop
➢ The data is shifted out and it is compared with the expected output.

6. What is the command to convert normal flop to scannable flop?

ANS:
command : INSERT_TEST_LOGIC is used to convert normal flip flop to scannable flop.
7. What is the command to stitch the scan chain?
ANS:
command : INSERT_TEST_LOGIC is used to stitch(connect) the scan chain.
8. What are the advantages and disadvantages of scan chain balancing?
ANS:
Advantages:
>> By doing scan chain balancing it reduces the test time.
>> Clock pulses are used efficiently without losses.
>> Almost equal numbers of scan cells are in each scan chain.
>> It increases the fault coverage.
Disadvantages:
>> It produces X values if there are fewer flip flops in a scan chain.

9. Write the commands for scan insertion

ANS:
Commands for scan insertion are :
➢ set_context dft -scan : This command is used for scan Insertion
➢ read_verilog (file name.vg) : This command is used for reading the gate level netlist
file.
➢ read_cell_library (library filename) : Used to read the tessent cell library.
➢ set_current_design (module name) : this command is used to set the top level module
from the net list.
➢ set_design_level physical_block : set the design level as sub-block/physical_block
➢ set_system_mode (insertion/setup) : used to change the mode to insertion/setup to
create the ports
➢ create_port (port name) -direction input : This command is used to create a port.
➢ set_context dft -scan : This command also used to change Mode to setup Again
to add the DFT configuration
➢ set_scan_enable (port name) -active high : This command is used to set the value of
the port
➢ add_clocks 0 clk : Used to state the off state value of clock
➢ add_clocks 1 reset : Used to state the off state value of reset
➢ set_scan_insertion_options (-chain_count) or (-chain length) (number) : Used to
mention the scan chain length or scan cells in a chain.
➢ check_design_rules : This command is to check the design rules. We check the DRC
rules specific to the context. If no DRC failure is there, we enter the analysis mode. If any
DRC failure occurs the tool will remain in the setup mode which enables it to analyze
DRC violation.
➢ analyze_scan_chains : this command will gives the distribution of scan cells in a
chain
➢ report_scan_chains : This command will give the detailed report of:
● Name of scan chain
● Name of scan chain group
● Scan chain input and output pins
● Length of the scan chain
● Name of the scan clock(s)

➢ insert_test_logic : It will insert the test structure and convert the normal flip flop
to scan flip flop and will stitch up scan chains to increase the testability of the circuit.

➢ write_design -output_file (file name) -rep : this command write the –output file means
we need to write the design without DRC/Violations.
-replace/-rep : It indicates that whatever may have been written in the output file
previously, we have the right to replace it.

➢ write_atpg_setup (scan file name) -replace : It write the test procedure file and other
do files required for ATPG pattern generation