Design of Enhanced Performance Folded

Cascoded Operational Transconductance

Amplifier
Cite as: AIP Conference Proceedings 1324, 360 (2010); https://doi.org/10.1063/1.3526234
Published Online: 03 December 2010

Priyanka Soni, B. P. Singh and Monika Bhardwaj

ARTICLES YOU MAY BE INTERESTED IN

Design and analysis of two stage CMOS operational amplifier using 0.13 µm technology
AIP Conference Proceedings 2203, 020040 (2020); https://doi.org/10.1063/1.5142132

Design of CMOS low-dropout voltage regulator for power management integrated circuit in
0.18-µm technology
AIP Conference Proceedings 2203, 020006 (2020); https://doi.org/10.1063/1.5142098

Design of a High Performance Operational Amplifier

AIP Conference Proceedings 1324, 452 (2010); https://doi.org/10.1063/1.3526257

AIP Conference Proceedings 1324, 360 (2010); https://doi.org/10.1063/1.3526234 1324, 360

© 2010 American Institute of Physics.

 Design of Enhanced Performance Folded Cascoded
Operational Transconductance Amplifier
Priyanka Soni, B.P. Singh, Monika Bhardwaj
[email protected], [email protected], [email protected]

Mody Institute of Technology & Science/ECE Department, Lakshmangarh (Sikar), India

Abstract—This paper presents a modified folded cascode transconductance amplifier. Inclusion of an extra stage and
compensation network in the proposed amplifier enhanced the performance over the conventional folded. The
proposed circuit offers good trade-off on the conflicting performance parameters such as bandwidth, slew rate, d.c.
gain, phase margin and settling time. The simulation has been carried out on Tanner EDA tool on TSMC 180 nm
technology.
Keywords— Operational Transconductance amplifier (OTA), folded cascode stage, operational amplifiers.

I. INTRODUCTION propose the new folded cascode OTA. Section IV

presents the proposed FCA characteristics. Section V
The rapid increasing use of battery-operated portable
gives simulation results and we draw the conclusions
equipments in application areas such as
in Section VI.
telecommunications and medical electronics imposes
the use of low-power and miniaturized circuits II. PREVIOUS WORK
realized with VLSI (very large scale integrated)
technology. In order to achieve fast settling time
coupled with high DC gain and high bandwidth, the
folded cascode amplifier is used in many analogue
circuit designs. Operational transconductance
amplifier (OTA) in its folded-cascode structure is
analysed as it is used in a wide range of analogue
sample-data circuit applications such as fast-settling
amplifier, interface circuit, switched-capacitor filter,
ADC, DAC etc. In such applications high DC gain of
the OTA is required and so folded cascode amplifier
(FCA) [4] is an obvious selection. The OTA is well
known for its high bandwidth in open-loop
configuration. In FCA PMOS input pair is preferred
over the NMOS one owing to its higher non dominant
poles, lower flicker noise, lower input common-mode
voltage [8], [9].
The OTA based circuits can be used for high
frequency applications where conventional operational
amplifier based circuits has bandwidth limitation.
Multipath schemes were used in previous work [2], [3]
to enhance the performance of the FCA. The settling
speed depends mainly on the unity gain frequency and Figure 1. Conventional folded cascode amplifier
a single pole settling accuracy is due to high DC gain
of the folded cascode circuit [1]. Since the folded- The schematic of differential input, single ended
cascode OTA presents a single parasitic pole and output conventional folded cascode amplifier [4] is
relatively large DC gain, it is commonly used for shown in the Fig. 1. It is cascade of a differential
high-frequency applications. For high speed transconductance stage. All the transistors are sized in
applications, fast settling OTAs are required, which order to get optimum output. This design shows
demand both high unity gain band width and slew superior frequency response than two-stage
rate. operational amplifiers.
This paper is organized as follows. In Section II, It consists of two differential input pairs with the
same
CREDIT LINE (BELOW) TO BE INSERTED ON
we describe the previous work. In section III, we
THE type
FIRSTof transistors,
PAGE OF EACHM1-M2.
PAPER The gain and phase

CP1324, International Conference on Methods and Models in Science and Technology (ICM2ST-10)
edited by R. B. Patel and B. P. Singh
© 2010 American Institute of Physics 978-0-7354-0879-1/10/$30.00

360
of the operational amplifier can be obtained with However, the amplifier’s band width, gain and slew
signal applied to M1 and M2 of the OTA ensuring all rate are arguably the most critical design criteria. The
transistors in the saturation region [4]. Transistors M3 analysis of Fig. 2 shows that FCA delivers 65.6 MHz
and M4 have the largest transconductance. However, bandwidth and 60 dB gain.
their role is only limited to providing a folded node for
the small signal current generated by input PMOS
transistors. The body of all transistors is connected to IV. PROPOSED FCA CHARACTERISTICS
source in order to avoid substrate bias effect.
The modifications presented in section III
III. NEW PROPOSED CIRCUIT
provide the modified FCA with enhanced features
The schematic of modified folded cascoded over conventional FCA. In order to present these
operational transconductance amplifier is shown in enhancements, all devices are assumed to operate in
Fig. 2, with PMOS differential pair, two NMOS saturation region using the simplified square law drain
folded cascode, and R-C compensation network. current model given by:

                              (1) 

Where,
ID = Drain Current
µ = Carrier Mobility
Cox = Oxide Capacitance per unit area
W= Channel Width
L= Channel Length
VGS = Gate source voltage
VT = Threshold voltage

Body effect is avoided for all transistors by connecting

their body to source. It reflects the influence of the
zero source to substrate voltage upon the device. The
values of threshold voltage for NMOS and PMOS are
0.3748918 and -0.3847793 respectively.

A. Gain and Gain band width

Figure 2. Proposed folded cascode amplifier The gain of FCA is the multiplication of
transconductance with output impedance. Amplifier’s
All the transistors from M0 to M10 have the same size small signal transconductance, Gm, can be calculated
as conventional FCA. The proposed FCA contains a by finding the short circuit current at the output with
folded cascode as first stage and a common source as respect to the input. The load capacitance and the
second stage. The second stage consisting of M11 and GBW is directly related to the transconductance of the
M12 transistors forms the output section. In proposed operational transconductance amplifier as
model an equal bias current (IB) flow in both input
transistors M1 and M2. M11 transistor is getting the Gm = GBW 2π CL (2)
same bias as M0 and M12 is getting input from
conventional FCA. The instability of amplifier is In order to obtain a large GBW, transistors with large
compensated out with the addition of an external RC transconductance and lesser load capacitances must be
compensation network. Compensation is a provision selected. The variation in gain and GBW with load
of a device or circuit for the purpose of reducing capacitance is shown in Fig. 3 and 4 respectively. Fig.
sources of errors or error due to variations in specified 3 shows that for high band width lesser load
operating conditions. Lag compensating network capacitance is required. The gain remains constant
(series combination of R and C) permits low gain at with variation in load capacitance. Therefore, the bias
higher frequencies and high gain at lower frequencies. currents through the input transistors have to be large.
The value of the compensating resistance and The gain decreases at high frequency due to internal
capacitance is calculated in order to get the better capacitances associated with devices. This fall can be
stability and phase margin of the proposed circuit. enhanced by the adding compensating capacitance. So

361
we connect a compensating capacitance in proposed
circuit to enhance gain. The gain of the proposed FCA
is 14 dB more than conventional while the unity GBW
is 4.93 times that of the conventional for same power
supply. The frequency response of both conventional
and proposed amplifiers is plotted in Fig. 6 which
contains gain in dB and the phase in degrees. The
unity gain bandwidth is the frequency at which the
gain becomes 0 dB in the magnitude plot.

Figure 5. Variation in slew rate with load capacitance

B. Slew Rate and Settling Time

The slew rate is defined as the ratio of the maximum

Figure 3. Variation in GBW with load capacitance

(a)

Figure 4. Variation in gain (dB) with load capacitance

362
 (b)

Figure 6. Frequency response simulation results

(a) Magnitude and (b) Phase

output current to the load capacitance as shown below:

(3)

It is specified on the amplifier’s data sheet in units of

V/µs. It implies that if the input signal applied to an
amplifier circuit is of the nature that demands an
output response faster than the specified value of SR,
the operational amplifier will not comply. The settling
time of an amplifier is very important parameter as it
defines the speed at which amplifier can be sampled.
It is clear from (3) that with the increment in
load capacitance, slew rate decreases. Graphical
variations are shown in Fig. 5. The slew rate is also Figure 7 Slew rate (output versus time)
affected by compensating capacitor. The rate, at which
C. Phase Margin
output voltage (slew rate) can change, is primarily
limited by frequency compensation capacitor. The
The phase margin is a good indicator to the transient
voltage across capacitor cannot change
response and it is determined by poles and zeros of the
instantaneously, but is governed by size of capacitor.
amplifier’s transfer function. Phase margin is a
Speed is a direct measure of the ability of the
measure of relative stability. The dominant poles for
amplifier to respond to large input signals. The
‘s’ domain can be determined by output impedances
effective speed is defined as the time taken for the
and capacitive load. It has been obtained from
response to an input step to settle to a given error (e.g.
frequency response (Fig. 6) by tracing the gain line
0.001%) of its final value. Two distinct periods
down from its vertical intercept to where it crosses the
determine the speed, the slewing period and the linear
0-dB line at approximately 65.6 MHz. Then we trace
settling period. During the slewing period, the
the 65.6 MHz line up until it intersects the phase curve
variation rate of the output is limited to a maximum
to read the phase angle. Then phase margin can be
value (slew rate). This is originated in the charging of
obtained as:
a capacitive node with a limited current. During the
linear settling period the output voltage settles to its
Phase margin = Phase Angle - (-180)
final value in a small-signal linear fashion [5].
= Phase Angle + 180
The settling time of an operational amplifier is
defined as the time taken by the output to respond to a
step change of input that remains within a defined
error band. To design low power fast settling
amplifier, it is needed to model some of their
parameters such as the slew rate accurately with
simple relations. A two-pole model was developed in
[6],[7] considering the slew rate limitation. An
operational amplifier has inherent capacitances, load
capacitance and compensation capacitance. The rate of
change of voltage at each point in the circuit is limited
by the available current to charge the capacitance at
that point. Maximum rate of change of voltage across
these capacitors defines the slew rate. Fig.7 shows the
settling behaviour of both conventional and proposed
OTA. Since the settling time is strongly dependent on
phase margin, precise frequency shaping is required in
order to achieve the minimum settling time (MST). Figure 8 Variation in phase margin with load capacitance

Table I
(Design Specifications with simulation results)

363
 VI. CONCLUSION
Parameter Conventional Proposed FCA
FCA
In this paper, a 0.18 µm folded cascode
Technology 0.18 µm 0.18 µm
operational transconductance amplifier, using
Power Supply(v) 1.8 1.8 compensation technique, has been presented and
Load 5.6 5.6
simulated with a supply voltage of 1.8 V. The
Capacitor(p.f.) proposed circuit essentially improves the parameters
Compensating .......... 1K such as the unity gain frequency (GBW), phase
Resistance(Ω) margin, gain, slew rate and settling time. The obtained
Compensating ........... 0.9p gain is large enough for practical applications. This
Capacitance(f) approach is efficient and viable to improve the gain,
Gain(dB) 46 60 bandwidth and the phase margin.
Phase Margin(deg.) 80 61
REFERENCES
Slew rate(V/µs) 3.125 9.64
[1] Mohammad Yavari and Omid Shoaei, “A Novel fully
GBW(MHz) 13.3 65.6 Differential Class AB folded cascode OTA for switched
capacitor applications”, IEICE Electronics Express, vol. 1,
Settling time(µs) 0.35 0.19
No. 13, 358-362, Oct. 2004.
[2] K. Nakamura and L.R. Carley, “An enhanced fully differential
folded cascode op amp," IEEE J. Solid-State Circuits, vol. 27,
The variation in phase margin with load capacitance is pp. 563-568, Apr. 1992.
shown in Fig. 8. From the graph it is clear that at a [3] J. Adut, J Silva-Martinez, and M. Rocha-Perez, “A 10.7 MHz
load capacitance of 5.6 p.f., the optimum phase sixth-order SC ladder filter in 0.35 µm CMOS technology”,
IEEE Trans .Circuits Syst. I: Reg. Papers, vol. 53, no. 8, pp
margin of 610 results. With the increment or 1625-1635 Aug. 2006.
decrement in the value of load capacitance, the [4] Rida S. Assaad, Jose Silva Martinez, “The recycling folded
performance of system degrades. For the proposed cascode: A general enhancement of the folded cascode
circuit it is 610, which is a good figure for stability of amplifier”, IEEE J. Solid-state Circuits, vol. 44, NO. 9, Sep.
2009.
an amplifier. [5] F. Wang and R. Harjani, “Dynamic amplifiers: Settling,
slewing and power issues,” IEEE Int. Symp. Circuits Syst.,
V. SIMULATION RESULTS 1995.
[6] C. T. Chuang, “Analysis of the settling behavior of an
operational amplifier,” IEEE J. Solid-state Circuits, vol. SC-
Simulation has been done on tanner EDA tool at 17, pp. 74-80, Feb. 1982.
TSMC 180nm technology with 1.8 V supply voltage. [7] J. C. Lin and J. H. Nevin, “A modified time-domain model for
TSPICE simulation results of the circuit confirm the nonlinear analysis of an operational amplifier,” IEEE J. Solid-
effectiveness of the approach. Proposed FCA shows State Circuits, vol. SC-21, pp. 478-483, June 1986.
[8] Phillip E. Allen, Douglas R. Holberg, “CMOS Analog circuit
better performance when circuit area is not a major Design,” 2 nd Edition, 2004
concern. To get better stability, RC compensation [9] R. Jacob Baker, Harry W. Li, David E. Boyce ,”CMOS circuit
network is used, R was set to be 1 KΩ and capacitor design, layout and simulation,” 2nd edition ,2000.
was set to be 0.9 pf with load capacitance of 5.6 pf
Fig. 6 shows the frequency response of proposed FCA
including the conventional FCA. The settling
performance of both FCA is shown in Fig. 7. The
design specifications and the summary of simulation
results are shown in table I. Fig. 5 shows the
variations in slew rate with load capacitor. In these
simulations, for comparison, dimensions of transistors
and bias currents used in proposed FCA circuit is the
same as in conventional FCA. Simulation result shows
that the proposed FCA achieves unity gain band width
of 65.6 MHz, which is about 4.93 times that of the
conventional FCA. In order to measure gain band
width, step signal is applied at the input. It results into
the settling time of 0.19 µs, which is much lesser than
other topologies. The proposed FCA also achieves a
gain of about 14 dB greater than the conventional
folded cascode OTA. The slew rate is 3.08 times
larger than that of the conventional folded cascode.
The proposed FCA has a phase margin of 610 while
conventional has 800 indicating better performance.

364