Analog Circuits and Simulation and Lab ECE

LABORATORY MANUAL
“ ANALOG CIRCUITS AND SIMULATION LAB [ECL 202]”

IVth SEMESTER ELECTRONICS AND COMMUNICATION

ENGINEERING

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

SCMS SCHOOL OF ENGINEERING &TECHNOLOGY

VIDYA NAGAR, PALISSERY, KARUKUTTY- 683582
Analog Circuits and Simulation and Lab ECE

INDEX

Sl No Name of the experiment Page No

1. RC Integrator And Differentiator

2. Clipping circuits using diodes.

3. . Clamping circuits using diodes

Exp No: 1
Date:
4. RC coupled amplifier using BJT in CE configuration-
Measurement of gain, BW and plotting of frequency response
5. Cascade amplifier – gain and frequency response

6. Feedback amplifiers (current series, voltage series) - gain and

frequency response

7. Low frequency oscillators – RC phase shift or Wien bridge

SIMULATION EXPERIMENTS-LTSPICE
8 RC Integrator And Differentiator

9. Clipping circuits using diodes.

10. . Clamping circuits using diodes

11. RC coupled amplifier using BJT in CE configuration-

Measurement of gain, BW and plotting of frequency response
12. Cascade amplifier – gain and frequency response

13. Feedback amplifiers (current series, voltage series) - gain and

frequency response

14. Low frequency oscillators – RC phase shift or Wien bridge

EXPERIMENT-1
RC INTEGRATOR AND DIFFERENTIATOR

1.1 AIM
To design and set up an RC integrator and Differentiator and study its response to pulse and
Analog Circuits and Simulation and Lab ECE

square waves.

1.2 EQUIPMENT & COMPONENTS REQUIRED

Cathode-ray Oscilloscope, Function Generator, BNC connector, Resistor-5.6kΩ, Capacitors-
3.3µF, 220pF
1.3 THEORY
A differentiator gives the derivative of input voltage as output.  A differentiator using passive
components resistors and capacitors is a high pass filter. It acts as a differentiator only when
the time constant is too small. The voltage at output is proportional to the current through the
capacitor. The current through the capacitor can be expressed as  .The output is
taking across the resistor. So output will be . Thus differentiation of input takes
place. 

          When a square wave is applied at the input, during the positive half cycle, capacitor
charges. So initially the voltage across the resistor will be the applied voltage. As the
capacitor charges, the voltage across resistor decreases.    

        Consider the case of integrator. It is a low pass filter. Here the time constant of the
circuit should be very large. Here output is taking across the capacitor. As the input square
wave is applied, during the positive half cycle the voltage across capacitor increases from
zero to the maximum (peak value of applied voltage). During the negative half cycle, the
capacitor starts to discharge and comes to zero. This process repeats for the remaining cycles
and a triangular wave is obtained.

1.4 CIRCUIT DIAGRAM

RC Integrator

RC Differentiator
Analog Circuits and Simulation and Lab ECE

1.5 OUTPUT WAVEFORMS

Differentiator

Integrator

1.6 Design:
Design of Integrator:
Let the input be pulse train of 1kHz. Then T=1ms.
For an Integrator
To avoid loading select
The output impedance of the signal generator = 600Ω
Then R= 6000Ω
Use 5.6 k std
We get C= 2.857 µF. Use 3.3µF std.
Analog Circuits and Simulation and Lab ECE

Design of Differentiator:
Let the input be pulse train of 1kHz. Then T=1ms.
For an Integrator
To avoid loading select
The output impedance of the signal generator = 600Ω
Then R= 6000Ω
Use 5.6 k std
We get C= 285pF. Use 220pF std.

1.7 PROCEDURE:

1. Wire the circuit as shown in the figure after testing the components.
2. Note down the output waveforms for the following conditions using a potentiometer.
(i) (ii) (iii)
3. Repeat the above steps for a 10Vpp, 1 kHz pulse wave input.

1.8 RESULT
Designed and set up an RC integrator and Differentiator and study its response to pulse and
square waves.

EXPERIMENT-2
CLIPPING CIRCUITS

2.1AIM:
To design and construct the various clipping circuits using diodes.
Analog Circuits and Simulation and Lab ECE

2.2 COMPONENTS & EQUIPMENTS REQUIRED:

1 Resistor 3.3 k 1
2 Diode IN 4001 2
3 Function Generator - 1
4 CRO - 1
5 Dual Power Supply (0-15)V 1
6 Bread board - 1

2.3 THEORY
The property of a diode as a switching device is used in clipping circuits. They are linear
wave shaping circuits which clips off either the positive or negative portions of an input
waveform. It is also used to slice off an input waveform between two voltage levels .
They are classified as series and shunt clippers.

2.3.1 Positive clipper with clipping at 0 volt

This circuit allows only the negative halves of the input to the output. All positive half
cycles are bypassed through the diode since the diode gets forward biased when input
voltage becomes positive. Due to the voltage drop across the diode, the clipping occurs
exactly at 0.6V.

2.3.2 Negative clipper with clipping at 0 volt

This circuit allows only the positive halves of the input to the output. All negative half
cycles are bypassed through the diode since the diode gets forward biased when input
voltage becomes negative . Due to the voltage drop across the diode, the clipping occurs
exactly at -0.6V.

2.3.3 Positive clipper with clipping at +3V volt

Till the input becomes greater than +3V the diode is reverse biased and the input will
appear at the output. When input exceeds +3V the diode becomes forward biased and the
cell voltage appears at the output.

2.3.4 Negative clipper with clipping at -3V volt

Till the input becomes less than -3V the diode is reverse biased and the input will appear
at the output. When input less than -3V the diode becomes forward biased and the cell
voltage appears at the output.

5.3.5 Double clipper with clipping level at +3V AND -3V

This the circuit is the merging of positive and negative clippers. During positive half
cycles of the input one branch become short and other remains open and vice versa during
negative half cycle. Actual clipping levels are +3.6V and -3.6V due to diode drops.

5.3.6 Two level slicer at +3V and +5V

This circuit allows the signal to pass to the output only between +3V and +5V. During
negative half cycles Dl conducts and D2 reverse biased and the output remains at
+3V.During positive half cycle when the input exceeds +3V Dl is reversed and input appears
at the output. If the input exceeds +5V D2 conducts and output remains at +5V. The actual
clipping occurs at +2.4V and +5.6V.
Analog Circuits and Simulation and Lab ECE

2.4 CIRCUIT DIAGRAM

2.4.1 POSITIVE CLIPPER AT 0V

2.4.2 NEGATIVE CLIPPER AT 0V

2.4.3 POSITIVE CLIPPER AT +3V

2.4.4 POSITIVE CLIPPER AT -3V

Analog Circuits and Simulation and Lab ECE

2.4.5 NEGATIVE CLIPPER AT +3V 2.4.6 NEGATIVE CLIPPER AT -3V

2.4.7 DOUBLE CLIPPING

2.5 PROCEDURE
i) Set up the circuit on the bread board
ii) Feed a sine wave from the signal generator
iii) Observe the clipped waveforms on CRO
iv) To observe transfer characteristics on CRO feed Vin to X-channel and Vo to Y- Channel
and press the XY switch.
Analog Circuits and Simulation and Lab ECE

2.6 EXPECTED GRAPH

2.6.1 POSITIVE CLIPPING

2.6.2 NEGATIVE CLIPPING

2.6.3 POSITIVE CLIPPER BIASED AT +3V

2.6.4 POSITIVE CLIPPER BIASED AT -3V

2.6.5 NEGATIVE CLIPPER BIASED AT+3V

Analog Circuits and Simulation and Lab ECE

2.6.6 NEGATIVE CLIPPER BIASED AT -3V

2.6.7 DOUBLE CLIPPER

2.6.8 SLICER WITH CLIPPING LEVEL AT 3V and +5V

2.7 RESULT
The various clipping circuits were designed and resulting waveforms were observed.
Analog Circuits and Simulation and Lab ECE

3. CLAMPING CIRCUITS

3.1 AIM
To design,set up and study various clamping circuits using diodes

3.2 COMPONENTS & EQUIPMENTS REQUIRED

Power supplies, CRO, function generator, capacitors, diode and bread board

3.3 THEORY
Clamping circuits are used to add or subtract a dc voltage to a given waveform
without changing the shape. The capacitor which is charged to a voltage and
subsequently prevented from discharging can serve as a replacement for a dc source.

3.3.1 Clamper clamping positively at OV

During negative half cycle of the input the diode conducts and capacitor charges to
Vm with positive polarity at the right side of the capacitor. During positive half cycle the
capacitor cannot discharge since the diode does not conduct. Thus the capacitor acts as a dc
source of Vm volts connected in series with input signal.

3.3.2 Clamper clamping negatively at OV

During positive half cycle of the input the diode conducts and capacitor charges to
Vm with negative polarity at the right side of the capacitor. During negative half cycle the
capacitor cannot discharge since the diode does not conduct. Thus the capacitor acts as a dc
source of Vm volts connected in series with input signal.

3.3.3 Clamper clamping negatively at -3V

During positive half cycle capacitor charges through the dc source and the diode till
(Vm +3V) with negative polarity at the right plate. The charging of the capacitor is extended
to (Vm+3V) due to the presence of the dc source.

3.3.4 Clamper clamping negatively at +3V

During positive half cycle capacitor charges through the dc source and the diode till
(Vm -3V) with negative polarity at the right plate. The charging of the capacitor is limited to
(Vm-3V) due to the presence of the dc source.

3.3.5 Clamper clamping positively at -3V

During negative half cycle capacitor charges through the dc source and the diode
till (Vm -3V) with positive polarity at the right plate. The charging of the capacitor is limited
to (Vm-3V) due to the presence of the dc source

3.3.6 Clamper clamping positively at +3V

During negative half cycle capacitor charges through the dc source and the diode till
(Vm +3V) with positive polarity at the right plate. The charging of the capacitor is
limited to (Vm+3V) due to the presence of the dc source.
Analog Circuits and Simulation and Lab ECE

3.4 CIRCUIT DIAGRAM

3.4.1 POSITIVE CLAMPER

3.4.2 NEGATIVE CLAMPER

3.4.3 POSITIVE CLAMPER BIASED AT +3V

3.4.4 POSITIVE CLAMPER BIASED AT -3V

Analog Circuits and Simulation and Lab ECE

3.4.5 NEGATIVE CLAMPER BIASED AT +3V

3.4.6 NEGATIVE CLAMPER BIASED AT -3V

3.5 PROCEDURE
i) Set up the circuit on the bread board
ii) Feed a sine wave from the signal generator
iii) Observe the clamped waveforms on CRO
iv) To observe transfer characteristics on CRO feed Vin to X-channel and Vo to
Y- channel and press the XY switch
3.6 EXPECTED GRAPH
Analog Circuits and Simulation and Lab ECE

3.6.1 POSITIVE CLAMPER

3.6.2 NEGATIVE CLAMPER

3.6.3 POSITIVE CLAMPER AT +3V

3.6.4 POSITIVE CLAMPER AT -3V

Analog Circuits and Simulation and Lab ECE

3.6.5 NEGATIVE CLAMPER AT +3V

3.6.6 NEGATIVE CLAMPER AT -3V

3.7 RESULT
The various clamping circuits were set up and their waveforms were observed
Analog Circuits and Simulation and Lab ECE

4. RC-COUPLED AMPLIFIER

4.1 AIM
To design and set up an RC -coupled C E amplifier using bipolar junction
transistor and to plot its frequency response.
4.2 Components and equipments required Transistor, dc source,
capacitors, re- sistors, bread board, signal generator, multimeter and CRO.
Theory RC -coupled C E amplifier is widely used in audio frequency
applications in radio and TV receivers. It provides current, voltage and power
gains. Base current controls the collector current of a common emitter
amplifier. A small increase in base current results in a relatively large increase
in collector current. Similarly, a small decrease in base current causes large
decrease in collector current. The emitter-base junction must be forward
biased and the collector base junction must be reverse biased for the proper
functioning of an amplifier. In the circuit diagram, an NPN transistor is
connected as a common emitter ac amplifier. R1 and R2 are employed
for the voltage divider bias of the transistor. Voltage divider bias provides
good stabilisation independent of the variations of β. The input signal Vin is
coupled through CC 1 to the base and output voltage is coupled from collector
through the capacitor CC 2 .
The input impedance of the amplifier is expressed as Zin = R1 ||R2 ||(1 + hF
E re ) and output impedance as Zout = RC ||RL where re is the internal
emitter resistance of the transistor given by the expression = 25 mV/IE , where
25 mV is temperature equivalent voltage at room temperature.
Selection of transistor Transistor is selected according to the frequency
of oper- ation, and power requirements. The hF E of the transistor is another
aspect we should be careful about. Low frequency gain of a BJT amplifier is
given by the expression.
Voltage gain Av = −hFR E RL . In the worst case with RL = Ri , AV =
−hF E . i

hF E of any transistor will vary in large ranges. For example, the hF E

of SL100 (a general purpose transistor) varies from 40 to 300. hF E of
BC107 (an AF driver) varies from 100 to 500. Therefore a transistor must be
selected such that its minimum guaranteed hF E is greater than or equal to
AV required.
Selection of supply voltage VC C For a distortionless output
from an audio amplifier, the operating point must be kept at the middle of
the load line selecting VC EQ = 50% VC C (= 0.5VC C ). This means that
Analog Circuits and Simulation and Lab ECE

the output voltage swing in either positive or negative direction is half of VC

C . However, VC C is selected 20% more than the required voltage swing. For
example, if the required output swing is 10 V, VC C is selected 12 V.

Selection of collector current IC The nominal value of IC can be

selected from
Analog Circuits and Simulation and Lab ECE

the data sheet. Usually it will be given corresponding to hF E bias. It is the bias
current at which hF E is measured. For BC107 it is 2 mA, for SL100 it is 150
mA, and for power transistor 2N3055 it is 4 A.
Design of emitter resistor RE Current series feedback is used in
this circuit using RE . It stabilizes the operating point against temperature
variation. Voltage across RE must be as high as possible. But, higher drop
across RE will reduce the output voltage swing. So, as a rule of thumb, 10%
of VC C is fixed across RE .
Analog Circuits and Simulation and Lab ECE

V V C
V
RERE=
I E = IC
R
E since IE ≈ IC C
, RE = 0.1 IC
Design of RC Value of RC can be obtained from the relation RC =
0.4VC C /IC
since remaining 40% of VC C is dropped
across RC .
Design of potential divider R1 and R2 Value of IB is obtained
by using the expression IB = IC /hF E min. At least 10IB should be allowed
to flow through R1 and R2 for the better stability of bias voltages. If the
current through R1 and R2 is near to IB , slight variation in IB will affect
the voltage across R1 and R2 . In other words, the base current will load the
voltage divider. When IB gets branched into the base of transistor, 9IB flows
through R2 . Values of R1 and R2 can be calculated from the dc potentials
created by the respective currents.
Design of bypass capacitor CE The purpose of the bypass capacitor is
to bypass signal current to ground. To bypass the frequency of interest,
reactance of the capacitor XC E computed at that frequency should be much
less than the emitter resistance. As a rule of thumb, it is taken XC E ≤ RE
/10.
Design of coupling capacitor CC
The purpose of the coupling capacitor is to couple the ac signal to the
input of the amplifier and block dc. It also determines t he lowest frequency
that to be amplified. Value of the coupling capacitor CC is obtained such that
its reactance XC at the lowest frequency (say 100 Hz or so for an audio
amplifier), should be less than the input impedance of the amplifier. That
means XC must be ≤ Rin /10. Here Rin = R1 ||R2 ||(1 + hF E re ) where re
is the internal emitter resistance of the transistor given by the expression = 25
mV/IE at room temperature.

Procedure
1. Test all the components using a multimeter. Set up the circuit and verify
dc bias conditions. To check dc bias conditions, remove input signal and
capacitors in the circuit.
2. Connect the capacitors in the circuit. Apply a 100 mV peak to peak
sinusoidal signal from the function generator to the circuit input.
Observe the input and output waveforms on the CRO screen
simultaneously.
 3. Keep the input voltage constant at 100 mV, vary the frequency of the input
signal from 0 to 1 MHz or highest frequency available in the generator.
Measure the output amplitude corresponding to different frequencies and
enter it in tabular column.
4. Plot the frequency response characteristics on a graph sheet with gain in
dB on y-axis and logf on x-axis. Mark log fL and log fH corresponding
to 3 dB points. (If a semi-log graph sheet is used instead of ordinary
graph sheet, mark f along x-axis instead of logf ).
5. Calculate the bandwidth of the amplifier using the expression BW= fH − fL .
6. Remove the emitter bypass capacitor CE from the circuit and repeat the
steps 3 to 5 and observe that the bandwidth increases and gain decreases
in the absence of CE .

Circuit diagram

VCC
+12 V
 R RC
2.2 k CC2 10 µF
1 + -
CC1 10 µF 47 Vo
k
- + B
BC107 C
E
RL
100 mV 10 680 +C
k Ω E
- 22 µF
C B E

Design
Output requirements: Mid-band voltage gain of the amplifier = 50 and required
output voltage swing = 10 V.
Selection of transistor Select transistor BC107 since its minimum
guaranteed
hF E (= 100) is more than the required gain (=50) of the amplifier.
Quick Reference data of BC107
Type: NPN-Silicon, Application: In audio frequency
 Maximum rating: VC B = 50 V, VC E = 45 V, VEB = 6 V, IC = 100 mA.
Nominal rating: VC E = 5 V, IC = 2 mA, hF E = 100 to 500.
DC biasing conditions VC C is taken as 20% more than required ouput swing.
Hence VC C = 12 V.
IC = 2 mA, because hF E is guaranteed 100 at that current as per data sheet.
In order to make the operating point at the middle of the load line, assume the dc
conditions VRC = 40% of VC C = 4.8 V, VRE = 10% of VC C = 1.2 V and VC E =
50% of VC C = 6 V .
Design of RC VRC = IC × RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k.
Design of RE VRE = IE × RE = 1.2 V. From this, we get RE = 600 Ω because
IE ≈ IC . Use 680 Ω std.
Design of voltage divider R1 and R2
Assume the current through R1 = 10IB and that through R2 = 9IB for a stable
voltage across R1 and R2 independent of the variations of the base current.
VR2 = Voltage drop across R2 = VBE + VRE .
i.e., VR2 = VBE + VRE = 0.6 + 1.2 = 1.8 V. Also, VR2 = 9IB R2 = 1.8 V
1.8
But IB = IC /hF E = 2 mA/100 = 20 µA. Then R = 9×20×10 −6 = 10.6 k. Use 10 k.
2
VR1 = voltage across R1 = VC C − VR2 = 12 V − 1.8 V = 10.2 V
10.2
Also, VR1 = 10IB R 1 = 10.1 V. Then R 1 = 10×20×10−6 = 50 k. Select 47 k std.
Design of RL : Gain of the common emitter amplifier is given by the expression
AV = −(rc /re ). Where rc = RC ||RL and re = 25 mV /IE = 25 mV /2 mA = 12.5 Ω.
Since the required gain = 50, substituting it in the expression we get, RL = 845 Ω.
Use 820 Ω std.
Design of coupling capacitors CC 1 and CC 2
XC 1 should be less than the input impedance of the transistor. Here, Rin is the
series impedance.
Then XC 1 ≤= Rin /10. Here Rin = R1 ||R2 ||(1 + hF E re ) because is RE
bypassed. We get Rin = 1.1 k. Then XC 1 ≤ 110 Ω.
So, CC 1 ≥ 1/2πfL × 110 = 14 µF . Use 15 µF std.
 Similarly, XC 2 ≤ Rout /10, where Rout = RC . Then XC E ≤ 240 Ω.
So, CC 2 ≥ 1/2π × 240 = 6.6 µF. Use 10 µF std.
Design of bypass capacitors CE
To bypass the lowest frequency (say 100Hz), XC E should be less than or equal to
the resistance RE .
i.e., XC E ≤ RE /10 Then, CE ≥ 1/(2π × 100 × 68) = 23 µF. Use 22 µF.
Graph
Gain in dB
Gain in dB
M dB
M-3 dB M dB
M-3 dB

log f log f
log fL log f H log fL log f H
With CE Without CE
Result
With CE :
Mid-band gain of the amplifier =. . . . . .
Bandwidth of the amplifier =. . . . . . Hz
Without CE :
Mid-band gain of the amplifier = . . . . . .
Bandwidth of the amplifier = . . . . . .Hz

Troubleshooting
1. Before the ac signal is applied, check dc conditions of the amplifier. Ensure that the
transistor is in active region by verifying that the E-B junction is forward biased and C-B
junction is reverse biased.
2. Replace RE by a pot and connect the bypass capacitor at the variable terminal of the pot.
Verify whether VBE = 0.6 V. This is very important.
3. If the output waveform gets clipped, reduce the amplitude of the input signal, vary RC
or adjust VC C slightly.
4. If the voltage at the collector VC = 12 V, collector circuit is not drawing current. Tran- sistor
is in cut off state. Base-emitter junction may not be forward biased.
5. If VC = 0, possible trouble is open collector circuit or collector shorted to earth. If
VE = 0, emitter is drawin

25
 Exp No: 3
Date:

INVERTING & NON INVERTING AMPLIFIER AND VOLTAGE

FOLLOWER

AIM: To design and set up the following basic op-amp circuits:

1) Inverting Amplifier
2) Non inverting Amplifier
3) Voltage Follower
And find out the frequency response characteristics.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp
Resistors
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

I Inverting Amplifier

A = -Rf/R1 (Voltage gain)

Take A =5
Rf = 5R1
Choose Rf = 10kΩ, R1=2kΩ

II Non-Inverting Amplifier
A = 1+ Rf/R1
Take A = 2
Rf = R1
Choose Rf = 10kΩ, R1=10kΩ

26
OBSERVATION:

1) Inverting Amplifier
Vi = 1V

f (Hz) Vo(V) Av(dB)

2) Non inverting Amplifier

Vi = 1V

f (Hz) Vo(V) Av(dB)

27
PROCEDURE:

I Inverting Amplifier

1. Construct the inverting amplifier circuit shown in figure.

2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Apply 1V amplitude, 1 kHz sinusoidal input signal to the amplifier.
5. Observe the input and output waveforms simultaneously on CRO.
6. Compare the phase of input and output signals.
7. Record the output waveform amplitude.
8. Increase the amplitude of the input until distortion occurs at the output.
9. Record the corresponding output amplitudes and plot a graph of the output
amplitude vs the input amplitude.

II Non-Inverting Amplifier

1. Construct the non-inverting amplifier as shown in the figure.

2. Apply 1V amplitude, 1 kHz sinusoidal input signal to the amplifier.
3. Observe Vin and Vo at the same time on the CRO.
4. Verify whether the output is in phase with the input.
5. Note down the output voltage by varying the frequency of the input signal.
6. Draw its frequency response characteristics.

28
III Voltage Follower

1. Wire up the voltage follower circuit.

2. Apply a sine wave of frequency 10 KHz, with amplitude of approximately 1.0 V to the circuit.
3. Observe Vin and Vo at the same time on the CRO.
4. Confirm that input and output amplitudes are equal.

RESULT:

CIRCUIT DIAGRAM

Inverting Amplifier Non inverting Amplifier

29
 Voltage follower

MODEL GRAPH:

30
 Exp No:
Date:

ASTABLE MULTIVIBRATORS

AIM: To design and set up an astable multivibrator circuit using op amp whose frequency of operation = 1
KHz.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp
Resistors
Capacitors
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:
1
Use R 2  1.16 R1 for equation f o  to be used
2 RC
Let R1  10k Then

R2= 11.6kΩ

Choose C=0.05µF and find R

R=10kΩ

31
 CIRCUIT DIAGRAM

MODEL GRAPH

OBSERVATION:

No: of Divisions Time/div Volt/div Time Period

Amp(V)
X axis Y axis (ms) (V) (ms)

32
 Output
Voltage

Voltage
across
capacitor

PROCEDURE:

1. Give the circuit connections as per the circuit diagram.

2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Observe the output from CRO.
5. Sketch the capacitor and output waveforms.
6. Measure the time period of the output voltage waveform and compare it with the designed value.
7. Repeat the procedure for different duty cycles.

RESULT:

33
 Exp No:
Date:

MONOSTABLE MULTIVIBRATORS

AIM: To design a monostable mutivibrator circuit for a pulse width of 1ms.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp
Resistors
Capacitors
Diode
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

34
 CIRCUIT DIAGRAM

MODEL GRAPH

35
OBSERVATION:

No: of Divisions Time/div Volt/div Time Period

Amp(V)
X axis Y axis (ms) (V) (ms)

Output
Voltage

Voltage
across
capacitor

PROCEDURE:

1. Construct the circuit connections as per the circuit diagram.

2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Adjust the signal generator to produce a 2V p-p, 200Hz square wave at the trigger input.
5. Observe the output from CRO.
6. Sketch the input and output waveforms.
7. Measure the pulse width of the output voltage waveform and compare it with the designed value.

RESULT:

Exp No:

36
 Date:

SCHMITT TRIGGER

AIM: To design and set up a Schmitt Trigger using op-amp for an LTP = 2V and a UTP = 3V.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp
Resistors
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

Assume Vo = Vcc-1V =  14v

( Vo  VF )  R 2
UTP =
R1  R 2

( Vo  VF )  R 2
LTP=
R3  R 2

VR 2
Here R 2 
I2

Where VR 2 is either UTP or LTP

I 2 is assumed as 50µA

PROCEDURE:

37
 1. Make connections according to the circuit diagram.
2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Adjust the signal generator to produce a 5Vp-p, 1 KHz sine wave as the input.
5. Verify the input and output simultaneously on CRO.
6. Measure and record the output amplitude and frequency.
7. Observe the hysterisis curve on CRO by keeping the time/div knob of CRO in x-y mode and
feed Vin to the x-channel and Vo to the y-channel.

RESULT:

38
 CIRCUIT DIAGRAM

MODEL GRAPH

Hysterisis curve

39
 Exp No:
Date:

TRIANGULAR WAVEFORM GENERATOR

AIM: To design a triangular wave generator using op amp whose frequency of operation = 1 KHz.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp 2
Resistors 3
Capacitors 1
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

Assume R1= 10kΩ, R2=10KΩ, R3=20KΩ C=0.01µF and  Vsat  14V

R3
f0  =500Hz
4 R1C R2

The Peak value of triangular wave is given by

R2
VP  Vsat =7V
R3

40
 CIRCUIT DIAGRAM

MODEL GRAPH:

OBSERVATION:

41
 No: of Divisions Time/div Volt/div Time Period
Amp(V)
X axis Y axis (ms) (V) (ms)

PROCEDURE:

1. Make the circuit connections are given as per the circuit diagram.
2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Measure the output voltage and time period and plot the output waveform.
5. Observe the change in the frequency of the output waveform by varying the values of resistances
R1, R2 and R3.

RESULT:

Exp No:
Date:

RC PHASE SHIFT OSCILLATORS

42
AIM: To design and set up an RC phase shift oscillator using op-amp whose frequency of oscillation = 1
KHz.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp
Resistors
Capacitors
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

Assume C=0.1µF

The frequency of oscillation is given by

1
fo 
2 6 RC

Therefore R=650Ω

To prevent the RC network from loading the amplifier it is selected such that R1  10 R

Thus we get R1 =6.5KΩ

R f  29R1 =188KΩ assume approximate value

43
 CIRCUIT DIAGRAM

MODEL GRAPH:

OBSERVATION:

No: of Divisions
Time/division Volt/division Amp(V) Time(ms)
X axis Y axis

44
PROCEDURE:

1. Check whether the op-amp is in good condition.

2. The circuit connections are given as per the circuit diagram.
3. Manually trace the circuit to check the correctness of physical connection.
4. Calibrate the CRO.
5. The amplitude and frequency of the sine wave is noted and the waveform is drawn.

RESULT:

45
 Exp No:
Date:

WIEN BRIDGE OSCILLATORS

AIM: To design and set up a Wien Bridge oscillator with and without amplitude stabilization using an
op-amp for a
frequency = 2 KHz.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity
Op amp
Resistors
Capacitors
Diode
JFET
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

I) Design of Wien Bridge oscillator without amplitude stabilization

The frequency of oscillation is given by

1
f 
2CR

Assume C=0.05µF

Therefore R=1.592KΩ use approx value 1.8KΩ

R f  2 R1  3.6k Use standard value 3.3 k

II) Design of Wien Bridge oscillator with amplitude stabilization using Diodes

Here Rf =R2+R3
RF
For sustained oscillation AV  1  should be 3
R1

46
Assuming R1=1.8KΩ we get RF =3.6KΩ
2VF
R2 Assuming I1 =1mA, R2=1.4KΩ.
I1
Thus R3=2.2kΩ

IRCUIT DIAGRAM WBO with

Amplitude Stabilization

MODEL GRAPH:

47
OBSERVATION:

No: of Divisions Time/div Volt/div Time Period

Amp(V)
X axis Y axis (ms) (V) (ms)

PROCEDURE:

1. Check whether the op-amp is in good condition.

48
 2. The circuit connections are given as per the circuit diagram.
3. Manually trace the circuit to check the correctness of physical connection.
4. Calibrate the CRO.
5. Observe the output waveform on the CRO and measure the amplitude and time period of the sine
wave.
6. Plot the output waveform.
7. Set up the circuit for amplitude stabilization.
8. Adjust the potentiometer to get the sine wave without any distortion and clipping.
9. Repeat the steps 5 and 6.

RESULT:

Exp No:
Date:

49
 ACTIVE SECOND ORDER FILTERS - LOW PASS FILTER

AIM: (i) To design and set up a second order low pass filter for a cut off frequency f o = 1 KHz.
(ii) To tabulate output voltage for various input frequencies by keeping input voltage constant.
(iii) To plot the gainVs frequency and find the 3dB cutoff frequency.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp
Resistors
Capacitors
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:
Assume C 2  0.01 F, f  1K Hz
XC1  R2 .
1
 R2 .
2 fC 2
1
R2   R2 .  11 .6 K
2 f C 2
R3  R2 .  11 .6 K  10 K  1K
C2  C3  0.01 F
for second order
 RF 
1  R1   1.586
 
Assume R1  10K
 then RF  5.86K  5.6 K  270

CIRCUIT DIAGRAM

50
MODEL GRAPH:

OBSERVATION:

Vin=1V

f(Hz) Vo (V) Av(dB)

51
PROCEDURE:

1. Construct the second order low pass filter circuit shown in the figure.
2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Apply a 1V, 100 Hz sinusoidal input signal and note down the output displayed on the oscilloscope.
5. Keeping the input amplitude constant increase the frequency of the input signal.
6. Record the output voltage and frequency on the tabular column.
7. Plot the frequency response characteristics and mark the filter cut off frequency.

RESULT:

52
 Exp No:
Date:

ACTIVE SECOND ORDER FILTERS - HIGH PASS FILTER

AIM: (i) To design and set up a second order high pass filter for a cut off frequency f o = 1 KHz.
(ii) To tabulate output voltage for various input frequencies by keeping input voltage constant.
(iii) To plot the gain vs frequency and find the 3dB cutoff frequency.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp
Resistors
Capacitors
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

53
 Assume C 2  0.01 F, f  1K Hz
XC1  R2 .
1
 R2 .
2fC 2
1
R2   R2 .  11 .6 K
2  fC 2
R3  R2 .  11 .6 K  10 K  1K
C2  C3  0.01 F
for second order
 RF 
1  R1   1.586
Assume R1  10K
 then RF  5.86K  5.6 K  270

CIRCUIT DIAGRAM

MODEL GRAPH:

OBSERVATION:

54
 Vin=1V

f(Hz) Vo (V) Av(dB)

PROCEDURE:

1. Construct the second order high pass filter circuit shown in the figure.
2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Apply a 1V, 100 Hz sinusoidal input signal and note down the output displayed on the oscilloscope.
5. Keeping the input amplitude constant increase the frequency.
6. Record the output voltage and frequency on the tabular column.
7. Plot the frequency response characteristics and mark the filter cut off frequency.

RESULT:

55
 Exp No:
Date:

ACTIVE SECOND ORDER FILTERS - BAND PASS FILTER

AIM: (i) To design and set up a second order band pass filter for a center frequency f o = 1 KHz and a pass
band of
Approximately  33Hz on each side of 1 KHz
(ii) To tabulate output voltage for various input frequencies by keeping input voltage constant.
(iii) To plot the gain Vs frequency and find the 3dB cutoff frequency.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Op amp

56
 Resistors
Capacitors
Power Supply 1
Signal generator 1
Bread board 1
CRO 1

DESIGN:

R2
R1 
2
R2  2QX C at f o
R1
R4 
2Q 2  1
From given above B= 66Hz
fo
Q= = 15.2
B
Assume R3  R2 =120KΩ
2Q
Thus C=  0.0403F
2f o R2
Choose the value of C1 = C2 = C

R2
R1  = 60KΩ
2
R1
R4  = 130.13Ω (use 150Ω standard value)
2Q 2  1
CIRCUIT DIAGRAM

57
MODEL GRAPH:

OBSERVATION:

Vin=1V

f(Hz) Vo (V) Av(dB)

PROCEDURE:

1. Construct the second order band pass filter circuit shown in the figure.
2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.

58
 4. Apply a 1V, 100 Hz sinusoidal input signal and note down the output displayed on the oscilloscope.
5. Vary the input frequency keeping the input amplitude constant.
6. Record the output voltage and frequency on the tabular column.
7. Plot the frequency response characteristics and mark the filter cut off frequency.

RESULT:

Exp No:
Date:

59
 IC VOLTAGE REGULATORS

AIM: To familiarize with the electrical characteristics of 723 general purpose voltage regulators.

PINOUT DIAGRAM

EQUIVALENT CIRCUIT

INFORMATION FROM DATASHEET:

 150 mA output current without external pass transistor

 Output currents in excess of 10A possible by adding external transistors
 Input voltage 40V max
 Output voltage adjustable from 2V to 37V
 Can be used as either a linear or a switching regulator

60
 Exp No:
Date:

LOW VOLTAGE REGULATOR USING 723 IC

AIM: To design and set up low voltage regulator and fold back voltage regulator using 723 voltage
regulator IC. Output
voltage = 6 V.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

Voltage Regulator IC
Resistors
Capacitors
Power Supply 1
Ammeter 1
Voltmeter 1
Bread board 1

DESIGN:

61
OBSERVATION:

Low voltage regulator

Line Regulation Load Regulation

Vin(V) Vo(V) IL(mA) Vo(V)

IL(mA) Vo(V)
Low voltage regulator using fold back

Line Regulation
Load Regulation

Vin(V) Vo(V)

62
 CIRCUIT DIAGRAM

Low Voltage Regulator LVR with Current Fold Back

63
MODEL GRAPH:

Low Voltage Regulator

LVR with Fold Back

PROCEDURE:

1. Check the IC and set up the circuit on the bread board as shown.
2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.

64
 4. Apply Vin from an unregulated power supply.
5. Connect a milli-ammeter and a rheostat in series with the output and connect a voltmeter in parallel.
6. To obtain the load regulation, vary the input and note down the corresponding variation in the
output voltage.
7. To obtain the line regulation, vary the rheostat from no load to full load and observe the
corresponding current and voltage.
8. The line and load regulation characteristics can be plotted from the readings.
9. The same procedure can be repeated for fold back regulator.
10. For fold back regulators load regulation, after a particular point the voltage and current decreases
suddenly from a point. Note this point correctly.
VNL  VFL
11. Calculate the % load regulation using the expression: x 100.
VNL

RESULT:

Exp No:
Date:

HIGH VOLTAGE REGULATOR USING 723 IC

AIM: To design and set up high voltage regulator and fold back voltage regulator using 723 voltage
regulator IC. Output
voltage = 12 V.

COMPONENTS AND EQUIPMENTS REQUIRED:

65
 Equipments / Components Specification / Range Quantity
Voltage Regulator IC
Resistors
Capacitors
Power Supply 1
Ammeter 1
Voltmeter 1
Bread board 1

DESIGN:

66
 CIRCUIT DIAGRAM

MODEL GRAPH:

Line Regulation Load Regulation

OBSERVATION:

Line Regulation Load Regulation

Vin(V) Vo(V) IL(mA) Vo(V)

67
PROCEDURE:

1. Check the IC and set up the circuit on the bread board as shown.
2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Apply Vin from an unregulated power supply.
5. To obtain the load regulation, vary the input and note down the corresponding variation in the
output voltage.
6. To obtain the line regulation, vary the rheostat from no load to full load and observe the
corresponding current and voltage.
7. The line and load regulation characteristics can be plotted from the readings.

RESULT:

68
 Exp No:
Date:

GENERAL DESCRIPTION LM555 TIMER

The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional
terminals are provided for triggering or resetting if desired. In the time delay mode of operation,
the time is precisely controlled by one external resistor and capacitor. For astable operation as an
oscillator, the free running frequency and duty cycle are accurately controlled with two external
resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the
output circuit can source or sink up to 200mA or drive TTL circuits.

69
 Exp No:
Date:

MONOSTABLE MULTIVIBRATOR

AIM: To design and set up a monostable multivibrator using 555 timer Ic to obtain.
a. 50% duty cycle
b. 70% duty cycle

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

LM555
Resistors 1
Power Supply 1
Signal generator 1
Bread board 1
Capacitor 2
CRO 1

Design: Monostable multivibrator for T  1ms

T  1.1RC
C  0.1F
1m
RA   10 K
0.1 * 1.1

70
 CIRCUIT DIAGRAM

MODEL GRAPH:

71
 Trigger input

Output at pin 3

Output at pin 6

PROCEDURE:

1. Assemble the circuit as illustrated in figure.

2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Observe the corresponding output of the op amp for different digital inputs.

RESULT:

72
 Exp No:
Date:

ASTABLE MULTIVIBRATOR

AIM: To design and set up a astable multivibrator using 555 timer Ic.

COMPONENTS AND EQUIPMENTS REQUIRED:

Equipments / Components Specification / Range Quantity

LM555 1

73
 Resistors 2
Power Supply 1
Bread board 1
Capacitor 1
CRO 1

Design: Astable Multivibrator for T=1ms

TON = 0.69( R A + RB )*C
TOFF = 0.69 RB * C
T = TON + TOFF
T = 0.69( R A +2 RB )*C
1.45
f = 1/T =
( R A  2 RB )C
TOFF
% Duty cycle D = *100
T
RB
D=  100
( R A  2 RB )
Let TON =0.7 m sec and TOFF =0.3ms
Choose C = 0.1µf

We get R A =6.8KΩ and RB =4.7 KΩ

74
 CIRCUIT DIAGRAM

MODEL GRAPH:

75
 Output at pin 3

Output at pin 6

PROCEDURE:

1. Assemble the circuit as illustrated in figure.

2. Manually trace the circuit to check the correctness of physical connection.
3. Calibrate the CRO.
4. Observe the corresponding output of the op amp for different digital inputs.

RESULT:

76
77