Lecture-1

Low Power VLSI Design

 Why Low Power?

❖ Important issue in the present day VLSI circuit realization

✓ Increasing Transistor Count
✓ Higher Speed of Operation
✓ Greater Device Leakage Currents

❖ Packaging and Cooling Cost

✓ Contemporary high performance processor consume heavy power
✓ Cost associated with packaging and cooling such devices is prohibitive
✓ Low power methodology to be used to reduce cost of packaging and cooling

❖ Reliability
✓ Every 10°C rise in temperature roughly doubles the failure rate
Power and Energy

Power is the instantaneous power in the device,

1. Peak power: Peak power
while energy is the integration of power with
consumed by a particular device is
time. the battery life is primarily determined by the highest amount of power it can
this energy consumed consume at any time. The high
value of peak power is generally
related to failures like melting of
some interconnections and power-
line glitches.

2. Average power: Average power

consumed by a device is the mean of
the amount of power it consumes over
a time period. High values of average
power lead to problems in packaging
and cooling of VLSI chips.
Sources of Power Dissipation

The average power dissipation in conventional CMOS digital circuits can be classified
into three main components, namely,

(1) The dynamic (switching) power dissipation

(2) The short-circuit power dissipation and
(3) The leakage power dissipation.

If the system or chip includes circuits other than conventional CMOS gates that have continuous
current paths between the power supply and the ground, a fourth (static) power component should
also be considered
Types of Power Dissipations
Switching Power Dissipation
In digital CMOS circuits, dynamic power is dissipated when energy is drawn from the
power supply to charge up the output node capacitance. During the charge-up phase, the output
node voltage typically makes a full transition from 0 to VDD, and the energy used for the
transition is relatively independent of the function performed by the circuit.

The total capacitive load at the output of the NOR gate consists of
(1) The output capacitance of the gate itself
(2) The total interconnect capacitance, and
(3) The input capacitances of the driven gates.
The first and primary source
of dynamic power
consumption is the
Switching power dissipation
occurs due the power
required to charging and
discharging of the output
capacitance on a gate.
Cont.
❖ Output capacitance:
✓ The output capacitance of the gate consists mainly of the junction parasitic capacitances, which are due to the drain
diffusion regions of the MOS transistors in the circuit.
✓ The important feature to highlight here is that the amount of capacitance is approximately a linear function of the
junction area. So, the size of the total drain diffusion area determines the amount of parasitic capacitance

❖ Total interconnect capacitance:

✓ The interconnect lines between the gates contribute to the total interconnect capacitance.
✓ Note Particularly in sub-micron technologies, the interconnect capacitance can become the dominant component,
compared to the transistor-related capacitances

❖ Input capacitances:
✓ The input capacitances are mainly due to gate oxide capacitances of the transistors connected to the input terminal.
✓ Again, the amount of the gate oxide capacitance is determined primarily by the gate area of each transistor
Cont.
Generic representation of a CMOS logic gate for switching power calculation
 Cont..

The average power dissipation of the CMOS logic gate, driven by a periodic input voltage waveform with
ideally zero rise- and fall-times, can be calculated from the energy required to charge up the output node to
VDD and charge down the total output load capacitance to ground level

Simplifying this integral gives the well-known expression for the average dynamic (switching) power
consumption in CMOS logic circuits.

Note the average switching power dissipation of a CMOS gate is essentially independent of all transistor
characteristics and transistor sizes.
Cont.

• Effect of reducing the power supply voltage VDD on switching power dissipation
The analysis of switching power dissipation presented above is based on the assumption that the output
node of a CMOS gate faces one power-consuming transition (0-to-VDD transition) in each clock cycle. This
assumption, however, is not always correct; the node transition rate can be smaller than the clock rate,
depending on the circuit topology, logic style and the input signal statistics.

To better represent this behavior, we will introduce αT (node transition factor), which is the effective
number of power-consuming voltage transitions experienced per clock cycle
Where Ci represents the parasitic capacitance associated with
each node and α Ti represents the corresponding node
transition factor associated with that node
Short-Circuit Power Dissipation:
A CMOS inverter and its transfer curve Short-circuit current of a CMOS inverter
during input transition
• The shape of the short-circuit current curve is dependent on several factors:
1. The duration and slope of the input signal
2. The I-V curves of the P and N transistors, which depend on their sizes, process technology, temperature, etc
3. The output loading capacitance of the inverter

• Under an input ramp signal, a first order analysis of the short-circuit current reveals that the energy dissipated
is

where β is the size of the transistors and 't is the duration of the input signal
 Short-circuit Current Variation with Output Load

Total current under varying output capacitance

Short-circuit current under varying output capacitance

Effects of deteriorating input signal slope

Total current under different input signal slopes.

Effects of deteriorating input signal slope

Short-circuit under different input signal slopes

• A 32 bit off-chip bus operating at 5V and 66MHz clock rate is driving a capacitance of 25pF/bit. Each bit is
estimated to have a toggling probability of 0.25 at each clock cycle. What is the power dissipation in
operating the bus?
• The chip size of a CPU is I5mm x 25mm with clock frequency of 300MHz operating at 3.3Y. The length of
the clock routing is estimated to be twice the circumference of the chip. Assume that the clock signal is routed
on a metal layer with width of 1.2um and the parasitic capacitance of the metal layer is 1 fF/um2. What is the
power dissipation of the clock signal?