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Analog and Digital VLSI Design Analog Assignment

The document describes the design of a two-stage fully differential OTA. It includes: 1) The schematic of the OTA with a folded cascode first stage and a gain stage. 2) Calculations of transistor widths and lengths to meet specifications such as gain bandwidth of 400MHz. 3) Plots showing the circuit meets specifications for parameters like DC gain, phase margin, output swing, and slew rate.

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Adrian Chase
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83 views

Analog and Digital VLSI Design Analog Assignment

The document describes the design of a two-stage fully differential OTA. It includes: 1) The schematic of the OTA with a folded cascode first stage and a gain stage. 2) Calculations of transistor widths and lengths to meet specifications such as gain bandwidth of 400MHz. 3) Plots showing the circuit meets specifications for parameters like DC gain, phase margin, output swing, and slew rate.

Uploaded by

Adrian Chase
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Analog and Digital VLSI Design

Analog Assignment

Prepared By

Piyush Bhatt 2017A3PS0206P


Dhruv Jain 2017A3PS0336P
Botlaguduru Satvik 2017A8PS0421P

Birla Institute of Technology and Sciences, Pilani


Problem Statement:67

Design a two-stage Fully-Differential OTA (Folded Cascode


[Differential amplifier + common gate stage] + gain stage).
a) Analog schematic for OTA.
b) Analysis of all equations for OTA, with a systematic derivation of all
transistors W/L ratios and spectre simulation of circuit for the following
specifications.
i) UGB ≥ 400 MHz
ii) Phase margin ≈ 550 - 650
iii) Output voltage swing differential ≈ 3V
c) Show the biasing circuitry to bias all the voltages in your design (except
the input).
d) Calculate and plot the following parameters for your OPAMP: DC gain,
Bode plot for AC gain and phase, ICMR plot, slew rate, Differential Output
Swing (dc + Transient), power consumption, and input and output offset
voltage.
Theory
Operational amplifiers (op amps) are an integral part of many analog and
mixed-signal systems. Op amps with vastly different level of complexity are
used to realize functions ranging from dc bias generation to high-speed
amplification or filtering. In an Op amp the cascoding of transistors
increases the gain while limiting the output swings. In some applications
the gain and/or the output swings provided by Cascode op amps are not
adequate. In such cases, we resort to "two-stage" op amps, with the first
stage providing a high gain and the second, large swing. In contrast to
Cascode op amps, a two-stage configuration isolates the gain and swing
requirements.
Schematic
Calculation of W/L’s
Unity Gain Bandwidth >= 300MHz

Using this formula we calculated gm for for M9 and M10.


Using the specification given for Power dissipation(<=3mW), we get the I
for the circuit. P = Vdd.I
Setting currents such that maximum dissipation under maximum range M1
and M2 , we further divide these currents in two equally flowing through the
further branches (through M9 and M10).
Now using the equation for gm we calculate W/L ratio for M9 and M10.
For W/L ratio of M19, we needed to set the Vov of M19 to a fixed value
which we took to be 0.2V as an assumption. Corresponding to that we
calculated the W/L of M19 using the saturation current equation of a MOS.
Similarly we know the currents through the MOS M5, M6, M7, M8.
Assuming Vov to be 0.2V and knowing the current, we calculate the W/L for
those transistors as well using the same equation.
Using the same procedure, we calculate W/L values for the other
MOSFETs. For the current biasing MOSFETS, ratio of currents flowing
through them also has to be kept in mind, and hence current source is
connected accordingly.
After some calculations and adjusting W/L ratios of the MOSFETs a
suitable value of current was chosen such that all MOSFETs are in
saturation and UGB requirements are met.
W/L values Table
Transistor W L W/L
Name
M1 35um 350nm 100
M2 35um 350nm 100
M3 17.5um 350nm 50
M4 17.5um 350nm 50
M5 0.5um 350nm 1.428
M6 0.5um 350nm 1.428
M7 0.5um 350nm 1.428
M8 0.5um 350nm 1.428
M9 14um 350nm 40
M10 14um 350nm 40
M11 1um 350nm 2.857
M12 35um 350nm 100
M13 20um 350nm 57.142
M14 20um 350nm 57.142
M15 15um 350nm 42.857
M16 15um 350nm 42.857
M17 20um 350nm 57.142
M18 20um 350nm 57.142
M19 20um 350nm 57.142
C(load)=0.1pF
DC Gain and AC gain/Phase Margin Bode Plot

For DC gain, AC gain and phase bode plot, AC analysis was done for the
circuit and ratio of Inputs and Outputs (gain in dB) was plotted against
frequency. From the graph it was observed that the
DC Gain = 23.22 dB
UGB = 371dB (Approximately)
Phase Margin = 62.1 degrees

Slew Rate
For calculation of slew rate, pulse inputs were given to the inputs with a
180 degree phase difference and a transient analysis was performed. The
output difference was plotted with respect to time. The slopes of rising and
falling give us the positive and negative slew rate respectively.
(a) Positive Slew Rate

Positive Slew Rate = 13.8 V/us

(b) Negative Slew Rate

Negative Slew Rate = -4.84V/us


ICMR
For ICMR, the inputs were DC swept from -1.25 to 1.25 with a step us 0.3
V. The output difference was plotted against Voltage.

From the graph, it can be seen that ICMR = 218.6mV

Output Voltage Swing Differential


For Output Voltage swing differential, transient analysis of the circuit was done
giving AC inputs to the input voltages.
From the above graph, we see,
Output Voltage Swing Differential = 2*(995mV+995mV)
= 3.98 V
DC Operating Points
The following are the DC operating points obtained from the circuit.
From the above DC operating points we calculated the following
I(VDD)=0.00495432 A
I(VSS)=0.00579591 A
Power Consumption= Vdd * I(Vdd) + Vss * I(Vss)
= 1.25 * 0.00495432 + 1.25 * 0.00579591= 13.4377 mW
On connecting the inputs to ground and getting the DC operating points,

Output Offset Voltage= -0.02 V


Performing a DC sweep on a common voltage souce(input) we get,(at 0V)

Input Offset Voltage= 1.2 V

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