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Digital Electronics: Inst Ruct Ions T O Cand Idat Es

This document contains instructions and questions for a digital electronics exam. It lists 8 questions related to topics like Boolean algebra, Karnaugh maps, magnitude comparators, parallel adders/subtractors, FPGA, synchronous counters, EPROM, shift registers, and master-slave JK flip-flops. Students are instructed to attempt any 5 questions, with each question worth 12 marks, over a time period of 2 hours. The document also contains standard instructions warning students that cheating or sharing exam materials would be treated seriously.

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Armaan
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34 views2 pages

Digital Electronics: Inst Ruct Ions T O Cand Idat Es

This document contains instructions and questions for a digital electronics exam. It lists 8 questions related to topics like Boolean algebra, Karnaugh maps, magnitude comparators, parallel adders/subtractors, FPGA, synchronous counters, EPROM, shift registers, and master-slave JK flip-flops. Students are instructed to attempt any 5 questions, with each question worth 12 marks, over a time period of 2 hours. The document also contains standard instructions warning students that cheating or sharing exam materials would be treated seriously.

Uploaded by

Armaan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Roll No. Total No.

of Pages : 02
Total No. of Questions : 08
B.Tech (CSE)/(IT) (Sem.–3)
DIGITAL ELECTRONICS
Subject Code : BTES-301-18
M.Code : 76435
Date of Examination : 21-10-21
Time : 2 Hrs. Max. Marks : 60

INST RUCT IONS T O CANDIDAT ES :


1. Attempt any FIVE question(s), ea ch que stion c arrie s 12 marks.

1. Using the Boolean Algebra, simplify the expression :

AB   A  B  C  AB

2. Use a Karnaugh map to simplify the function to its minimum sum of product form :

X  ABCD  ABCD  ABCD  ABCD

3. Draw the block schematic of Magnitude comparator and explain its operation.

4. Draw & explain the block diagram of a 4-bit parallel adder / Sub-tractor.

5. Write a note on FPGA with a neat diagram.

6. Simplify using K-map.

f (ABCDE) = ΠM(6,9,11,13,14,17,20,25,28,29,30) and implement using NAND/NOR


logic.

7. a) Explain the principle of operation of a dual slope ADC. How is it advantageous over
ramp type ADC?

b) Design a synchronous Mod-6 counter using JK-flip-flops.

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8. Write short notes on any Two :

a) EPROM

b) Shift register

c) Master-slave JK flip-flop

Note: Any student found attempting answer sheet from any other person(s), using
incriminating material or involved in any wrong activity reported by evaluator shall be
treated under UMC provisions.
Student found sharing the question paper(s)/answer sheet on digital media or with any
other person or any organization/institution shall also be treated under UMC.
Any student found making any change/addition/modification in contents of scanned copy of
answer sheet and original answer sheet, shall be covered under UMC provisions.

2|M - 76435 65

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