Introduction to AVR Architecture

(AVR chip)
Ismail Ariffin
ECE, SKE, FE, UTM, Skudai, Johor
2019/2020
 Contents
• AVR background history, AVR family groups,
AVR Architecture, Atmega32 programming
model
 AVR
(Advanced Virtual RISC)
 Introduction to AVR
• The AVR architecture was designed by two students Alf-Egil Bogen and
Vegard Wollan in Norway and then was bought and developed by
Atmel in 1996. Atmel Corporation is an American-based designer and
manufacturer of semiconductors, founded in 1984. The company
focuses on embedded systems built around microcontrollers.
• There are many kind of AVR microcontroller with different properties
such as 8-bit AVR and 32-bit AVR. Open AVR Studio to see list of AVR
microcontrollers.
• Except for AVR32 (32-bit microcontroller), AVRs are all 8-bit
microprocessors – the CPU can work only 8 bits of data at a time.
• Data larger that 8 bits has to be broken into 8-bit pieces to be
processed by the CPU.
• The AVR is a modified Harvard architecture machine where program
and data is stored in separate physical memory systems that appear in
different address spaces, but having the ability to read data items from
program memory using special instructions.
 AVR Family Overview
• AVRs are generally classified into four groups:
o Classic AVR (AT90Sxxxx)
o This is the original AVR chip
o i.e. AT90S2313, AT90S4433
 AVR Family Overview
o Mega AVR (ATmegaxxxx)
o These are powerful microcontrollers with more than 120
instructions
o Has lots of different peripheral capabilities, which can be
used in different designs.
o i.e. ATmega8, ATmega32, ATmega128
 AVR Family Overview
o Tiny AVR (ATtinyxxxx)
o Has less instructions and smaller packages compared to
mega family.
o Can design systems with low cost and power consumption
using Tiny AVRs.
o i.e. ATtiny13, ATtiny25
 AVR Family Overview
o Special purpose AVR
o The ICs of this group can be considered as a subset of other
groups.
o But their special capabilities are made for designing specific
applications such USB controller, CAN controller, LCD
controller, Zigbee, Ethernet controller, FPGA.
o i.e. AT90PWM216,AT90USB1287
Let’s get familiar with AVR part number

ATmega128

Atmel mega
ROM =128K
group

ATtiny44 AT90S4433

Atmel
Tiny ROM =4K Atmel Classic
ROM =4K
group group
 ATmega32 vs ATmega16
ATmega32 ATmega16
Number of instructions 131 131
Flash program memory 32K 16K
Internal SRAM 2K bytes 1K bytes
EEPROM 1K bytes 512 bytes
External memory none none
General-purpose 8-bit registers 32 32
IO ports 4 4
Serial interfaces SPI, USART, Two-wire SPI, USART, Two-wire
Timers two 8-bit, one 16-bit two 8-bit, one 16-bit
PWM channels 3 4
Analogue comparator, Analogue comparator,
ADC
8-channel 10-bit ADC 8-channel 10-bit ADC
Interrupt vectors 21 21
 ATMega32 Pin out & Descriptions
Clears all the
registers and
restart the
execution of
program -reset

Provides supply
voltage to the chip.
Port
It should be B Port A
connected to +5 -
vcc Reference voltage
for ADC-aref
These pins are
used to connect
external crystal or Supply voltage for
RC oscillator -xtal ADC and portA.
Port Cit to VCC -
Connect
Port D acc

Module 2/11
 ATMega32 Pin out & Descriptions

Digital IO is the most fundamental mode of connecting a MCU to external

world. The interface is done using what is called a PORT. A port is the point
where internal data from MCU chip comes out or external data goes in. They
are present is form of PINs of the IC. Most of the PINs are dedicated to this
function and other pins are used for power supply, clock source etc . ATMega32
ports are named PORTA, PORTB, PORTC, and PORTD.

Module 2/12
Atmega32 Pinout

Module 2/13
ATMega32 Pin out & Descriptions

Mega32/Mega16
(XCK/T0) PB0 PA0 (ADC0)
(T1) PB1 PA1 (ADC1)
(INT2/AIN0) PB2 PA2 (ADC2)
(OC0/AIN1) PB3 PA3 (ADC3)
(SS) PB4 PA4 (ADC4)
(MOSI) PB5 PA5 (ADC5)
(MISO) PB6 PA6 (ADC6)
(SCK) PB7 PA7 (ADC7)
PINA

PORTB
DDRB
PINB
RESET DDRA AREF
PORTA
VCC AGND
PORTC
GND DDRC AVCC
PINC
XTAL2 PC7 (TOSC2)
XTAL1 PC6 (TOSC1)
(RXD) PD0 PC5 (TDI)
(TXD) PD1 PC4 (TDO)
(INT0) PD2 PC3 (TMS)
(INT1) PD3 PC2 (TCK)
(OC1B) PD4 PC1 (SDA)
(OC1A) PD5 PC0 (SCL)
(ICP) PD6 PD7 (OC2)

Module 2/14
ATMega32 Pin out & Descriptions

Module 2/15
 ATMega32 Pin out & Descriptions
Defining a pin as either Input or Output – The DDRx Registers

LDI R20,0x75 ;R20 = 0b01110101 (binary)

OUT PORTA,R20 ;PORTA = R20
OUT DDRA,R20 ;DDRA = R20

DDRx = 0b01110101; /* Configuring I/O pins of portb */

Module 2/16
 ATMega32 Pin out & Descriptions
Case 1 : To make a pin go high or low ( if it is an output pin)- Data Register PORTx

Module 2/17
 ATMega32 Pin out & Descriptions
The PINx register gets the reading from the input pins of the MCU

Module 2/18
 ATMega32 Pin out & Descriptions

Pull-up resistors are used in electronic logic circuits to ensure that

inputs to logic systems settle at expected logic levels if external
devices are disconnected or high-impedance

vcc
1 = Close
PORTx.n 0 = Open

pin n of
port x PINx.n

Outside the Inside the

AVR chip AVR chip

Module 2/19
 ATMega32 Pin out & Descriptions

Case 2 : To activate / Deactivate pull up resistors-Data Register PORTx

DDRx
DDRx.n 0 1
PORTx
PORTx.n high impedance Out 0
0
1 pull-up Out 1
PINx.n

Module 2/20
AVR Architecture
AVR Architecture

Module 2/22
 Definition of AVR architecture
• What is AVR?
– AVR, an acronym of Advanced Virtual RISC, is a
microcontroller featured in ATMEL based
embedded system.
• What is AVR architecture and organization?
– a set of hardware units featured in AVR
– CPU, registers, memory
– Program memory and data memory use separated
busses to CPU.
 AVR Architecture
o AVR uses Harvard architecture, that has separate buses for the
code and data memory.
o Two kind of busses in AVR;
o Program Bus – provide access to Program Flash ROM.
o Data Bus – to bring data to the CPU.
 AVR SYSTEM BUSES
• Address Bus
– 16 bit Unidirectional line
– carry address to select data storage location in the
system
• Data Bus
– 8-bit Bidirectional line
– channel to carry data in and out the processor
• Control Bus
– Unidirectional line (majority)
– Bidirectional (minor)
– carry control signal to acknowledge processor
operation activity, for examples: read, write
 AVR CPU

• PC: address of next

instruction
• IR: prefetched
instruction
• ID: current instruction
• GPR: R0-R31
• ALU: Note internal
data path

2/15/2020 26
 CPU internal activity
• Fetch instruction from memory
– Code in IR register
Fetch
• Decode instruction
– Interpret & Enable the required
circuits for operation
• Fetch data (if applicable) Execute Decode
– Data from resources
• Execute instruction

CPU operation cycle

 ALU Operation & Assembly Instruction
ALU /CPU Assembly Operan Operation Description
Function mnemonic d (Register Transfer
Language - RTL)
Add Wihout Carry ADD Rd,Rs Rd Rd + Rs Add Rd to Rs, store at Rd
Add with Carry ADC Rd,Rs Rd Rd +Rs + C Add Rd with Rs and Carry, store at Rd
Subtract SUB Rd,Rs Rd Rd - Rs Rd subtracts Rs,store at Rd
Subtract Immediate SUBI Rd,K Rd Rd + K Rd subtracts K, store at Rd
Subtract with Carry SBC Rd,Rs Rd  Rd – Rs - C Rd subtracts Rs and C, store at Rd
AND AND Rd,Rs RdRd v Rs ANDing Rd with Rs, store at Rd
OR OR Rd,Rs Rd Rd Λ Rs ORing Rd with Rs, store at Rd
Exclusive-OR EOR Rd,Rs Exclusive-OR between Rd and Rs, store at Rd
Logical Shfit Right LSR Rd Rd  Rd << 1,Rd[7]<- Shift right R18, R18[msb]0
Rotate Left ROL Rd 0 Rotate left R21, CR21[msb], R21[lsb]C
Rd  Rd >> 1,
Rd[7]C, CRd[0]
Load Immediate LDI Rd,K Rd  K Load Rd with a constant value, K
Load Data Space LDS Rd,k Rd [k] Load Rd from memory k address
Store Data Space STS k,Rs [k]  Rs Store memory k address from Rs
Ones Complement COM Rd Rd  ~Rd Ones complement of R10
Multiply Unsigned MUL Rd,Rs R1:R0 Rd X Rs Multply signed R16 and R17, result saves in
R1 (high byte result) and R0 (low byte result)
AVR Processor - ATmega32 Registers
ATMega32 Programmer Model: Registers (GPRs)

 The R26..R31 registers have some added functions to their general

purpose usage. These registers are 16-bit address pointers for indirect
addressing of the Data Space. The three indirect address registers X, Y,
and Z are shown above.
 In the different addressing modes these address registers have
functions as fixed displacement, automatic increment, and automatic
decrement

Module 2/30
 General Purpose Register in AVR
o AVR microcontrollers have many registers for arithmetic and
logic operations.
o In CPU, registers are used to store information temporarily.
o That information could be;
o A byte of data to be processed
o And address pointing to the data to be fetched.
o The vast majority of AVR registers are 8-bit registers because in
AVR only one data type: 8-bit.
MSB LSB

o With an 8-bit data type, any data larger than 8 bits must be
broken into 8-bit chunks before it is processed.
 General Purpose Register in AVR
o In AVR there are 32 general purpose
registers.
o They are R01-R31 and are located in
the lowest location of memory
address.
o To understand of the purpose of
general purpose registers, two
simple instructions LDI and ADD is
used as example.
o LDI R16,10
o Load register R16 with value 10
o ADD R2,R18
o Add data in R2 with data in R18 and
save result in R2
AVR Memory
• Flash: Machine
instructions (program) go
here
• SRAM: For run time data
– Note bus independence for
data and instructions
• EEPROM: Secondary
storage
– EEPROM and Flash
memories have a limited
lifetime of erase/write
cycles

Dr. Tim Margush - Assembly Language

2/15/2020 33
Programming
 Memory

Memory Address-1  Memory Location-1

Memory Address-2  Memory Location-2

1 2 3 4 5 6 7 8

1 byte = 8-bit data

1 word= 2 bytes
1 double = 2 words

Memory Address-n  Memory Location-n

Number of addresses 2N (where N is an integer)

 Internal Data SRAM
o Internal data SRAM widely used for storing data and parameters
by AVR programmers and C compilers.
o Each location of the SRAM can be accessed directly by its
address.
o Each location is 8 bits wide and can be used to store any data we
want.
o The size of SRAM can be vary from chip to chip.
 AVR Data Memory
o Two kinds of memory
space in AVR:
o Code memory space –
where program is stored.
o Data memory space –
stores data.
o The data memory is
composed of three parts:
o General purpose register.
o I/O memory (Special
Function Register)
o Internal data SRAM
 ATMega32 Programmer Model: Memory

• AVR microcontrollers are Harvard

architecture. This means, that in this
architecture are separate memory types
(program memory and data memory)
connected with distinct buses. Such memory
architecture allows processor to access
program memory and data memory at the
same time. This increases performance of
MCU comparing to CISC architecture, where
CPU uses same bus for accessing program
memory and data memory.

• Each memory type has its own address space:

Type Flash RAM EEPROM
F_END Size, kB RAMEND Size, kB E_END Size, kB
Atmega8 $0FFF 8 $045F 1 $1FF 0.5
Atmega32 $3FFF 32 $085F 2 $3FF 1
Atmega64 $7FFF 64 $10FF 4 $7FF 2
Atmega128 $FFFF 128 $10FF 4 $FFF 4

Module 2/37
ATMega32 Programmer Model: Internal SRAM

• Internal data SRAM is widely used for storing data and

parameters by AVR programmers and C compilers.

• Each location of the SRAM can be accessed directly by its

address.

• Each location is 8 bit wide and can be used to store any

data we want.

• Size of SRAM is vary from chip to chip, even among

members of the same family.

Module 2/38
 AVR DATA TYPE
Data Type Binary Signed Decimal Hexadecimal Binary
Coded
Decimal
(BCD)
Digit 0 and 1 0 and 1 0 to 9 0 to 9,A to F 0 and 1

Example: 0b00000000 Negative All All positive: 0 to 99

8-bit or to binary: positive 0 to $FF
byte 0b11111111 0b1000000 to :0 to 255 Negative:
value 0b11111111, Negative: $80 to $FF
range Positive -128 to - Postiive:
binary: 1, $00 to $7F
0b00000000 Positive:
to 0 to 127
0b01111111
o Data Prefix Symbol Data Symbolic Unit Presentation
o K (Kilo) = 210 = 1024 Use $ or 0x for hexadecimal
o M (Mega) = 220 = 1,048,576 Use % or 0b for binary
o G (Giga) = 230 Default is decimal
 I/O Memory
o The I/O memory or special function memory stores information
dedicated to specific function such as status register, timers,
serial communication, I/O ports, ADC and etc.
o The function of each I/O memory location is fixed by the CPU
designer.
o The number of locations in the data memory set aside for I/O
memory depends on the pin numbers and peripheral functions
supported by that chip.
o But, all off the AVRs have at least 64 bytes of I/O memory
locations called standard I/O memory.
I/O Memory
I/O Memory
 AVR MEMORY ARCHITECTURE
Memory Organization Capacity Address Size Data Size Address
(#bit) (#bit)

SRAM 1K x 8 1K Bytes 10 8 0x60 to 0x45F

2K x 8 2K bytes 11 0x60 to 0x85F

ROM 16K x 8 16K bytes 14 8 $0 to $3FFF

32K x 8 32K bytes 15 $0 to $7FFF
64K x 8 64K bytes 16 $0 to $FFFF

EEPROM 1K x 8 1Kbytes 10 8 $0 to $3FF

 SUMMARY
• Know AVR Architecture for programming
usage which are five types of processor
registers, ROM, RAM and I/O memory.
• Know the structure and the profile of
AVR Memory