1

Real-Time implementation of a SPLL for FACTS.

Francisco D. Freijedo, Jesús Doval-Gandoy, Member, IEEE, Óscar López, Member, IEEE, David Piñeiro,
Carlos M. Peñalver, Member, IEEE, Andrés A. Nogueiras, Member, IEEE
Electronics Technology Department
University of Vigo
ETSI Industriales, Campus Lagoas
36200 Vigo, SPAIN
Email: [email protected]; [email protected]; [email protected]

Abstract— This paper presents a real-time implementation of a Va Vd

software phase-locked loop (SPLL) for using in FACTS systems. Vb Clarke & Park
The FACTS phase locked loops (PLLs) main characteristics and Vc Transformations Vq w
A
,

q
PI 1/s
A A

the disturbances impact over their performance are reviewed

making special emphasis on the weak points of the usual three- A q
phase trans-vector-type PLLs. These weak points are mainly slow
response under low amplitude ac inputs and three-phase unbal-
ances. Recently some alternatives, specially the adaptive SPLL,
solved these typical trans-vector issues. However, the discrete Fig. 1. Trans-vector-type three-phase PLL.
implementation of adaptive SPLL in a programmable device like
a microcontroller, a DSP or a FPGA seems very complex. In
this work a double-loop SPLL has been developed with the aim They have demonstrated that the PLL delay leads to an uncon-
of reducting the complexity of a discrete implementation and
trolled exchange of real and reactive between the STATCOM
without losing performance with respect to the adaptive SPLL.
The proposed double-loop SPLL has been implemented in real- and the transmission line. They have obtained similar results
time using Matlab/Simulink and the fast prototyping platform for SSSC; furthermore, in SSSC, when a disturbance in the
dSpace DS1103; its high performance and feasibility are shown power system occurs, large overshoot and undershoot appears
in the simulation and real-time implementation sections. in the dc capacitor voltage. Therefore, by improving the PLL
speed the performance of FACTS devices are enhanced.
I. I NTRODUCTION PLL performance is critical in control of dynamic voltage
restorer (DVR) too. Especially, when a DVR is protecting a
A. Background phase-shift sensitive load, the PLL speed of response to detect
Phase Locked Loops (PLLs) are widely used in the control these phase-shifts becomes crucial [4]. The different control
of FACTS. Their principal use is to track the positive sequence strategies of DVR use the fault information to calculate the
phase of the grid three-phase ac signal. Furthermore PLLs injected voltage; therefore, the faster the PLL obtains this
should provide frequency and amplitude measurements. PLL information, the faster the DVR response is.
outputs are used to calculate the switching times of devices in
the control loop of FACTS; therefore they have an important
role in system dynamics and performance [1]. Indeed, the C. Characteristics of PLLs working connected to grid
speed of response and accurate of PLL becomes especially
As it has been shown, PLLs used in FACTS work connected
critical when a transient happens in the distribution system.
to three-phase grid; they mainly have to track the phase-angle
Lately, the FACTS requirements on power quality, perfor-
of the positive sequence of the fundamental component of
mance and fault recovery have been increased, and the control
voltage.
systems developed has became more and more sophisticated.
The most widely used three-phase PLLs using in FACTS
However the role of PLLs in these control systems is not still
are based on the trans-vector-type PLL [2]. Trans-vector-type
investigated enough [2]. In this work a single-phase software
PLLs use the Park’s and Clarke’s transformations for changing
PLL is presented as an alternative to the most widely used →
−
the natural reference frame ( V abc ) to the rotating reference
three-phase trans-vector-type PLL. →
− →
−
frame d-q ( V dq ); then the phase-angle of V dq is tracked in
the feedback loop (Fig. 1). Different alternatives to track the
B. Role of PLL in FACTS control dq-frame rotating phase-angle have been implemented. In [5]
The effect of PLL in different control schemes has been an- to track the fundamental phase is achieved making zero the
alyzed in different works. In this subsection a brief discussion quadrature component using a proportional integrator (PI) or
about them is presented. a lag/lead filter in the feedback loop. However, in [6] and [7]
In [3] the authors have studied the effect of the PLL delay the used method makes zero the direct component. Actually
on the performance of static synchronous series compensator both methods are similar; the feedback loop makes constant a
(SSSC) and static synchronous compensator (STATCOM). voltage reference in the dq rotating reference frame.

1-4244-0136-4/06/$20.00 '2006 IEEE 2390

 2

Voltage sag from 1 p.u. to 0.5 p.u. and phase-angle jump of -45 deg.
Vphase qerr w ,

qo.
Phase Detector
A

1
PI 1/s
A

0.8
Loop filter DCO
qo.
A

0.6

0.4

Amplitude (p.u.)
Fig. 2. One-phase SPLL equivalent scheme of classical PLL. 0.2

Three-phase PLLs only need a feedback loop for tracking -0.2

the whole phase. Furthermore, they have a good transient -0.4

response and internal harmonic cancellation. However, its -0.6

behaviour is bad with lower ac voltages and under unbalanced -0.8

conditions [2]. Indeed, the main issue of trans-vector-based
-1
PLLs is that they can not track individual phase-angle jumps,
→
− 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14
because V dq does not have enough information to deter- Time (ms)

mine them. Recently, some works have improved these issues

evolving the trans-vector-type PLL to a double synchronous Fig. 3. Voltage sag from 1 p.u. to 0.5 p.u. with a +45 deg. phase-angle jump.
reference frame (DRSF) which employs two feedback loop;
one for the positive sequence and other for the negative
sequence [8]. noise. The speed of response of PLLs to these disturbances
An alternative to three-phase PLLs is the use of three single- determines their performance.
phase PLLs which track the phase-angle of the input ac signals Voltage sags are a frequent phenomenon in electrical dis-
independently. Furthermore, single-phase PLL should be more tribution. They are characterized by a sudden drop in voltage
effective in system like the series voltage restorer (SVR) of amplitude for several cycles. They are mainly due to faults
[9] where a independent compensation is made for each phase. in the distribution system. Trans-vector-type PLLs have a
Single-phase PLL classical scheme, widely explained in [10], poor speed of response to sags, because the gain on the
has been implemented in hardware since 70s. Classical PLL feedback loop is proportional to the input voltage amplitude;
can be easy implemented in software (SPLL) replacing the therefore inserting a gain compensator improves the speed
classical blocks with their equivalent transfer function blocks of response of PLLs during sags. Voltage swells are short
(Fig. 2). duration overvoltages; like in voltage sags the PLL gain should
The main limitation in hardware classical PLLs is the be compensated.
utilization of only a single feedback loop, thereby it is not Phase-angle jumps are suddenly changes in the phase of
possible to choice the filter coefficients for improving all the the signal. During three-phase faults, phase-angle jumps occur
type of transient responses at the same time. This difficulty mainly due to difference in reactance to resistance ratio
must be solved with an intermediate solution, in which the between source and feeder. These phase-angle jumps usually
PLL has an acceptable performing in all cases but without a have values of few degrees. Voltage sags and large phase-
high speed. Other important limitation on classical hardware angle jumps can also appear at the same time, due to one-
PLLs is the internal second harmonic generation which de- phase faults in three-phase system [11]. In Fig. 3 is shown an
teriorates the output phase a lot. Using high order filter to example of phase voltage sag with a phase-angle jump due to
avoid this limitations has not been a useful solution due to the a unbalanced fault. In 0.26 ms. the voltage amplitude drops
introduced delay. to 0.5 p.u. and then the phase-angle leads 45 deg. After a few
Recently, with the advance of technology of microcon- cycles, the voltage sags ends, and then phase-angle delays 45
trollers, DSPs, FPGAs, etc, the performance of hardware deg to pre-fault value (dashed). The PLL speed of response
classical PLLs can easily improve using SPLLs. A high to this type of disturbance is very critical in DVR and SVR
improvement in system transient response can be achieved by protecting sensible loads.
controlling in different loops frequency, phase angle and volt- Slight frequency changes around natural frequency (50 Hz.
age magnitude [2]. The addition of control loops to the system or 60 Hz.) can occur; they are due to distribution line unbal-
gives the designer more degree of freedom to improve system ances and faults. PLLs should detect these frequency variations
responses. Moreover, the software implementation allows to and they should work without getting worse their performance.
use adaptive techniques for enhancing the whole performance Another typical and growing up disturbance is the harmonic
of the SPLL. The SPLL developed in this work take these contamination; it is mainly due to switching loads, which gen-
advantages for its implementation. erate harmonic components. These harmonics reach the whole
electrical distribution system, through the common coupling
II. P OWER QUALITY DISTURBANCES AND PLL S points, and they have a bad influence over a lot of systems.
Voltage and current deviations from their ideal shape are Moreover, the electrical distribution system is contaminated
known as power quality disturbances [11]. The critical distur- with electrical noise too. PLLs should be immune to harmonics
bances in FACTS applications are voltage sags, voltage swells, and noise. In fact, the used PLLs feedback filters, like PI, lag-
phase-angle jumps, frequency changes, harmonics and electric lead, etc, are low pass filters, which should attenuate harmonic

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 3

Vphase Amplitude Phase

Amplitude
gets better the SPLL performance. Nevertheless, the dynamic
Phase Frequency
loop Vphase normalized loop of this SPLL has a complex study; moreover the discrete im-
Voutput normalized
plementation of its adaptive techniques would demand several
linearizations whose effect is not easy to evaluate. Therefore,
Fig. 4. Proposed SPLL architecture. using this SPLL in a higher level control system seems
very difficult; the three-loop SPLL has the advantage to face
with amplitude, frequency and phase tracks independently, but
components and noise of the input signal. enhances more the whole complexity.
Finally, from the point of view of three-phase systems, To reduce the three-loop complexity, maintaining the SPLL
unbalances between phases are power disturbances too. There performance, can be achieved taking into account the mag-
is a system unbalance when there are signals with distinct nitude change of the disturbances. While distribution system
amplitudes, or phase to phase angles different from 120 deg., faults can produce great voltage amplitude depressions and
or both. As it has been shown in the previous section three- great phase-angle jumps [11], the mean value of the frequency
phase PLLs based on trans-vector-type are not useful enough rarely oscillates more than 1 Hz around the natural frequency.
under unbalanced situations. Therefore other solutions like Therefore, it is correct to consider much smaller frequency
DRSF or single-phase PLLs must be used for having an changes than phase-angle or voltage changes. Assuming this
accurate and independent phase-angle track during unbalances. approximation, a double-loop PLL can be developed with sim-
ilar, or better, real performance. Moreover, adaptive techniques
III. D ESIGN OBJECTIVES AND SPLL QUALITY used in [2] and in the Matlab Power System Blockset (PSB)
MEASUREMENT
[12] can be applied using the quasi constant frequency approx-
imation; so they are more useful for a discrete implementation.
Ideally, the SPLL must have a quick speed of response to
grid disturbances; being especially critical sags, phase-angle
jumps and sags with phase jumps in systems protecting sensi- B. Amplitude-loop
tive loads. Moreover the system must be easily implemented The PLL first block is the amplitude-loop. Its input signal
in a microcontroller, DSP or FPGA as a part of a high level →
− →
−
is V phase in p.u. and its outputs are the amplitude of V phase
control system. and the normalized signal which is the input of the phase-
The SPLL quality measurement can checked in different loop. The amplitude of normalized signal must be 1 p.u. so the
ways. The main magnitude to measure the SPLL performance gain of the phase-loop maintains itself constant for any input
is the phase-angle error. In steady state, when the system is amplitude. As it is shown in Fig. 5 and in Fig. 4 the output
tracked, the phase-angle error must be zero. However, when normalized signal is used in the amplitude-loop to obtain the
a disturbance occurs a phase-angle error appears; then the amplitude error signal Ec ; the input signal and the output
feedback loop must compensate it. The speed of response to normalized signal are squared, so when the phase are tracked
a disturbance can be measured as the time since it occurs Ec can be calculated using (1).
to the time when the steady state error becomes zero (or
quasi zero). Nevertheless, the speed of response to all different
disturbances is not an absolute measurement of the SPLL
2
Ec = (V̂phase − 1) sin2 (ωt + Φ)
performance; other parameters like recovery overshoots and 1 sin(2(ωt + Φ)) (1)
2
= (V̂phase − 1)( + )
average quadratic phase-error during the faults should be taken 2 2
into account. Moreover, depending on the application and on Ec pass through the loop filter giving the filtered signal
the higher level control the ripple in the outputs, amplitude Ecf which has very attenuated the second harmonic. Then
error, frequency error and noise immunity may be more or the dc component of Ecf is used to correct the amplitude
less important features of the SPLL. around the nominal amplitude (1 p.u.) being the correct factor
Fc = 1 + Ecf . The low pass filter Kpv improves the response
IV. A MPLITUDE - PHASE DOUBLE FEEDBACK LOOP SPLL of a simple PI because it attenuates more the second harmonic
The proposed PLL in this paper is shown in 4; it has component√ of Ec and therefore it reduces the ripple in Fc . The
two independent feedback loops whose features are shown inverse of Fc gets the V̂phase measure and the √ normalized
below. But, before analyzing these feedback loops, it should be signal is obtained multiplying the input signal by Fc .
explained the quasi constant frequency approximation which
has been employed thinking of a discrete implementation. C. Phase-loop
After the amplitude-loop, the phase-loop (Fig. 6) is placed.
A. Quasi constant frequency approximation The input of the phase-loop is the normalized signal. The
As it has been explained before, multiple-loop techniques phase loop outputs are the phase, the frequency and the
achieve more degrees of freedom to designers. The best normalized output signal. Actually, the phase-loop works like a
example of this is the adaptive SPLL proposed in [2] which classical PLL using as input a normalized signal which makes
has a great performance for several type of disturbances. This its gain constant. Like in classical PLLs a PI filter with a
work also shows that the utilization of adaptive techniques integrator is used for phase tracking. The integrator block

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 4

Fig. 7. Elimination of the second harmonic by subtraction.

Fig. 5. SPLL amplitude-loop.

Fig. 8. Frequency averager block for a constant frequency (50 Hz).

the multiplier. Due to its simplicity and effectiveness this

method has been employed in the phase detector of the phase-
amplitude-loop (Fig. 6).
The used phase detector is shown in Fig. 7.This system
efficiently eliminates all the second harmonics when the SPLL
is locked, but when it is unlocked, the amplitude of the second
harmonic is multiplied by a factor dependent of instantaneous
tracking error in the system. Such method will be only
advantageous when the SPLL is locked or his tracking error is
Fig. 6. SPLL phase-loop.
little (over less than 5 deg.). This penalizes a little the speed of
response to phase-angle jumps, but the global influence over
the dynamics improves a lot the PLL performance.
together with the natural frequency block form the digitally
2) Frequency averager: After the phase detector the fre-
controlled oscillator (DCO).
quency averager (FA) block is put (Fig. 8). This block is an
But, with respect to the classical PLL loops, this phase-
approximation of the PSB/FVA (Frequency variable averager)
loop contains blocks which implement adaptive techniques to
for a fixed frequency value which is the natural frequency
improve the system performance. These blocks are explained
(50 Hz). Its finality is to eliminate the harmonic components
as follows.
of the input signal. The input of FA is multiplied by the
1) Cancellation of second harmonic in phase detector:
frequency and integrated. The transport delay block delays
Classical PLL uses a multiplier as phase detector. The phase-
its input signal exactly one cycle (20 ms.). Then from the
error is obtained from the feedback loop multiplying the input
output of the integrator, the same signal delayed one cycle is
signal by the output signal led 90 deg. (cos(θo ) ). Then the
subtracted. The transfer function of FA is shown in (3); its
output of the multiplier has two terms. A term which only
main feature in Fig. 6 is its gain which drops abruptly to zero
depends on the signal error, and a second harmonic term (2).
in all the harmonics of “F req”.

sin(ωt + θi ) × cos(ωt + θo ) = F req −s

1 1 (2) H(s) = (1 − e F req ) (3)

= sin(θi − θo ) + sin(2ωt + θi + θo ) s
2 2 The discrete implementation of the FA block consumes
When the system is tracked the first term of (2) can be memory recurses because the SPLL needs to hold the points of
linearized as sin(θi − θo ) ≈ θi − θo . This term has all the its input during a cycle. This can be easily seen in the discrete
information of the phase error. However, the second term of transfer function (4).
(2), which has not information, has a big amplitude. Ideally,
this second harmonic component is eliminated in the loop F req · Ts 1

filter. However the gain of the loop filter for 2ω is not small H(z) = (1 − z − F req·Ts ) (4)
z−1
enough to cancel the influence of the second harmonic in the
This block can be optionally used in amplitude-loop for
dynamics. This influence is clearly visible in analog PLLs
avoiding the ripple in the amplitude measure (Fig.5).
where the phase measure has a ripple over the ideal ramp.
The phase detector can help to mitigate the second harmonic
generation. The first try of removing the problem has been ap- D. Coefficients choice and performance
plied in [2] moving the second harmonic to a higher frequency The rigorous study of the SPLL dynamics is quite complex,
which is much more attenuated in the low-pass filters.A less because it contains a lot of nonlinearities; however, the use
complex, but effective method, has been developed in the of software tools can help the designer in the stability and
PSB/SPLL [12]. The second harmonic is estimated from the performance analysis. The “Simulink response optimization
output phase. Then it is directly subtracted in the output of tool” (SRO) has been employed in this work [13]. The

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 5

50

40
1

30

20
0.5
Phase-error (deg.)

Amplitude (p.u.)
10

0
0
-10

-20

-0.5
-30

Vspll
-40

-1 Vphase
-50
0 0.05 0.1 0.15 0.2 0.25 0.3
Time (sec)
0.1 0.15 0.2 0.25 0.3 0.35
Time (s)
Fig. 9. Fitting the phase-angle error during a 0.5 p.u. sag with a +45 deg.
phase-angle jump using the SRO tool.
Fig. 10. SPLL response to a 0.5 p.u. sag with a +45 deg. phase-angle jump.

1.1

SRO tool inputs are the desired SPLL responses (boundary

conditions) for an input signal (disturbance), and the outputs 1
Vspll
are all the coefficient combinations and their response that can
fit to the input boundary conditions (Fig. 9). 0.9 Vphase
Amplitude (p.u.)

In this work, the final coefficients choice has been made

evaluating the SPLL quality parameters for different distur- 0.8

bances, especially the most critical. After this, the stability of

SPLL must be checked in all the possible worst-cases. The 0.7

final election of the coefficients is shown in table I.

0.6
TABLE I
SPLL GAINS 0.5

Amp-loop Ki Amp-loop Kp Phase-loop Ki Phase-loop Kp

0.4
965.5 1.12 148.9 169.3 0.1 0.15 0.2 0.25 0.3 0.35
Time (s)

Fig. 11. SPLL amplitude during the 0.5 p.u. sag with +45 deg. phase jump.
V. S IMULATION RESULTS
Simulations results have been obtained using Mat-
lab/Simulink. These results analyze the main SPLL features used to determine the time used by the SPLL for tracking
during a voltage sag with phase-angle jump of +45 deg, similar after a disturbance; determining when the system is tracked
to Fig. 3. The main reason of electing this disturbance is its depends on a designer criterion. For example, for a phase-
significance over the SPLL whole performance, because it has jump of 45 deg. the designer may establish that the system is
an amplitude depression and a big phase-angle jump. tracked when the phase-error is less than 2.5 deg. However,
→
− this is not an absolute measurement, because a system with
In Fig. 10 it is shown V phase with the disturbance (dashed)
→
− →
− high overshoot can achieve quickly a phase-error smaller than
and the SPLL response V spll (solid); V spll is obtained
multiplying the output amplitude by the normalized output the threshold value, but due to oscillation the system cannot
signal. It can be seen that in approximately a cycle the SPLL be considered tracked.
output is adapted to fault voltage and it spends the same time Comparing these results with the results of adaptive SPLL
to return to pre-fault situation. shown in [2], it can be seen that both systems have similar
The SPLL amplitude measured during the disturbance is performance under amplitude sags and phase-angle jumps.
shown in Fig. 11. It can be seen that the overshoot is greater
→
− VI. R EAL -T IME IMPLEMENTATION RESULTS
when V phase returns to pre-fault situation. It is important to
say that the adaption time depends on the deep of the sag, To analyze the feasibility of the SPLL in a real system it has
being especially critical for very low amplitude sags. Tuning been implemented using the fast prototyping platform dSpace
the SPLL for a faster response to deep sags, involves a high DS1103 which contains a microprocessor, a DSP and an I/O
gain in the amplitude-loop which generates large overshoot in interface. A programmable AC power source has been used
the outputs during the transients. to generate the disturbances. The inputs and outputs of the
In Fig. 12 it is shown the SPLL response for the disturbance prototype have been captured in a digital oscilloscope.
phase-angle steps. The difference between SPLL phase and In Fig. 13 they are shown the input signal from the ac
the real phase gives the phase-error. The phase-error is widely source, the SPLL output signal and the normalized measured

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 6

60

50

40 Vphase
Phase-angle (deg.)

VSPLL
30

20

10

-10
0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (s)

Fig. 12. SPLL phase-angle response to a 0.5 p.u. sag with a +45 deg.
phase-angle jump.

Fig. 14. Real-Time implemented SPLL response to a 0.5 sag with phase-angle
Vphase jump of +45 deg. (Vphase dashed, Vspll solid).

implementation very feasible for its use in programmable

devices like microcontrollers, DSPs or FPGAs, and into a
higher level control system.

ACKNOWLEDGEMENT
Vspll Phase
This work was supported by the Spanish Ministry of Science
and Technology under project number DPI2003-01513.

R EFERENCES
[1] N. G. Hingorani and L. Gyugyi., Understanding FACTS, R. J. Herrick.,
Ed. IEEE Press., 2000.
[2] D. Jovcic, “Phase locked loop system for FACTS,” IEEE Transactions
on Power Systems, vol. 18, no. 3, pp. 1116–1124, August 2003.
[3] A. H. Norouzi and A. M. Sharaf., “Two control schemes to enhance the
dynamic performance of the statcom and sssc,” IEEE Transactions on
power delivery., vol. 20, pp. 435–442, 2005.
Fig. 13. Input Vphase , output Vspll and SPLL measured phase-angle.
[4] J. G. Nielsen, F. Blaabjerg, and N. Mohan, “Control strategies for
dynamic voltage restorer compensating voltage sags with phase jump,”
Proceed. of APEC2001, vol. 2, 2001, pp. 1268-1273., vol. 2, pp. 1268–
phase-angle during a typical steady-state situation. It can be 1273, 2001.
[5] C. Zhang, C. Fitzer, V. K. Ramachandraramurthy, A. Arulampalam,
seen that the output signal is closely equal to reference. M. Barnes, and N. Jenkins, “Software phase-locked loop applied to
Moreover, the phase-angle ramp is straight and it has not dynamic voltage restores (DVR),” Proc. IEEE Power Eng. Soc. Winter
second harmonic, because it has been removed previously in Meeting. Conf., vol. 3, pp. 1033–1038, 2001.
[6] V. Kaura and V. Blasko., “Operation of a phase locked loop system
phase-detector. under distorted utility conditions.” IEEE IEEE Transactions on industry
In Fig. 14. the real-time response of the SPLL for the applications., vol. 33, pp. 58–63, 1997.
disturbance analyzed in simulation is shown. The input of [7] H. Awad, J. Svensson, and M. Bollen., “Phase-locked loop for static
series compensator.” in EPE, 2003.
SPLL with the disturbance and the synchronized oscilloscope [8] P. Rodriguez, J. Pou, J. Bergas, I. Candela, R. Burgos, and D. Boroyevic,
trigger signal have been generated in the AC power source. It “Double synchronous reference frame pll for power converters control,”
can be seen that the implementation results are very similar in Conference on Power Electronics Specialists, 2005.
[9] ABB, “Series voltage restorer-data sheet.” 2004, 3BHT 490 484 R001.
to the simulation results, which confirms the feasibility of a [10] R. E. Best, Phase Locked Loops. Design, Simulation and Applications.
discrete implementation of the model. 4th Edition. McGraw-Hill, 1999.
[11] M. H. J. Bollen., Understanding power quality problems. Voltage sags
and interrupions., R. J. Herrick., Ed. IEEE Press Editorial Board.,
VII. C ONCLUSIONS 2000.
[12] Mathwoks, Power System BlockSet, User Manual., 2000.
A SPLL for FACTS control has been proposed, and its [13] Mathworks., Simulink Response Optimization For Use with Simulink.
features have been shown with simulation and real-time im- User’s guide., 3rd ed., March. 2006.
plementation. Moreover, the used algorithms make the discrete

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