ELEC 3040/3050

Lab #7

PWM Waveform Generation

References: STM32L1xx Technical Reference Manual

STM32L100RC Data Sheet
Goals of this lab exercise

 Begin applying system design concepts to

primary semester design project
 Speed controller for a dc motor
 Generate a pulse-width-modulated (PWM)
waveform with keypad-selectable duty cycle
 Using a programmable timer

The generated waveform will be amplified in the next lab to

drive a dc motor

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Motor Speed Control Project
1. Generate a PWM waveform
2. Amplify the waveform to drive the motor
3. Measure motor speed
4. Measure motor parameters
5. Control speed with a PID or other controller

12v DC
Tachometer
Motor
Frequency/
9v
Amplitude
Power Amplifier
Measurement
Supply
Computer
System

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PWM Digital Waveforms

 A pulse-width modulated (PWM) signal is a

periodic signal comprising pulses of varying
duration
 Modulation refers to modifying the pulse width
(with period held constant) to achieve a desired
effect
 “Effect” often an average voltage to control a device
 PWM signals are often used to drive motors,
commercial lights, etc.

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 PWM to Drive a Servo Motor

 Servo PWM signal

 20 ms period
 1 ms pulse width
 Vavg ≈ Vmax/10

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PWM Waveform Parameters
T = period of waveform (constant)
T1 = duration of pulse (T2 = T – T1)
Duty Cycle = T1/T = T1/(T1+T2)

Vavg = Vmax x Duty Cycle

Vavg = 0.5Vmax
Pulses can
also be
Vavg = 0.25Vmax active-low.

Vavg = 0.75Vmax

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 Timer operating modes
Timer capture/compare channels provide operating modes other than periodic
interrupts
 Output compare mode – Create a signal waveform/pulse/etc.
 Connect timer output TIMx_CHy to a GPIO pin
 Compare CNT to value in Capture/Compare Register CCRy
 Change output pin when CNT = CCRy
 Pulse-Width Modulated (PWM) waveform generation mode
 Similar to output compare mode
 Force output pin active while CNT < CCRy
 Force output pin inactive while CCRy ≤ CNT ≤ ARR
 ARR sets PWM period, CCRy determines PWM duty cycle
 One pulse mode – Create a single pulse on a pin
 Similar to output compare mode
 Disable counter when the event occurs
 Input capture mode – Capture time at which an external event occurs
 Connect a GPIO pin to timer input TIMx_CHy
 Capture CNT value in Capture/Compare Register CCRy at time of an event on the pin
 Use to measure time between events, tachometer signal periods, etc

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 General-purpose timers TIM10/TIM11
* 2.097MHz if default MSI clock used
(0x0020_0000 cycles/sec)
* 16 MHz if HSI clock used
Basic timing function
(earlier lab)

Capture/Compare Channel 1 – TIMx_CH1 input/output

2 channels in TIM9, 4 channels in TIM2-3-4, no channels in TIM6-7

TIM6-7-10-11 have up counters, TIM2-3-4-9 have up/down counters

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 Timer capture/compare channels
ARR
Input capture:
Output compare:
Copy CNT to CCRx
Trigger an event
when input event
when CNT = CCRx
detected

CCRx

One-pulse

Pulse-width
modulation OCxREF active
inactive
CNT < CCRx CNT >= CCRx

Period CNT=CCRx=3 CNT=ARR=7

Start (toggle OCxREF) (reset CNT and OCxREF)

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Capture/Compare Output Stage

ARR
Comparator
Output**
CNT Outputs

=
Output polarity
CCR1

Enable output
Output Compare or PWM mode

** Route output OC1 to a GPIO pin as an “alternate function”.

(each GPIO pin can connect to one or two timer channels)

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Timer outputs as GPIO pin alternate functions
Each GPIO pin configurable as: INPUT, OUTPUT, ANALOG, ALTERNATE FUNCTION
- Select pin modes in GPIOx->MODER (10 = alternate function)

From STM32L100RX Data Sheet Table 7. “Pin Definitions” (partial)

1. Select AF mode for pin in MODER

2. Select AFn in GPIOx->AFRL/AFRH

We will use
TIM10_CH1
(Pin PA6)

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 Selecting an alternate function
GPIOn->MODER selects AF mode for pins (10)
Timers
GPIOn->AFR[0] selects AFs for pins Pn7-Pn0
GPIOn->AFR[1] selects AFs for pins Pn15-Pn8
Only a subset of AF’s available at each pin,
as listed in data sheet. (see previous slide)

Example: Configure PA6 as TIM3_CH1 (AF2)

GPIOA->MODER &= ~0x00003000; //clear PA6 mode
GPIOA->MODER |= 0x00002000; //PA6 = AF mode
GPIOA->AFR[0] &= ~0x0F000000; //clear AFRL6
GPIOA->AFR[0] |= 0x02000000; //PA6 = AF2

AFR[0]:
AFRLn
defines
pin n,
n=0..7

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Timer System Control Register 1
See timer overview
from earlier lab
TIMx_CR1 (reset value = all 0’s)
7 6 5 4 3 2 1 0

ARPE CMS* DIR* OPM URS UDIS CEN

Center mode select Direction Counter Enable*

00 = edge-aligned 0 = count up 0 = disable
-count in one direction 1 = count down 1 = enable
Others: center aligned
-count in both directions
One Pulse Mode
* TIM6-7-10-11 limited to count up: 1 = counter stops at update event
- DIR = 0 & CMS = 00 only 0 = counter continues at UE

*CEN only bit that needs to be changed for simple PWM

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 Timer Status Register
See timer overview
TIMx_SR (reset value = all 0’s) from earlier lab

7 6 5 4 3 2 1 0

CC4IF CC3IF CC2IF CC1IF UIF

TIM10 has only CC1IF

Update interrupt flag
1 = update interrupt pending
Capture/compare interrupt flags 0 = no update occurred
1 = capture/compare interrupt pending
0 = no capture/compare event occurred Set by hardware on update event
Cleared by software
Set by hardware on capture/comp event (reset UIF bit to 0)
Cleared by software
(reset CCxIF bit to 0)

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 Timer DMA/Interrupt Enable Register
See timer overview
from earlier lab
TIMx_DIER (reset value = all 0’s)
8 7 6 5 4 3 2 1 0

UDE CC4IE CC3IE CC2IE CC1IE UIE

Update DMA request enable

TIM10 has Update interrupt* enable
1 = enable, 0 = disable only CC1IE
1 = enable, 0 = disable

Capture/Compare interrupt* enable

TIMx interrupt on capture/compare event
1 = CCx interrupt enabled, 0 = disabled

* Capture/compare and update events generate the same IRQn signal, and use
the same interrupt handler. Handler reads status register flags to determine source.

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Capture/Compare Register (CCR)
 Compared to TIMx_CNT to trigger operations at specified times.
 TIMx_CCRy = TIMx capture/compare register, channel y
 TIM2-3-4: y=1,2,3,4; TIM9: y = 1,2; TIM10-11: y=1
 CCRy register width same as CNT/ARR registers (16 bits)
------------------------------------------------------------------------------------------
 Input capture mode: TIMx_CNT captured in TIMx_CCRy when a
designated input signal event is detected
 Output compare mode: TIMx_CCRy compared to TIMx_CNT; each
match is signaled on OCy output
 One pulse mode: same as output compare, but disable after match
 PWM mode: TIMx_CCRy compared to TIMx_CNT
 CNT < CCRy => output active
 CNT ≥ CCRy => output inactive

TIMx_CNT operates as discussed previously for periodic interrupt generation:

- Signal update event and reset to 0 when CNT = ARR while counting up
- Signal update event and reload ARR when CNT = 0 while counting down

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Capture/Compare Mode Registers
TIMx_CCMR1: bits 7:0 configure channel 1; bits 15:8/channel 2
TIMx_CCMR2 (TIM2-3-4): bits 7:0/channel 3; bits 15:8/channel 4
(reset values = all 0’s)

If Output Mode ->

If Input Mode** ->
** discuss later

Output Compare 1 Mode Capture/Compare 1 Select

000 = frozen (no events) 00 = output
001 = Set CH1 active* on match 01 = input**: IC1 = TI1
010 = Set CH1 inactive* on match 10 = input**: IC1 = TI2
011 = Toggle CH1 on match 11 = input**: IC1 = TRC
100 = Force CH1 to inactive* (immediate)
101 = Force CH1 to active* (immediate)
110 = PWM mode 1 (active* to inactive*)
111 = PWM mode 2 (inactive* to active*)

* Active/inactive levels selected in TIMx_CCER register

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Capture/Compare Enable Register
TIMx_CCER (reset value = all 0’s) Channel 1
15 - 12 11 – 8 7 - 4
CC4 CC3 CC2
bits bits bits

CC1 Polarity CC1 Enable

If CC1 = output, CC1P selects: If CC1 = output:
0 = OC1 active high 1 = OC1 drives output pin
1 = OC1 active low 0 = OC1 does not drive output

If CC1 = input: If CC1 = input:

CC1NP/CC1P select capture trigger: 1 = Capture enabled
00: falling edge of input 0 = Capture disabled
01: rising edge of input
11: both edges of input

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 Pulse-Width Modulation (PWM) Mode
(TIMx_CCRy)
Duty
Duty cycle =
(Duty/Period) x 100%
Output pin

Period
(TIMx_ARR)
 PWM by comparing TIMx_CNT to both TIMx_CCRy and TIMx_ARR
 TIMx_ARR => Period
 TIMx_CCRy => Duty
 TIMx_CCMRn (capture/compare mode) (n=1 for channels 1-2 / n=2 for channels 3-4):
 Bits CCyS = 00 to select an output mode for channel y
 Bits OCyM = 110 (PWM mode 1) – active if CNT < CCRy, inactive otherwise
OCyM = 111 (PWM Mode 2) - inactive if CNT < CCRy , active otherwise
 TIMx_CCER:
 Bit CCyE = 1 to enable OCy to drive the output pin
 Bit CCyP = 0/1 to select active level high/low (output polarity) of OCy
 Configure GPIO MODER and AF registers to select alt. function TIMx_CHy for the pin

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PWM Signal Examples
ARR=8

1 2 3

1 2 3

OCXREF
1 3
always active

2 3 OCXREF
always inactive

1. OCXREF active (high) when TIMx_CNT < TIMx_CCRx

Assumes OCxM = 110 and CCxP = 0
2. OCXREF inactive (low) when TIMx_CNT ≥ TIMx_CCRx
3. Update Event when TIMx_CNT = TIMx_ARR (resets TIMx_CNT to 0)

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Example:
20KHz PWM signal with 10% duty cycle on pin PB6
 Use TIM4, Channel 1
 Since TIM4_CH1 = AF2 for pin PB6
 Assume timer clock = 16MHz* and prescale = 1
 PWM Period = 16MHz/20KHz = 800 (TIM4_ARR = 799)
 PWM Duty = 800 x 10% = 80 = TIM4_CCR1 * What if timer clock
 Configure TIM4_CCMR1 bits: = 2.097 MHz ?
 CC1S = 00 (make channel 1 an output) (0x0020_0000 Hz)
 CC1M = 110 (PWM mode 1: active-to-inactive)
 Configure TIM4_CCER bits:
 CC1E = 1 to enable output OC1 to drive the pin
 CC1P = 0 to define OC1 as active high
 Configure PB6 as alternate function TIM4_CH1
 Select AF mode for PB6 in GPIOB->MODER
 Select TIM4_CH1 (AF2) for PB6 in GPIOB->AFRL

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 Lab Procedure
 Generate a PWM waveform with timer TIM10
 Period should be 1 ms (frequency 1 KHz)
 First, generate a waveform with one duty cycle value
 Then, verify that you can generate waveforms with each
of the 11 specified duty cycles, from 0% to 100%, as
selected by keypad keys 0 – A.
 Measure and record the 11 duty cycle values
 Plot measured duty cycle vs. selection key #

 Repeat with higher/lower PWM frequencies**

 100 Hz, 10 KHz, etc.
**Motor performance may
 What needs to be changed? vary with PWM frequency.

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