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Expanding Memory Size

The document discusses expanding memory capacity by using multiple memory chips. It describes two methods: (1) Expanding the word size by using two 16x4 RAM chips where one chip stores the higher order bits and the other stores the lower order bits; (2) Expanding the number of memory locations by connecting multiple chips together and using an address decoder to select the appropriate chip. Programmable Logic Devices (PLDs) are also introduced, which can be programmed by blowing fuses to implement logic functions using AND and OR gates in a sum-of-products configuration.

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Felistus Kavuu
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991 views

Expanding Memory Size

The document discusses expanding memory capacity by using multiple memory chips. It describes two methods: (1) Expanding the word size by using two 16x4 RAM chips where one chip stores the higher order bits and the other stores the lower order bits; (2) Expanding the number of memory locations by connecting multiple chips together and using an address decoder to select the appropriate chip. Programmable Logic Devices (PLDs) are also introduced, which can be programmed by blowing fuses to implement logic functions using AND and OR gates in a sum-of-products configuration.

Uploaded by

Felistus Kavuu
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Expanding Memory Capacity

When a given application requires a RAM or ROM with a capacity that is larger than what is
available on a single chip, more than one such chip can be used to achieve the objective. The
required enhancement in capacity could be either in terms of increasing the word size or
increasing the number of memory locations.

(i) Word Size Expansion

Let us take up the task of expanding the word size of an available 16×4 RAM chip from four bits
to eight bits. Figure 7.19 shows a diagram where two such RAM chips have been used to achieve
the desired effect. The arrangement is straightforward. Both chips are selected or deselected
together. Also, the input that determines whether it is a ‘read’ or ‘write’ operation is common to
both chips. That is, both chips are selected for ‘read’ or ‘write’ operation together. The address
inputs to the two chips are also common. The memory locations corresponding to
various address inputs store four higher-order bits in the case of RAM-1 and four lower-
order bits in the case of RAM-2. In essence, each of the RAM chips stores half of the
Procedure
If it is required to have a memory of word size n and the word size of the available memory
ICs is N (n >N), then a number of similar ICs can be combined together to achieve the desired
word size.
The number of IC chips required is an integer next higher to the value n/N. These chips are
then connected in the following format;
(i) Connect the corresponding address lines of each chip individually, i.e. A0 of each chip is
connected together becoming A0 of the overall memory. Similarly, connect all the other
address lines together.
(ii) Connect the RD input of all the ICs together becoming the read input of the overall memory.
Similarly connect the WR and CS inputs.
(iii) The number of data input/output lines will be equal to the product of the number of chips
used and the word size of each chip.
EX: Obtain a 16 X 8 memory using a 16 X 4 memory ICs.
Since each chip can store 16, 4 – bit words, and we want to store 16, 8 – bit words, then each chip
is required to store half of each word. The figure 7.19 shows the relevant connections of the two
chips. It is assumed that the input/outputs (I/O) lines are bidirectional which is common in many
available memory chips.

In this case, the 16X8 memory, the higher order four bits (D 7, D 6, D 5, D 4) of each 8 – bit word are
located in memory M1 and the lower order four bits (D3, D 2, D 1 & D0) are in memory chip M0
(ii)Expanding Word Capacity
Memory chips can be combined to produce a memory with a desired number of locations. To
obtain a memory of capacity m words using the memory chips with M words each, the number
of chips required is an integer number next higher to the value m/M (m>M). These chips are
connected in the following format;
(i) Connect the corresponding address lines of each chip.
(ii) Connect the RD input of each chip together. Similarly, connect the WR inputs together.
(iii) Use a decoder of proper size and connect each of its outputs to one of the CS terminals of
memory chips e.g. if eight chips are required to select on of the eight chips at any one time.
EX: Obtain a 2048 X 8 memory using 256 X 8 chips.
Soln: The number of chips required is 2048/256 = 8. At any given time, only one of the 2048
locations is to be accessed which will be in one of the eight chips. This means only one of the
eight chips must be selected at a time.
For selecting one out of 2048 locations, the number of address lines required is 11 (i.e. 2 11= 2048).
Programmable Logic Devices (PLDs)
A PLD is an integrated circuit (IC) with internal logic gates that are connected through electronic
fuses. Programming the device involves blowing of the fuses along the paths that must be
disconnected so as to obtain a particular function. Like a ROM, once a PLD has been
programmed for a particular purpose, it cannot be erased and reprogrammed. An example of a
PLD is a Programmable Logic Array (PLA).

A PLA is a logic circuit made up of AND and OR gates which can be interconnected to generate
one or more outputs that are sum of product functions of several inputs.

By selectively blowing the fusible links that interconnect the logic inputs to the AND gates, and
the And gates to the OR gates, any desired sum-of-products output function can be generated. In
block diagram form, a PLA looks as shown on Figure 8.1.
Figure 8.3 below is showing an example of a 3-input, 2-output PLA.
Example: Use the PLA shown on Figure 8.3 to implement the truth-table shown below:
A shorthand way of drawing Figure 8.4 is shown in Figure 8.5.
In the implementation of large combinational logic circuits, PLDs are preferred to SSI or
MSI devices for the following reasons:

∙ PLDs use less circuit board area since one PLD package is equivalent to several packages
of SSI/MSI devices.

∙ PLDs shorten design time since fewer packages are used.

∙ Design changes can be done by reprogramming new PLDs, which is less time consuming
than redesigning a circuit board made up of SSI/MSI devices.

∙ Since PLD-based circuits use fewer ICs, there are fewer interconnections to be made and
this makes PLD-based circuits more reliable than SSI/MSI circuits.

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