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Cos103 CPU-and InstFormat

The document discusses the key components of a computer's central processing unit (CPU). The CPU contains three main components: the memory or storage unit, the control unit, and the arithmetic logic unit (ALU). The memory unit stores instructions and data. The control unit manages operations between the computer's parts but does not perform data processing. The ALU performs arithmetic and logical operations on data.

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Kamsy Afam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
85 views

Cos103 CPU-and InstFormat

The document discusses the key components of a computer's central processing unit (CPU). The CPU contains three main components: the memory or storage unit, the control unit, and the arithmetic logic unit (ALU). The memory unit stores instructions and data. The control unit manages operations between the computer's parts but does not perform data processing. The ALU performs arithmetic and logical operations on data.

Uploaded by

Kamsy Afam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Comput

er–CPU(
Cent
ralPr
ocessi
ngUni
t)
Thef
eat
uresoft
heCent
ralPr
ocessi
ngUni
t(CPU)ar
e:
 CPUi
sconsi
der
edast
hebr
ainoft
hecomput
er.
 I
tper
for
msal
ldat
apr
ocessi
ngoper
ati
ons.
 I
tst
oresdat
a,i
nter
medi
ater
esul
ts,
andi
nst
ruct
ions(
progr
am)
.
 I
tcont
rol
stheoper
ati
onofal
lpar
tsoft
hecomput
er.
TheCPUhasf
oll
owi
ngt
hreecomponent
s.
1.Memor
yorSt
orageUni
t
2.Cont
rol
Uni
t
3.ALU(
Ari
thmet
icLogi
cUni
t)
TheMemor
yorSt
orageUni
t
Thi
sunitcanst
orei
nstruct
ions,
data,
andintermedi
ateresult
s.Itsuppl
iesi
nfor
mati
ont
oot
her
uni
tsofthecomput
erwhenneeded.Itisknownasinter
nal st
orageunitor(
themai
nmemor
yorthe
pri
marystor
ageorRandom AccessMemor y(RAM)).
I
tssi
zeaff
ect
sspeed,
power
,andcapabi
l
ity
.Pr
imar
ymemor
yandsecondar
ymemor
yar
etwo
t
ypesofmemori
esint
hecomputer
.
Funct
ionsoft
hememor
yuni
tar
eto:
 St
oreal
lthedat
aandt
hei
nst
ruct
ionsr
equi
redf
orpr
ocessi
ng.
 St
orei
nter
medi
ater
esul
tsofpr
ocessi
ng.
 St
oref
inal
resul
tsofpr
ocessi
ngbef
oret
her
esul
tsar
erel
easedt
oanout
putdev
ice.
 Tr
ansmi
tthr
ought
hemai
nmemor
yal
li
nput
sandout
put
s
TheCont
rolUni
t
Thi
sunitmanagestheoperat
ionsofal
lpar
tsoft
hecomput
erbutdoesnotcar
ryoutanyact
ual
dat
aprocessi
ngoperat
ions.
Funct
ionsoft
hisuni
tar
e:
 Cont
rol
thet
ransf
erofdat
aandi
nst
ruct
ionsamongot
heruni
tsofacomput
er
 Managesandcoor
dinat
esal
ltheuni
tsoft
hecomput
er.
 Obtai
nsthei
nst
ruct
ionsf
rom t
hememor
y,i
nter
pret
sthem,
anddi
rect
stheoper
ati
onoft
he
computer
 Communi
cat
eswi
thI
nput
/Out
putdev
icesf
ort
ransf
erofdat
aorr
esul
tsf
rom st
orage
TheALU(
Ari
thmet
icLogi
cUni
t)
Thi
suni
tconsi
stsoft
wosubsect
ionsnamel
y:
 Ari
thmeticSect
ion
 LogicSecti
on
Ar
it
hmeti
cSection
 Perfor
m operat
ionsl
i
keaddi
ti
on,
subt
ract
ion,
mul
ti
pli
cat
ion,
anddi
vi
sion.
 Al
lcompl
exoper
ati
onsar
edonebymaki
ngr
epet
it
iveuseoft
heabov
eoper
ati
ons.
Logi
cSect
ion
Per
for
m oper
ati
onssuchascompar
ing,
sel
ect
ing,
mat
chi
ng,
andmer
gingofdat
a.
Comput
erOr
gani
zat
ionandAr
chi
tect
ure
Comput erArchit
ecturer ef
er stot hoseat t
r i
butesofasy stem thathav eadi recti
mpactont he
l
ogicalexecuti
onofapr ogram.Exampl es:
 theinstructi
onset
 thenumberofbi t
susedt or epresentv ariousdat atypesofI /Omechani sms
 memor yaddr essingt echniques
Comput erOrganizati
onr eferstot heoper ational unit
sandt heirint
erconnect i
onsthatreali
zethe
archit
ectur
alspecifi
cations.Exampl esar ethingst hataretranspar enttothepr ogr
ammer :
 cont r
olsignals
 interf
acesbet weencomput erandper i
pheralsot hememor ytechnologybeingused
Forexampl e,t
heav ail
abili
tyofamul t
iplyinstructi
oni sarchitectureissue.Howt hatmul t
ipl
yis
i
mpl ementedisor gani
zat i
oni ssue.

•Ar
chit
ecturei
st hoseatt
ribut esv i
sibletotheprogrammer
 Instr
uct i
onset,numberofbi tsusedfordatarepresent
ati
on,
I/Omechanisms,addr
essi
ng
t
echniques.
 e.g.Isthereamul t
iplyinstructi
on?
•Or
ganizati
onishowt hef eaturesar eimplement ed
 Control si
gnal
s,inter f
aces, memor ytechnology
.
 Forinstance:I
st her ehardwar emul ti
plyuni
torisitdonebyrepeat
edaddit
ion?
•Al
lInt
elx86fami l
ysharet hesamebasi carchi
tectur
e
•TheI
BM Sy
stem/
370f
ami
l
yshar
est
hesamebasi
car
chi
tect
ure
•Thi
senabl
escodecompat i
bil
i
ty
 Atleastbackwards
•Or
ganizat
ionmostoft
endiffer
sbetweendi
ff
erentv
ersi
ons.

ComputerStr
uct
ureandFuncti
on
•St
ruct
urei
sthewayinwhichcomponent
srel
atet
oeachot
her
•Funct
ioni
stheoper
ati
onofi
ndi
vi
dual
component
saspar
toft
hest
ruct
ure
•Al
lcomputerf
uncti
onsare:
 Dataprocessi
ng:Computermustbeablet
opr
ocessdat
awhi
chmayt
akeawi
dev
ari
ety
offor
msandt herangeofprocessi
ng.
 Dat
astor
age:Comput
erst
oresdat
aei
thert
empor
ari
l
yorpermanent
ly.
 Dat
amov ement
:Comput
ermustbeabl
etomovedatabet
weenit
sel
fandt
heout
side
wor
ld.
 Cont
rol
:Ther
emustbeacont
rol
oft
heabov
ethr
eef
unct
ions.

ComputerComponent s
 TheCont r
olUnit(
CU),Ari
thmeti
candLogi
cUni t(ALU)const
it
utetheCent r
alProcessi
ngUnit
(CPU)
 Input/output(
I/Omodule)enableDat
aandinstructi
onstogetint
ot hesystem andresul
tst
o
getout
 Themai nmemor y(RAM),enabl
etempor
arystorageofcodeandr esult
s.
Fi
g:Dat
amov
ementoper
ati
on Fi
g:St
orageOper
ati
on

Fi
g:Pr
ocessi
ngf
rom /t
ost
orage Fi
g:Pr
ocessi
ngf
rom st
oraget
oi/
o

Fourmai
nstructuralcomponents:
 Centralprocessi
ngunit(
CPU)
 Mainmemor y
 I/
O
 System inter
connect
ions

CPUst
ruct
uralcomponent sare:
 Cont rolunit
 Arithmet i
candl ogicuni
t(ALU)
 Regi sters
 CPUi nterconnect
ions

BusI
nter
connect
ion
•Abusisacommuni cati
onpathwayconnecti
ngtwoormor
edev
ices
•Usual
l
ybroadcast(
allcomponentsseesignal
)
•Oft
engrouped
 Anumberofchannel sinonebus
 e. g.32bi tdatabusi s32separ atesi nglebitchannel
s
•Powerl i
nesmaynotbeshown
•Thereareanumberofpossi bleinterconnect ionsy st
ems
•Singleandmul ti
pleBUSst ructuresar emostcommon
•e.g.Cont rol/
Addr ess/Dat abus( PC)
•e.g.Unibus( DEC- PDP)
•Lotsofdev icesononebusl eadst o:
oPr opagationdelay s
oLongdat apat hsmeant hatco- ordinationofbuscanadv er
sel
yaf
fectper
for
mance
oIfaggr egatedatat ransferappr oachesbuscapaci ty
•Mostsy stemsusemul tipl
ebusest oov ercomet heseproblems

Wether
ef orehav et hefoll
owi ngbuses:
DataBus
 Car ri
esdat a
Not ethatthereisnodi ff
erencebet ween“ dat
a”and“inst
ructi
on”att
hisl
evel
 Wi dthisakeydet ermi nantofper f
ormance; wehave:
8,16,32, 64bit
AddressBus
 I dent i
fythesour ceordest i
nat i
onofdat a
o e. g.CPUneedst oreadani nstruct
ion( data)f
rom agivenlocat
ioni
nmemor y
 Buswi dthdet er
minesmaxi mum memor ycapacityofsystem
e.g.8080has16bi taddr essbusgi v i
ng64kaddr essspace
ControlBus
 Per forms: Controlandt i
mingi nformation
 Memor yreadandMemor ywr i
te
 I /Or eadandI /Owr ite
 Tr ansf erACK
 Busr equestandBusgr ant
 I nterruptrequestandI nterr
uptACK
 Cl ock
 Reset

CPURegi
ster
s
 Incomputerar chitecture,apr ocessorregi
sterisav eryfastcomput ermemoryusedtospeed
theexecuti
onofcomput erprogramsbypr ovi
dingqui ckaccesst ocommonl yusedv
alues,
typi
cal
ly,
thev aluesbei ngi nthemi dstofacalculat
ionatagi venpointinti
me.
 Theseregistersar eatt het opoft hememor yhierarchy,andof f
ert hefast
estwayforthe
syst
em tomani pulatedat a.
 Inav er
ysi mpl emi croprocessor ,itconsi
stsofasi nglememor ylocati
on,usuall
ycal
l
edan
accumulator.
 Regist
ersarebui ltfrom fastmul ti
-port
edmemor ycell.
 Theymustbeabl et odr i
vei t
sdat aontoaninternalbusinasi ngl
eclockcycle.
 Ther esul tofALUoper at i
oni sst oredher eandcoul dber e-usedi nasubsequentoper at i
onor
savedi ntomemor y.
 Regi st ersar enor mal l
ymeasur edbyt henumberofbi tstheycanhol d,forexampl e,an“ 8-bi
t
regi
st er”ora“ 32- bitregi ster”.
 Regi st ers are now usual l
yi mpl ement ed as a r egisterf il
e,butt hey hav e al so been
i
mpl ement edusi ngi ndi vidualflip-f
lops, highspeedcor ememor y,thi
nfilm memor y,andot her
waysi nv ari
ousmachi nes.
 Thet er mi sof t
enusedt or eferonl yt ot hegr oupofr egistersthatcanbedi r
ectl
yi ndex edf or
i
nputorout putofani nst ruction, asdef i
nedbyt hei nst r
uctionset .
 Mor epr operl
y,thesear ecal ledt he“ archi t
ect edregi sters“
.
 Fori nstance, thex86i nst r
uct ionsetdef inesasetofei ght32-bitregist
ers,butaCPU
t
hatimpl ement st heX86i nst ruct i
onsetwi l
lcont ainmanymor ehar dwar er egisters
t
hanjustt heseei ght .
Thef ol
lowi ngar eot hercl assesofr egisters:
(a) Accumul ator:I tismostf r
equent l
yr egisterusedt ost oredat atakenf rom memor y.Its
numberv ari
esf rom mi cropr ocessort omi croprocessor .
(b) Gener alPurposer egi sters:areusedt ost oredat aandi ntermedi at
er esultsduringpr ogram
execut ion.Itscont entscanbeaccessedt hroughassembl yprogr amming.
(c) Speci alpurposeRegi st ers:usedbycomput ersy stem att hetimeofpr ogram execut ion( not
accessi bletoUser s).
Someot hert ypesofspeci al purposer egi stersar egiv enbel ow:
 Memor
yAddr
essRegi
ster(
MAR)
:-st
oresaddr
essofdat
aori
nst
ruct
ionst
obef
etchedf
rom
memor
y.
 Memor yBuff
erRegist
er(
MBR)
:-st
oresi
nst
ruct
ionanddat
arecei
vedf
rom t
hememor
yand
sentt
ot hememory.
 I
nst
ruct
ion Regist
er(IR)
:st
oreinst
ructi
ons.When one i
nst
ruct
ion i
s compl
eted,next
i
nst
ruct
ioni
sfetchedi
nmemoryf
orprocessi
ng.
 Pr
ogr
am Count
er(
PC)
:-keepcounti
nst
ruct
ions.

ComputerFuncti
on
Thebasi
cfunct
ionperf
ormedbyacomputeri
sexecut
ionofapr
ogr
am (
asetofi
nst
ruct
ionsst
oredi
n
memory)
.
•ThetwostepsofInstr
uct
ionsCy
clear
e:
 Fetch
 Execute

FetchCycl
e:
 Pr ogram Counter(PC)hol dsaddr essofnexti
nstructi
ontofetch,
 Pr ocessorfetchesinstructi
onf r
om memor ylocati
onpointedtobyPC,
 PCi si ncrement;
Unlesstoldotherwise,
 TheI nst r
ucti
onisloadedi ntoInstruct
ionRegi
ster(I
R)
Execut
eCy cl
e:
 ThePr ocessorint
erpretsinstr
uctionandperformsr equi
redacti
ons,
suchas:
 datatr
ansferbetweenCPUandmai nmemor y
 Datatr
ansferbetweenCPUandI /Omodule
 Somear i
thmeticorlogi
cal
operat
ionsondata
 Alt
erat
ionofsequenceofoperati
ons;e.
g.j
ump(br
anch)

FetchI nstr
ucti
on Decode Fet
chOperand Dat
aOper
ati
on St
ore
Oper and
(Cal.Inst.Addr
ess) (I
nter
pret
er) (
Cal
.DataAddr
ess) (Pr
ocess) (
Memor
y)

Ther
ear etwopar t
sininstr
uction:
-opcodeandoper and.
Infetchcycletheopcodeofi nstr
ucti
onisbroughtint
oCPU.
Theoper and,atfi
rst
,issenttoDat aRegi
ster(
DR) ,
thent
oInstr
ucti
onRegist
er(I
R).
Decoderaccessest heopcode, decodesi
tandt y
peofoperat
ionisdecl
aredtoCPUfor
executioncyclei
sstarted.

I
nst
ructionFormat s(Repr esent ati
on)
 Comput ercanper form aspeci fi
ctask,byfoll
owi ngspeci
fi
edstepstocompl etet
hetask.
 Acol lecti
onofsuchor deredst epsformsa‘ program’.
 Theor deredstepsar ecal ledtheinstr
uctions.
 Comput erinstruct
ionsar estoredincentralmemor yl
ocati
onsandar eexecutedsequenti
all
y
oneatat i
me.TheCPU- Controlunitr
eadsani nstr
ucti
onfrom aspecif
icaddressinmemor y
andexecut esit.
 I tthencont inuesbyr eadingt henexti nstr
uct i
oninsequenceandexecut esituntilthe
compl et
ionoft hepr ogram.

Acomputerusuall
yhasav ariet
yofI nstruct i
onCodeFor mat s.
 Iti
st hefunctionoft hecont rolunitwi thi
nt heCPUt oi nt
erpreteachi nstruct
ioncodeand
providethenecessar ycontrol f
unct ionsneededt opr ocesst heinstr
uct i
on.
 Annbi tinstructionhaskbi t
saddr essf i
eldandm bi tsoperat i
oncodef i
eld,
canaddressed
2klocationdi r
ect l
yandspeci f
y2m di ff
erentoper ation
 Thebi t
soft hei nstruct i
onar edividedi ntogr oupscal l
edf i
elds.
 Themostcommonf ieldsininstruct i
onformat sare:
 AnOper ationcodef ieldthatspeci fiestheoper at
iontobeper formed.
 AnAddr essf ieldthatdesi gnat esamemor yaddr essorapr ocessorregist
er.
 AModef ieldt hatspecifiest hewayt heoper and( ort
heef f
ectiveaddress)i
s
determi ned.
Fig:Instructi
onformatwithmodef ield
 Theoper ati
oncodef i
eld( Opcode)ofani nstr
ucti
oni sagr oupofbi t
st hatdefinev ar
ious
processoroperat
ionssuchasadd, subt
ract,complement ,shi
ftetc.
 Thebitsthatdefi
nethemodef i
eldofani nstructi
oncodespeci fyav ari
etyofalternati
vesfor
choosingtheoperandsfrom thegi venaddr ess.
 Operati
onspeci f
iedbyani nstructionisexecut edonsomedat ast oredint hepr ocessor
regi
sterorinthememor ylocat i
on.
o Oper andsresi
dinginmemor yarespecifi
edbyt rmemor
hei yaddr ess.
o Oper andsresi
dinginpr ocessorregisterarespecif
iedwi har
t egisteraddress.

 Ani
nst
ruct
ioni
srepr
esent
edassequenceofbi
ts,
forexampl
e:

TheI
nst
ruct
ionabov
eisdi
vi
dedi
ntof
iel
ds:

-i
 Opcode: ndi
cat
estheoper
ati
ontobeperf
ormed,eg.
,92abov
eindi
cat
esacopyoper
ati
on.
weneedtwooper onesour
ands; ceandot
herdest
inat
ion

 Oper
and-repr
esents:
o natureofoperands(
dat
aoraddr
ess)abov
e;oper
and1i
saddr
essandoper
and2i
s
dat
a
o mode(
regi
sterormemor
y),
oper
and1i
smemor
y,andoper
and2i
simmedi
atedat
a

Ty
pesofI
nst
ruct
ion
 Computers may haveinstr
ucti
ons ofdif
ferentl
engths,cont
aini
ng var
ying numberof
addr
esses.
 Thenumberofaddr essf i
eldsintheinst
ructi
onfor
matofacomput erdependsont he
i
nter
nalorgani
zat
ionofi
tsregist
ers.

Mostcomput ersfall
intooneof3t ypesofCPUor ganizati
ons:
Singl
eaccumul atororganizat
ion:
 Al ltheoper ati
onsar eperformedwi thanaccumul atorr
egist
er.
 Thei nstructi
onf ormatinthistypeofcomput erusesoneaddr essfiel
d.
Forexampl e:ADDX, whereXi st
headdr essoftheoperands.
Generalregist erorganizati
on:
 Thei nstructi
onf ormatinthistypeofcomput erneedsthreeregist
eraddressf i
elds.
Forexampl e:ADDR1, R2,R3
Stackorgani zation:
Theinstructioni nastackcomput erconsi
stsofanoper ati
oncodewi thnoaddr essfiel
d.
Thisoper ati
onhast heef f
ectofpoppi ngthe2t opnumber sfrom t
hest ack,operat
ingt henumber
s
andpushi ngt hesum i ntothestack.
Forexampl e:ADD

Thef
oll
owi
ngar
ethet
ypesofi
nst
ruct
ions:

1.Thr
eeaddr essInstructi
on
I
nt hi
st y
pe,eachi nstructi
onspecif
iestwooper andlocat
ionandar esul
tlocat
ion.At emporary
l
ocati
onTi susedt ostoresomeintermediat
eresultsoasnottoal
teranyoftheoperandlocat
ion.
Thethreeaddr essinstruct
ionf
ormatr equi
resav er
ycomplexdesigntoholdthet hr
eeaddr ess
r
efer
ences.
Format
:OpX, Y,Z;X YOpZ
Exampl
e: ADDX, Y,Z; XY+Z
o Adv angage:I
tresul
tsi
nshortpr
ogramswheneval
uati
ngar
it
hmeti
cexpressi
ons.
o Disadvantage:Thei
nstr
uct
ionsrequi
ret
oomanybit
stospeci
fy3addr
esses.

2.Twoaddr essinst
r ucti
on
Thi
sisthemostcommoni ncommer ci
alcomput er
s.
Hereeachaddr essfi
eldcanspeci f
yeit
heraprocessorregist
er,oramemoryword.
Oneaddressmustdodoubl edut yasbothoperandandresult.
Thetwoaddr essinst r
uctionformatreducesthespacer equir
ement.Toavoi
dalter
ingtheval
ueof
anoperand,aMOVi nstructionisusedtomov eoneofthev al
uest oar
esul
tortemporar
ylocat
ionT,
befor
eperformingtheoper ati
on.
Format :
OpX, Y;XXOpY
Exampl e:SUBX, Y;XX-Y

3.Oneaddr essInst
ruct
ion
Thiswasgener all
yusedi nearli
ermachi newi t
ht heimpli
edaddr essbeenaCPUr egi
sterknownas
accumulator.
Sot heOne-addr
essinst
ructi
onusesani mpliedaccumul at
or(Ac)regist
erf
oral
ldatamani
pulat
ion.
Alloper
ationsaredonebetweent heACr egisterandamemor yoperand.
WeuseLOADandSTOREi nst
ructionfortr
ansf erto/f
rom memoryandAcr egi
ster
.
Format:OpX; AcAcOpX
Example:MULX; AcAc*X

4.Zeroaddr essInstr
uction
Thi
sdoesnotuseanyaddr essfi
eldf
orthei
nst
ruct
ionli
keADD,SUB,
MUL, DI
V,etc.
Howev erPUSHandPOPi nstr
ucti
onsneedanaddressfi
eldt
ospeci
fyt
heoperandthatcommuni
cates
wit
ht hestack.
Thename“ Zer o”addressi sgiv
enbecauseoftheabsenceofanaddressfi
eldinthecomput
ati
onal
i
nstructi
on.
Format :Op; TOSTOSOp( TOS–1)
Exampl e:DI
V; TOSTOSDI V(TOS–1)

Letusil
l
ustr
atethei
nfl
uenceofthenumberofaddressoncomputerpr
ograms,wewillev
aluat
ethe
ari
thmeti
cstat
ementX=(A+B)
*(C+D)usi
ngZero,one,t
wo,ort
hreeaddressi
nst
ruct
ions.

1.Three-
Addr
essInstr
ucti
ons:
ADDR1,A,B;R1M[ A]+M[ B]
ADDR2,C,D;R2M[ C]+M[ D]
MULX,R1,R2; M[ X]R1*R2
I
tisassumedthatthecomput erhastwoprocessorr
egi
ster
sR1andR2.Thesy
mbol
M[A]denot
est
he
operandatmemoryaddresssy mboli
zedbyA.

2.Two-
Addr
essInst
ruct
ions:
MOVR1,A; R1M[ A]
ADDR1,B; R1R1+M[ B]
MOVR2,C; R2M[ C]
ADDR2,D; R2R2+M[ D]
MULR1,R2; R1R1*R2
MOVX,R1; M[ X]R1

3.One-
Addr
essI
nst
ructi
on:
LOADA; AcM[ A]
ADDB; AcAc+M[ B]
STORET; M[ T]Ac
LOADC; AcM[ C]
ADDD; AcAc+M[ D]
MULT; AcAc*M[ T]
STOREX; M[ X]Ac
Her
e,Tisthet
empor
arymemoryl
ocat
ionr
equi
redf
orst
ori
ngt
hei
nter
medi
ater
esul
t.

4.Zer
o-Addr
essI
nst
ruct
ions:
PUSHA; TOSA
PUSHB; TOSB
ADD; TOS( A+B)
PUSHC; TOSC
PUSHD; TOSD
ADD; TOS( C+D)
MUL; TOS( C+D)*(
A+B)
POPX; M[X]TOS

Sobasi
cal
l
ywehav ethefoll
owingInstr
ucti
onTypes
Notalli
nstr
uctionsrequi
retwooperands

3-addressinstr
ucti
ons
OperationSource1,Sour
ce2,Dest
inat
ion
e.g.AddA, B,C; C=A+B


2-addr
essinstr
ucti
ons
Operat
ionSource,Dest
inat
ion
e.
g.Mov eB,C; C=B
AddA, C; C=C+A
HereSource2isimpli
cit
lyt
hedest
inat
ion


1-addr
essinst
ruct
ions
e.
g.LoadA
Stor
eC


0-addr
essinst
ruct
ions
e.
g.Stop

Addr
essi
ngModes
Specifi
esar uleforint
erpretingormodi fyi
ngt headdr essf ieldofthei nstr
uctionbefor
etheoper
and
i
sact uallyreferenced.
Comput ersuseaddr essingmodet echniquesf orthepur poseofaccommodat i
ngthefol
lowi
ng
purposes: -
 Togi vepr ogrammi ngv ersati
l
itytotheuserbypr ovidingsuchf acili
ti
esaspoi nt
erstomemory,
count ersforloopcont r
ol, i
ndexingofdat aandv ariousot herpurposes.
 Tor educet henumberofbi t
sint headdressingfieldoft heinstructi
ons.
Somecomput er
suseasi nglebinaryforoper ation&Addr essmode.
Themodef iel
disusedt olocatetheoper and.
Addr essfieldmaydesi gnat eamemor yaddr essorapr ocessorr egi
ster.
Therear e2modest hatneednoaddr essf i
eldatal l(I
mpl i
ed&i mmedi at
emodes) .

Ef
fect
iveaddress(EA):
 Theef f
ectiv
eaddressisdefi
nedtobethememoryaddr
essobt
ainedfrom t
hecomput at
ion
di
ctat
edbyt hegivenaddr
essi
ngmode.
 Theef f
ectiv
eaddressistheaddr
essoftheoper
andi
nacomputational
-t
ypeinst
ruct
ion.

Thewel
lknownaddr
essi
ngmodesar
e:
 Impli
edAddr
essi
ngMode.
 I
mmedi ateAddr essingMode
 Regi sterAddr essingMode
 Regi sterIndi
rectAddr essi
ngMode
 Aut o-incr
ementorAut o-decr
ementAddr
essi
ngMode
 DirectAddr essingMode
 I
ndi rectAddr essingMode
 Displ acementAddr essAddressi
ngMode
 Relat iveAddressingMode
 I
ndexAddr essingMode
 StackAddr essingMode

ImpliedAddr essingMode:
I
nt hi
smodet heoperandsarespeci f
iedi
mplici
tl
yint
hedefini
ti
onoft hei
nstructi
on.
Forexampl e-CMA -“ complementaccumul at
or”i
san i mplied-
modei nstruct
ion becausethe
operandint heaccumul atorr
egisteri
simpli
edinthedefi
nit
ionoftheinst
ructi
on.
I
nf act,al
lregisterr
eferenceinst
ructi
onsthatuseanaccumulatorareimpl
ied-modeinstruct
ions.

Adv
ant
age:
nomemor
yref
erence.Di
sadv
ant
age:
li
mit
edoper
and

I
mmediateAddressi ngmode:
 I
nt hi
smodet heoperandisspeci
fi
edi nt heinstr
uct
ioni
tsel
f.Inotherwords,animmedi ate-
modei nstr
uct ionhasanoperandfi
eldratherthananaddressf i
eld.
 Thisi
nstructionhasanoper andfi
eldratherthananaddressfiel
d.Theoperandfiel
dcont ai
ns
theactualoper andtobeusedinconjunct i
onwi t
htheoperat
ionspecifi
edinthei
nstruct
ion.
 Theseinstructionsareusef
ulfori
nit
ial
izingregist
ertoaconstantvalue;
Forexampl eMVIB, 50H

I
twasment ionedprevi
ouslythattheaddressf i
eldofani nstr
uct
ionmayspecifyeit
heramemor y
wor
dorapr ocessorregi
ster.Whentheaddr essfiel
dspecifi
esapr ocessorr
egi
ster
,thei
nst
ruct
ion
i
ssaidtobeinregi
ster-
mode.
Adv
antage:nomemor yreference.Di
sadvantage:l
imitedoperand

Regi
sterdir
ectaddressingmode:
 Inthi
smode, theoper andsareinr
egist
erst
hatresidewit
hintheCPU.
 Theparti
cularregist
erisselect
edfrom t
heregi
sterfi
eldi
nt hei
nst
ruct
ion.Forexampl
eMOV
A,B

Ef
fecti
veAddress(
EA)=R
Advant
age:nomemoryref
erence.Di
sadv
ant
age:
li
mit
edaddr
essspace

Regi
sterI
ndirectAddr
essingMode:
 Int
hismodet heinstr
ucti
onspeci
fi
esar egisteri
ntheCPUwhosecont
entsgi
vetheaddr
ess
oftheoperandinthememor y
.
 Inotherwords,theselect
edregi
stercontainstheaddressoft
heoperandr
athert
hanthe
operanditsel
f.
 Beforeusingar egist
erindi
rectmodei nst
ruct
ion,t
heprogrammermustensur
et hatthe
memor yaddr ess ofthe operand i
s pl
aced i
nt he pr
ocessorr
egi
sterwi
th a prev
ious
inst
ruct
ion.
ForexampleLDAXB

Ef
fecti
veAddress( EA)=( R)
Advant
age:Largeaddr essspace.
Theaddr essf i
eldofthei nstr
ucti
onusesf
ewerbi
tstoselectar
egi
stert
hanwoul
d
havebeenr equiredtospecifyamemoryaddr
essdi
rect
ly.
Di
sadvant
age: Extr
amemor yreference

Aut
oincrementorAut odecr ementAddr essingMode:
 Thi si s simi l
art or egisteri ndirectmode exceptt hatt he regi steri
si ncremented or
decrement edaf ter(orbefor e)itsvaluei susedt oaccessmemor y.
 Whent headdr essst oredint her egistersreferstoatableofdat ai nmemor y,i
tisnecessary
toincrementordecr ementt her egistersafterever
yaccesst othet able.
 Thi scanbeachi evedbyusi ngt heincrementordecr ementinstruct i
on.Insomecomput er
sit
i
saut omat ical
lyaccessed.
 Theaddr essf ieldofani nst ructi
oni susedbyt hecont r
oltoobt aint
heoper andsf r
om
memor y.
 Somet imes t he v al
ue giv en i nt he addr ess fi
eldist he addr ess oft he operand,but
somet imesi tistheaddr essf rom whi cht headdresshast obecal culated.

Dir
ectAddressingMode
 Inthismodet heef
fect
iveaddr
essisequalt
otheaddresspar
toftheinst
ructi
on.The
operandr esi
desinmemor yandit
saddr
essisgi
vendir
ectl
ybytheaddr
essf i
eldofthe
inst
ruct
ion.
ForexampleLDA4000H

Ef
fecti
veAddr
ess(EA)=A
Advant
age:Si
mple.Di
sadv
ant
age:
li
mit
edaddr
essf
iel
d

I
ndi
rectAddr essi
ngMode
 I nthi
smodet headdressfiel
doftheinst
ruct
iongi
vestheaddr
esswheret
heeff
ecti
ve
addressisstoredinmemor y
.
 Cont rolunitf
etchestheinstr
ucti
onfrom t
hememor yandusesit
saddr
esspar
ttoaccess
memor yagai
nt oreadtheeffect
iveaddr
ess.
Ef
fect
iveAddr
ess(EA)=(A)
Advant
age:
Flexi
bil
i
ty. Di
sadv
ant
age:
Compl
exi
ty

Di
spl
acementAddr essi
ngMode
 Av er
ypower fulmodeofaddressi
ngwhichcombinesthecapabil
i
tiesofdirectaddr
essi
ng
andr
egisterindir
ectaddr
essi
ng.
 Theaddr essf i
eldofi
nstr
ucti
onisaddedtothecontentofspeci
fi
cr egi
sterintheCPU.

Ef
fecti
veAddr
ess(EA)=A+( R)
Advant
age:Fl
exi
bil
i
ty.Di
sadv
antage:
Compl
exi
ty

Relat
iveAddr essingMode
 I nthismodet hecontentoftheprogr
am counter(PC)i saddedtotheaddr esspar
tofthe
i
nstructi
oni nordert
oobtaintheeff
ect
iveaddress.
 Theaddr esspar toft heinstr
uct
ionisusuallyasi gnednumber( eit
hera+v eora–v e
number ).
 Whent henumberi saddedt othecontentoftheprogram count
er,ther esultpr
oducesan
eff
ectiveaddresswhoseposi t
ioni
nmemor yi
srelat
ivetotheaddr
essoft henextinstr
uct
ion.
Eff
ecti
v eAddress( EA)=PC+A

I
ndexedAddr essingMode
 Int hismodet hecont entofani ndexregister(XR)i saddedt otheaddresspartoft
he
i
nstructiontoobtai
nt heef fectiv
eaddr ess.
 Thei ndexr egi
sterisaspeci alCPUr egist
erthatcontainsanindexval
ue.
 Not e:Ifani ndex-
typei nstructi
ondoesnoti ncl
udeanaddr essf i
eldi
ni tsfor
mat,t
he
i
nstructionisautomaticallyconv ert
edt otheregist
erindir
ectmodeofoperat
ion.
Ef
fect
iveAddr ess(EA)=XR+A

BaseRegisterAddr essingMode
 I
nt hismodet hecont entofabaser egi
ster(BR)isaddedt ot headdr esspartofthe
i
nstructiontoobt aintheeffecti
veaddress.
 Thisissi mil
art ot heindexedaddr essi
ngmodeexceptt hattheregi
sterisnowcalledabase
regi
sterinsteadoft heindexr egi
ster.
 Thebaser egisteraddr essingmodei susedi ncomput erstofacil
it
atether el
ocat
ionof
programsi nmemor yi.
e.whenpr ogramsanddat aaremov edfr
om onesegmentofmemor y
toanother .
Eff
ect
iveAddr ess( EA)=BR+A

StackAddressi
ngMode
Thestackistheli
neararr
ayoflocati
ons.Iti
ssomet i
mesrefer
redt
oaspushdownl
i
storl
asti
n
Fi
rstout(
LIFO)queue.Thest
ackpointeri
smaint
ainedi
nregi
ster
.
Ef
fect
iveAddr
ess(
EA)=TOS

DataTransferAndMani pul
ation
Dat
at r
ansferinst
ruct
ionscauset r
ansferofdatafrom onel
ocat
iont
oanot
herwi
thoutchangi
ngt
he
bi
naryinf
ormat i
on.Themostcommont ransf
erarebetweenthe
 Memor yandProcessorregi
ster
s
 Pr ocessorregi
stersandinputoutputdevices
 Pr ocessorregi
stersthemselves

DataManipulat
ionInst
ruct
ions
Datamanipul
ati
oninstr
ucti
onsper f
orm oper
ationsondat
aandprovi
dethecomput
ati
onal
capabi
l
iti
esforthecomputer.Theseinst
ruct
ionsperf
orm ar
it
hmet
ic,
logi
candshi
ft
Pr
ogr
am Cont
rolI
nst
ruct
ions
Thepr ogram controlinst
ruct
ionsprov
idedecisi
onmaki ngcapabi
li
ti
esandchanget hepathtaken
bythepr ogram whenexecut edincomput er
.Theseinst
ructi
onsspeci
f ycondi
ti
onsf oral
teri
ngthe
contentoftheprogr am count
er.Thechangeinvalueofprogr
am counterasaresultofexecuti
onof
program controlinstruct
ioncausesabr eakinsequenceofi nst
ruct
ionexecution.Somet y
pical
program contr
olinstructi
onsare:

Si
mpl eInstr
ucti
onSet
Assumewehav eapr ocessorwhoseInst
ructi
onSetconsist
soffourmachi
nel
anguage
i
nstructi
ons
 Mov efrom amemor ylocat
iont
oadat aregi
steri
nCPU
 Mov efrom adat aregi
steri
nCPUtoamemor ylocati
on
 Addt hecontentsofamemor yl
ocationt
oadat aregi
ster
 St op
Supposeourprogram forZ=X+Yl ooksli
ke:
MoveX,D0
AddY,D0
MoveD0,Z
Stop

Thi
sprogram i
scodedi
ntomachi
nei
nst
ruct
ionandi
sloadedi
ntomemor
yst
art
ingatl
ocat
ion
$00000000

Howdoest heCPUknowwhi chinstructiontoexecut e?


Thereisadedi catedr egisterinCPUcal ledPr ogram Counter(PC)thatpoi
ntst
othememory
l
ocationwher enexti nstructionisst ored
Therefore,
atst ar
tPC=$00000000
 I nst
ructi
oni sinMai nMemor y–itistobet r
ansfer
red(f
etched)toCPUtobeexecut
ed
 CPUhasanI nstructionRegi ster(IR)thatholdstheinst
ruct
ion
 Whatki ndofi nstructionistobeexecut ed?
 CPUhasi t
sownI nstructi
onI nter
pr et
er( Decoder)
 Fol
l
owedbyI
nst
ruct
ionexecut
ion
 Nexti
nst
ruct
ionf
oll
ows.PCi
sincr
ement
edbyl
engt
hofi
nst
ruct
ionj
ustcompl
eted

Mechanism ofTr
ansferr
ingDatafrom MM t oCPU
CPUhasanext er
nalbusthatconnectsittotheMemor yandI/Odevi
ces.
Thedatali
nesareconnectedtotheprocessorv i
at heMemor yDat
aRegister(
MDR)
Theaddressli
nesareconnect
edt othepr ocessorviatheMemoryAddressRegist
er(
MAR)
 Memor yaddr
essf r
om wherethei nstr
uction/datai
stobeaccessediscopi
edi
ntoMAR
 Cont
ent
sofMARar
eloadedont
oaddr
essbus
 Cor
respondi
ngmemor
ylocat
ionaccessed
 Cont
ent
soft
hisl
ocat
ionputont
odat
abus
 Dat
aondat
abusl
oadedi
ntoMDR

Program Executi
on
FetchCycle:
 Processorfet
chesonei
nst
ruct
ionatat
imef
rom successi
vememor
ylocat
ionsunt
ila
br
anch/jumpoccur
s.
 I
nst
ruct
ionsar
elocat
edi
nthememor
ylocat
ionpoi
ntedt
obyt
hePC
 I
nst
ruct
ioni
sloadedi
ntot
heI
R
 I
ncrementthecontent
soft hePCbythesi
zeofani nstr
ucti
on
DecodeCycle:
 I
nstruct
ioni
sdecoded/int
erpret
ed,
opcodewillpr
ovidethetypeofoper
ati
ont
obe
per
formed,thenat
ureandmodeoft heoperands
 Decoderandcontr
ollogi
cuni
tisresponsibl
etosel
ectt
her
egi
ster
sinv
olv
edanddi
rectt
he
dat
at r
ansfer
.
Execut
eCy cl
e:
Carr
youttheacti
onsspecif
iedbyt
heinstruct
ionintheI
R

Execut
ionf
oraddX,
D0i
naGPRpr
ocessor
I
nst
ruct
ionExecut
ionTi
me
ClockCy cles(P)–isregularti
meint
erv
alsdef
inedbyt
heCPUcl
ock
ClockRat e,R=1/Pcy cl
espersecond(Hz)
500MHz=>P=2ns
1.25GHz=>P=0. 8ns
Foreachi nstr
ucti
on:
Fetch:Total12clockcy cl
es
MAR PC1
MDR M[MAR]10
IR MBR1
Decode: 2clockcycles
Execute:dependsoni nst
r uct
ion

Accumulator(Acc)Ar chit
ect ur
e
TheAcchasonl yONEr egister–accumul ator(Acc)insteadoftheRegist
erFil
e
Exampl e:Z=X+Y
Mov econtentsofl ocati
onXt oAcc
Addcont entsofl ocat i
onYt oAcc
Mov efr
om Acct olocationZ
Stop
 Alloperationsanddat amov ement sar eonthissi ngl
eregi
ster
 Mostoft heinstr
uctionsint heinstructi
onsetr equireonl
yoneOper and
 Destinati
onandSour cear eimpl ici
tl
yAcc
 Leadst oshor t
erinstructi
onsbutpr ogram maybesl owertoexecut
esincet
her
ear
emor
e
mov est omemor yforintermedi ateresult
s(tofreeAcc)
 Mayl eadt oineff
ici
ency

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