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TMP64-Q1
SNIS220A – MARCH 2020 – REVISED JUNE 2020

TMP64-Q1 ±1% 47-kΩ Linear Thermistor With 0402 Package

1 Features 3 Description
1• AEC-Q100 qualified with the following results: Get started today with the Thermistor Design Tool,
offering complete resistance vs temperature table (R-
– Temperature Grade 1: –40 °C ≤ TA ≤ 125 °C T table) computation, other helpful methods to derive
– HBM ESD classification level H2 temperature and example C-code.
– CDM ESD classification level C6 Linear thermistors offer linearity and consistent
• Silicon-based thermistor with a sensitivity across temperature to enable simple and
positive temperature coefficient (PTC) accurate methods for temperature conversion. Low
• Linear resistance change across temperature power consumption and a small thermal mass
minimize the impact of self-heating. With built-in
• 47-kΩ nominal resistance at 25 °C (R25) failsafe behavior at high temperatures and powerful
– ±1% maximum (0 °C to 70 °C) immunity to environmental variation, these devices
• Consistent sensitivity across temperature are designed for a long lifetime of high performance.
The small size of the TMP6 series also allows for
– 6400 ppm/°C TCR (25 °C)
close placement to heat sources and quick response
– 0.2% typical TCR tolerance across times.
temperature range
Take advantage of benefits over NTC thermistors
• Fast thermal response time of 0.6 s (DEC) such as no extra linearization circuitry, minimized
• Long lifetime and robust performance calibration, less resistance tolerance variation, larger
– Built-in fail-safe in case of short-circuit failures sensitivity at high temperatures, and simplified
conversion methods to save time and memory in the
– 0.5% typical long term sensor drift processor.
2 Applications The TMP64-Q1 is currently available in a 0402
footprint-compatible X1SON package.
• Thermal compensation
– Display backlight Device Information(1)
– Battery management systems PART NUMBER PACKAGE BODY SIZE (NOM)
• Thermal threshold detection TMP64-Q1 X1SON 0.60 mm × 1.00 mm

– Motor control (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– On-board chargers & DC-DC converters
Typical Implementation Circuits Typical Resistances vs Ambient Temperature
VBias 90

RBias IBias 75
Resistance (k:)

60
RTMP64 VTemp RTMP64 VTemp

45

30
-40 -20 0 20 40 60 80 100 120 140
Temperature (qC) 64_F

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.4 Feature Description................................................. 10
2 Applications ........................................................... 1 8.5 Device Functional Modes........................................ 10
3 Description ............................................................. 1 9 Application and Implementation ........................ 11
4 Revision History..................................................... 2 9.1 Application Information............................................ 11
9.2 Typical Application .................................................. 11
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 4 10 Power Supply Recommendations ..................... 16
7 Specifications......................................................... 5 11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
7.1 Absolute Maximum Ratings ...................................... 5
11.2 Layout Example .................................................... 16
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 17
7.4 Thermal Information .................................................. 5 12.1 Receiving Notification of Documentation Updates 17
7.5 Electrical Characteristics........................................... 6 12.2 Support Resources ............................................... 17
7.6 Typical Characteristics .............................................. 7 12.3 Trademarks ........................................................... 17
12.4 Electrostatic Discharge Caution ............................ 17
8 Detailed Description .............................................. 9
12.5 Glossary ................................................................ 17
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9 13 Mechanical, Packaging, and Orderable
8.3 TMP64-Q1 R-T table............................................... 10
Information ........................................................... 17

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision Original (March 2019) to Revision A Page

• Changed data sheet status from: Advanced Information to: Production Data ....................................................................... 1
• Added Device Comparison table ............................................................................................................................................ 3

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5 Device Comparison Table

PART
R25 TYP R25 %TOL RATING TA PACKAGE OPTIONS
NUMBER
X1SON / DEC (0402)
–40 °C to 125 °C
TMP61 10k 1% Catalog SOT-5X3 / DYA (0603)
–40 °C to 150 °C TO-92S / LPG
X1SON / DEC (0402)
Automotive Grade-1 –40 °C to 125 °C
TMP61-Q1 10k 1% SOT-5X3 / DYA (0603)
Automotive Grade-0 –40 °C to 170 °C TO-92S / LPG
X1SON / DEC (0402)
TMP63 100k 1% Catalog –40 °C to 125 °C
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
TMP63-Q1 100k 1% Automotive Grade-1 –40 °C to 125 °C
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
TMP64 47k 1% Catalog –40 °C to 125 °C
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
TMP64-Q1 47k 1% Automotive Grade-1 –40 °C to 125 °C
SOT-5X3 / DYA (0603)

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6 Pin Configuration and Functions

DEC Package
2-Pin X1SON
Bottom View

± 1 2 +

Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
– 1 Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the +
—
+ 2 terminal is at a higher voltage potential than the – terminal.

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7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage across pins 2 (+) and 1 (–) +6 V
Current through the device +450 µA
Junction temperature (TJ) –65 +150 °C
Storage temperature (Tstg) –65 +150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002 (1)
±2000 V
HBM classification level 2
VESD Electrostatic discharge
Charged-device model (CDM), per AEC Q100-011
±1000 V
CDM classification level C6

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VSns Voltage across pins 2 (+) and 1 (–) 0 5.5 V
ISns Current passing through the device 0 100 µA
TA Operating free-air temperature (specified performance) (X1SON/DEC Package) –40 125 °C

7.4 Thermal Information

TMP64-Q1
(1)
THERMAL METRIC DEC (X1SON) Units
2 PINS
RθJA Junction-to-ambient thermal resistance (2) (3) 443.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 195.7 °C/W
RθJB Junction-to-board thermal resistance 254.6 °C/W
ΨJT Junction-to-top characterization parameter 19.9 °C/W
ΨJB Junction-to-board characterization parameter 254.5 °C/W
RθJC(bot) Junction-to-case (bot) thermal resistance – °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
(3) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.

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7.5 Electrical Characteristics

TA = -40 °C - 125 °C, ISns = 42.553 μA (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R25 Thermistor Resistance at 25 °C TA = 25 °C 46.53 47 47.47 kΩ
TA = 25 °C –1 1
RTOL Resistance Tolerance TA = 0 °C - 70 °C –1 1 %
TA = -40 °C - 125 °C –1.5 1.5
TCR-35 T1 = -40 °C, T2 = -30 °C +6220
TCR25 Temperature Coefficient of Resistance T1 = 20 °C, T2 = 30 °C +6400 ppm/°C
TCR85 T1 = 80 °C, T2 = 90 °C +5910
TCR-35 % T1 = -40 °C, T2 = -30 °C ±0.4
TCR25 % Temperature Coefficient of Resistance Tolerance T1 = 20 °C, T2 = 30 °C ±0.2 %
TCR85 % T1 = 80 °C, T2 = 90 °C ±0.3
96 hours continuous operation at RH = 85% and
TA = 130 °C -1 ±0.1 1
ΔR Sensor Long Term Drift (Reliability) VBias = 5.5 V %
600 hours continuous operation at TA = 150 °C
-1 0.5 1.8
VBias = 5.5V
tRES (stirred T1 = 25 °C in Still Air to T2 = 125 °C in Stirred
Thermal response to 63% 0.6 s
liquid) Liquid
tRES (still air) Thermal response to 63% T1 = 25 °C to T2 = 70 °C in Still Air 3.2 s

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7.6 Typical Characteristics

at TA = 25 °C, (unless otherwise noted)

100 100

80 80
Resistance (k:)

Resistance (k:
60 60

40 40
IBIAS = 2 PA
IBIAS = 10 PA VBIAS = 1.8 V
20 IBIAS = 20 PA 20 VBIAS = 2.5 V
IBIAS = 42.6 PA VBIAS = 3.3 V
IBIAS = 100 PA VBIAS = 5 V
0 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (qC) 64_R
Temperature (qC) 64_R

RBias = 47 kΩ with ±0.01 % Tolerance

Figure 1. Resistance vs. Ambient Temperature Using Figure 2. Resistance vs. Ambient Temperature Using
Multiple Bias Currents Multiple Bias Voltages
6500 6500

6400 6400
TCR (ppm/qC)

TCR (ppm/qC)

6300 6300

6200 6200

6100 6100

6000 6000
0 10 20 30 40 50 60 70 80 90 100 1.5 2 2.5 3 3.5 4 4.5 5
Bias Current (PA) 64_T
Bias Voltage (V) 64_T

RBias = 47 kΩ with ±0.01% Tolerance

Figure 3. TCR as a Function of Sense Current, ISNS Figure 4. TCR as a Function of Sense Voltage, VSNS
100 100

80 80
Resistance (k:)

Resistance (k:)

60 60

40 40

20 -40 qC 100 qC 20 -40 qC 100 qC

25 qC 125 qC 25 qC 125 qC
50 qC 50 qC
0 0
0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Bias Current (PA) 64_s
Bias Voltage (V) 64_s

RBias = 47 kΩ with ±0.01% Tolerance

Figure 5. Supply Dependence Resistance vs. Bias Current Figure 6. Supply Dependence R vs. VBias

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Typical Characteristics (continued)

at TA = 25 °C, (unless otherwise noted)
2.5 85

80
2
75

Resistance (k:)
1.5 70
Output (V)

65
1 60

55
0.5
VBias 50
VSNS
0 45
0 2 4 6 8 10 12 14 0 0.2 0.4 0.6 0.8 1
Time (Ps) 64_s
Time (s) 64_r

TMP64-Q1: VSNS = 1 V TMP64-Q1: Stirred Liquid. Temperature: 25 °C to 125 °C

Figure 7. Step Response Figure 8. Thermal Response Time

64

62

60

58
Resistance (k:)

56

54

52

50

48

46
0 2 4 6 8 10 12 14 16
Time (s) 64_r

TMP64-Q1: Still Air

Figure 9. Thermal Response Time

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8 Detailed Description

8.1 Overview
The TMP64-Q1 silicon linear thermistor has a linear positive temperature coefficient (PTC) that results in a
uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. TI
uses a special silicon process where the the doping level and active region areas devices control the key
characteristics (the temperature coefficient resistance (TCR) and nominal resistance (R25)) . The device has an
active area and a substrate due to the polarized terminals. Connect the positive terminal to the highest voltage
potential. Connect the negative terminal to the lowest voltage potential.
Unlike an NTC, which is a purely resistive device, the TMP64-Q1 resistance is affected by the current across the
device and the resistance changes when the temperature changes. In a voltage divider circuit, it is recommended
to maintain the top resistor value at 47 kΩ. Changing the top resistor value or the VBIAS value changes the
resistance vs temperature table (R-T table) of the TMP64-Q1, and subsequently the polynomials as described in
the Design Requirements section. Consult the TMP64-Q1 R-T table section for more information.
TCR (ppm/°C) = (RT2 – RT1) / ((T2 – T1) × R(T2+T1)/2) (1)
Below are the definitions of the key terms used throughout this document:
• ISNS: Current flowing through the TMP64-Q1.
• VSNS: Voltage across the two TMP64-Q1 terminals.
• IBias: Current supplied by the biasing circuit.
• VBias: Voltage supplied by the biasing circuit.
• VTemp: Output voltage that corresponds to the measured temperature. Note that this is different from VSns. In
the use case of a voltage divider circuit with the TMP64-Q1 in the high side, VTemp is taken across RBias.

8.2 Functional Block Diagram

VBias

RBias IBias

RTMP64 VTemp RTMP64 VTemp

Figure 10. Typical Implementation Circuits

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8.3 TMP64-Q1 R-T table

The TMP64-Q1 R-T table must be re-calculated for any change in the bias voltage, bias resistor, or bias current.
TI provides a Thermistor Design Tool to calculate the R-T table. The system designer should always validate the
calculations provided.

8.4 Feature Description

8.4.1 Linear resistance curve
The TMP64-Q1 has good linear behavior across the whole temperature range as shown in Figure 1. This range
allows a simpler resistance-to-temperature conversion method that reduces look-up table memory requirements.
The linearization circuitry or midpoint calibration associated with traditional NTCs is not necessary with the
device.
The linear resistance across the entire temperature range allows the device to maintain sensitivity at higher
operating temperatures.

8.4.2 Positive Temperature Coefficient (PTC)

The TMP64-Q1 has a positive temperature coefficient. As temperature increases the device resistance increases
leading to a reduction in power consumption of the bias circuit. In comparison, a negative coefficient system
increases power consumption with temperature as the resistance decreases.
The TMP64-Q1 benefits from the reduced power consumption of the bias circuit with less self-heating than a
typical NTC system.

8.5 Device Functional Modes

The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TMP64-Q1 is a positive temperature coefficient (PTC) linear silicon thermistor. The device behaves like a
temperature-dependent resistor, and may be configured in a variety of ways to monitor temperature based on the
system-level requirements. The TMP64-Q1 has a nominal resistance at 25 °C (R25) of 47 kΩ, a maximum
operating voltage of 5.5 V (VSns), and maximum supply current of 100 µA (ISns). This device may be used in a
variety of applications to monitor temperature close to a heat source with the very small DEC package option
compatible with the typical 0402 (inch) footprint. Some of the factors that influence the total measurement error
include the ADC resolution (if applicable), the tolerance of the bias current or voltage, the tolerance of the bias
resistance in the case of a voltage divider configuration, and the location of the sensor with respect to the heat
source.

9.2 Typical Application

9.2.1 Thermistor Biasing Circuits

Figure 11. Biasing Circuit Implementations With Linear Thermistor (Left) vs. Non-Linear Thermistor
(Right)

9.2.1.1 Design Requirements

Existing thermistors, in general, have a non-linear temperature vs. resistance curve. To linearize the thermistor
response, the engineer can use a voltage linearization circuit with a voltage divider configuration, or a resistance
linearization circuit by adding another resistance in parallel with the thermistor, RP. The Thermistor Biasing
Circuits section highlights the two implementations where RT is the thermistor resistance. To generate an output
voltage across the thermistor, the engineer can use a voltage divider circuit with the thermistor placed at either
the high side (close to supply) or low side (close to ground), depending on the desired voltage response
(negative or positive). Alternatively, the thermistor can be biased directly using a precision current source

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Typical Application (continued)

(yielding the highest accuracy and voltage gain). It is common to use a voltage divider with thermistors because
of its simple implementation and lower cost. The TMP64-Q1, on the other hand, has a linear positive temperature
coefficient (PTC) of resistance such that the voltage measured across it increases linearly with temperature. As
such, the need for a linearization circuits is no longer a requirement, and a simple current source or a voltage
divider circuit can be used to generate the temperature voltage.
This output voltage can be interpreted using a comparator against a voltage reference to trigger a temperature
trip point that is either tied directly to an ADC to monitor temperature across a wider range or used as feedback
input for an active feedback control circuit.
The voltage across the TMP64-Q1, as described in Equation 2, can be translated to temperature using either a
lookup table method (LUT) or a fitting polynomial, V(T). The Thermistor Design Tool must be used to translate
Vtemp to Temperature. The temperature voltage must first be digitized using an ADC. The necessary resolution
of this ADC is dependent on the biasing method used. Additionally, for best accuracy, the bias voltage (VBIAS)
should be tied to the reference voltage of the ADC to create a measurement where the difference in tolerance
between the bias voltage and the reference voltage cancels out. The engineer can also implement a low-pass
filter to reject system level noise, and the user should place the filter as close to the ADC input as possible.

9.2.1.2 Detailed Design Procedure

The resistive circuit divider method produces an output voltage (VTEMP) scaled according to the bias voltage
(VBIAS). When VBIAS is also used as the reference voltage of the ADC, any fluctuations or tolerance error due to
the voltage supply is canceled and does not affect the temperature accuracy. This type of configuration is shown
in Figure 12. Equation 2 describes the output voltage (VTEMP) based on the variable resistance of the TMP64-Q1
(RTMP64-Q1) and bias resistor (RBIAS). The ADC code that corresponds to that output voltage, ADC full-scale
range, and ADC resolution is given in Equation 3.
VBias

RBias
RFilter REF
IN
ADC
RTMP64 CFilter
IN
GND

Figure 12. TMP64-Q1 Voltage Divider With an ADC

§ RTMP64 ·
VTEMP VBIAS u ¨ ¸
© RBIAS RTMP64 ¹ (2)
§ VTEMP · n
ADC Code ¨ FSR ¸u2
© ¹
where
• FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF)
• n is the resolution of the ADC (3)
Equation 4 shows whenever VREF = VBIAS, VBIAS cancels out.
§ § RTMP64 ··
¨ VBIAS u ¨ ¸¸
¨ © BIAS RTMP64
R ¹ ¸ u 2n § RTMP64 · n
ADC Code ¨ ¸ ¨ ¸u2
VBIAS © BIAS RTMP64
R ¹
¨ ¸
¨ ¸
© ¹ (4)

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Typical Application (continued)

The engineer can use a polynomial equation or a LUT to extract the temperature reading based on the ADC
code read in the microcontroller. The Thermistor Design Tool should be used to translate the TMP64-Q1
resistance to temperature.
The cancellation of VBIAS is one benefit to using a voltage-divider (ratiometric approach), but the sensitivity of the
output voltage of the divider circuit cannot increase much. Therefore, not all of the ADC codes are used due to
the small voltage output range compared to the FSR. This application is very common, however, and is simple to
implement.
The engineer can use a current source-based circuit, like the one shown in Figure 13, to have better control over
the sensitivity of the output voltage and achieve higher accuracy. In this case, the output voltage is simply V = I ×
R. For example, if a current source of 100 µA is used with the TMP64-Q1, the output voltage spans
approximately 5.5 V and has a gain up to 40 mV/°C. Having control over the voltage range and sensitivity allows
for full utilization of the ADC codes and full-scale range. Similar to the ratiometric approach above, if the ADC
has a built-in current source that shares the same bias as the reference voltage of the ADC, the tolerance of the
supply current cancels out. In this case, a precision ADC is not required. This method yields the best accuracy,
but can increase the system implementation cost.

Precision
IBias Current Source

RTMP64 VTemp

Figure 13. TMP64-Q1 Biasing Circuit With Current Source

In comparison to the non-linear NTC thermistor in a voltage divider, the TMP64-Q1 has an enhanced linear
output characteristic. The two voltage divider circuits with and without a linearization parallel resistor, RP, are
shown in Figure 14. Consider an example where VBIAS = 5 V, RBIAS = 47 kΩ, and a parallel resistor (RP) is used
with the NTC thermistor (RNTC) to linearize the output voltage with an additional 47-kΩ resistor. The TMP64-Q1
produces a linear curve across the entire temperature range while the NTC curve is only linear across a small
temperature region. When the parallel resistor (RP) is added to the NTC circuit, the added resistor makes the
curve much more linear but greatly affects the output voltage range.
VBias VBias

RBias RBias

RTMP64 VTemp RNTC RP VTemp

Figure 14. TMP64-Q1 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits

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Typical Application (continued)

9.2.1.2.1 Thermal Protection With Comparator
The engineer can use the TMP64-Q1, a voltage reference, and a comparator to program the thermal protection.
As shown in Figure 15, the output of the comparator remains low until the voltage of the thermistor divider, with
RBIAS and RTMP64-Q1, rises above the threshold voltage set by R1 and R2. When the output goes high, the
comparator signals an overtemperature warning signal. The engineer can also program the hysteresis to prevent
the output from continuously toggling around the temperature threshold when the output returns low. Either a
comparator with built-in hysteresis or feedback resistors may be used.
VBias

RBias R1

VTrip
RTMP64
R2

Figure 15. Temperature Switch Using TMP64-Q1 Voltage Divider and a Comparator

9.2.1.2.2 Thermal Foldback

One application that uses the output voltage of the TMP64-Q1 in an active control circuit is thermal foldback.
This is performed to reduce, or fold back, the current driving a string of LEDs, for example. At high temperatures,
the LEDs begin to heat up due to environmental conditions and self heating. Thus, at a certain temperature
threshold based on the LED's safe operating area, the driving current must be reduced to cool down the LEDs
and prevent thermal runaway. The TMP64-Q1 voltage output increases with temperature when the output is in
the lower position of the voltage divider and can provide a response used to fold back the current. Typically, the
current is held at a specified level until a high temperature is reached, known as the knee point, where the
current must be rapidly reduced. To better control the temperature/voltage sensitivity of the TMP64-Q1, a rail-to-
rail operational amplifier is used. In the example shown in Figure 16, the temperature “knee” where the foldback
begins is set by the reference voltage (2.5 V) at the positive input, and the feedback resistors set the response of
the foldback curve. The foldback knee point may be chosen based on the output of the voltage divider and the
corresponding temperature from Equation 5 (like 110 °C, for example). A buffer is used in-between the voltage
divider with RTMP64-Q1 and the input to the op amp to prevent loading and variations in VTEMP.

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Typical Application (continued)

5V

RFB
RBias R2 300 k
94 k 200 k
R1
10 k
VTemp VOut
VRef

RTMP64 R3
200 k

Figure 16. Thermal Foldback Using TMP64-Q1 Voltage Divider and a Rail-to-Rail Op Amp

The op amp remains high as long as the voltage output is below VRef. When the temperature goes above 110 °C,
then the output swings low to the 0-V rail of the op amp. The rate at which the foldback occurs is dependent on
the feedback network, RFB and R1, which varies the gain of the op amp, G, given by Equation 6. This in return
controls the voltage/temperature sensitivity of the circuit. This voltage output is fed into a LED driver IC that
adjusts output current accordingly. The final output voltage used for thermal foldback is VOUT, and is given in
Equation 7. In this example where the knee point is set at 110 °C, the output voltage curve is as shown in
Figure 17.
§ RTMP64 ·
VTEMP VBIAS u ¨ ¸
© RBIAS RTMP64 ¹ (5)
RFB
G
R1 (6)
VOUT G u VTEMP 1 G u VREF (7)
6

4
VTEMP (V)

0
0 25 50 75 100 125 150
Temperature (qC) D014

Figure 17. Thermal Foldback Voltage Output Curve

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10 Power Supply Recommendations

The maximum recommended operating voltage of the TMP64-Q1 is 5.5 V (VSns), and the maximum current
through the device is 100 µA (ISns).

11 Layout

11.1 Layout Guidelines

The layout of the TMP64-Q1 is similar to that of a passive component. If the device is biased with a current
source, the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the
circuit is biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is
connected to ground, and V+ is connected to the output (VTEMP). If the device is placed on the upper side of the
divider, V+ is connected to the voltage source and V– is connected to the output voltage (VTEMP). Figure 18
shows the device layout.

11.2 Layout Example

Figure 18. Recommended Layout: DEC Package

16 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

Product Folder Links: TMP64-Q1

 TMP64-Q1
www.ti.com SNIS220A – MARCH 2020 – REVISED JUNE 2020

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2020, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TMP64-Q1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Jun-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TMP6431QDECRQ1 ACTIVE X1SON DEC 2 10000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HJ
& no Sb/Br)
TMP6431QDECTQ1 ACTIVE X1SON DEC 2 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 HJ
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Jun-2020

OTHER QUALIFIED VERSIONS OF TMP64-Q1 :

• Catalog: TMP64

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP6431QDECRQ1 X1SON DEC 2 10000 178.0 8.4 0.7 1.15 0.47 2.0 8.0 Q1
TMP6431QDECTQ1 X1SON DEC 2 250 178.0 8.4 0.7 1.15 0.47 2.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jun-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP6431QDECRQ1 X1SON DEC 2 10000 205.0 200.0 33.0
TMP6431QDECTQ1 X1SON DEC 2 250 205.0 200.0 33.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DEC0002A SCALE 11.000
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

1.05 B
A
0.95

PIN 1 INDEX AREA

0.65
0.55

0.50
0.41
C

SEATING PLANE
0.05
0.00 0.03 C

0.65

1 2
SYMM
0.55
2X
0.45
0.1 C A B

PIN 1 ID SYMM
(45 X0.125) 0.3
2X
0.2
0.1 C A B

4224506/A 08/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
DEC0002A X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (0.25) SYMM

SYMM
2X (0.5)

(R0.05) TYP
(0.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:60X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
METAL EDGE
METAL UNDER
EXPOSED SOLDER MASK
METAL
EXPOSED
METAL SOLDER MASK SOLDER MASK
OPENING OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4224506/A 08/2018

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DEC0002A X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (0.3) (0.05)
SYMM

PCB PAD METAL

UNDER SOLDER PASTE

SYMM
2X (0.5)
1 2

(R0.05) TYP
(0.7)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:60X

4224506/A 08/2018
NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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