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Casio CZ-5000 Synthesizer. Service documentation.
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0% found this document useful (0 votes)
311 views60 pagesCasio CZ-5000 Service Manual
Casio CZ-5000 Synthesizer. Service documentation.
Uploaded by
Bigg DadyCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 60
Service Manuat
& PARTS LIST mm
LESOOD
JUNE 1985
RO
CASIO. CAUTION:
When the connector © (from the batteries) is disconnected, all the sound data in the Memory Bank
‘are cleared. When this happens, initialize the unit by the following procedures.
1, Turn the power switch off and press INITIALIZE button.
2. Turn the power switch on, then the display indicates;
SYSTEM ALL
INITIALIZEC Y/N)?
3. While pushing INITIALIZE button, press YES button on the data entry section of the panel
All the Memory Bank data are initialized, then the display shows:
SYSTEM
INITIALIZED !! 2
4
6.
16.
"7.
18,
19,
CONTENTS
SCHEMATIC DIAGRAM ......
14. Main PCB (A) M5153. MAIM
1-2. Main PCB (B) M6153-MA1M
13. Stereo Chorus Circuit PCB M5162. MA2M .
1-4, MIDI and MT Control PCB M5153-MA3M .
1.5. Amp. Block PCB M5153-ASIM ....
1.6. LED Drive Circuit PCB M5153-MA4M
1-7. Panel Block (A) PCB M5153-CN1M
1-8. Panel Block (B) PCB M5153-CN2M
1.9, Modulation Switch PCB M5153-CN3 .
1-10. Power Supply Circuit PCB M5183-PS1, PS2....
1.11. Keyboard (1) PCB M416-KY1
12. Keyboard (2) PCB M416-KY2
1-13, Keyboard PCB M425-KY3
WIRING DIAGRAM
PCB VIEW & MAJOR CHECKPOINT .
34, PCBM5153.MAIM
32. PCBMS153MAZM .
MAJOR WAVEFORMS .
BLOCK DIAGRAM.
DIGITAL CIRCUIT BLOCK DIAGRAM .....
MAIN CPU (uPD7811-180)
SUB-CPU (uPD7811-204) ....
MAIN. RAMS & ROM ACCESS
‘SUB-RAMS & ROM ACCESS
ACCESS TO MUSIC LSI...
CPU INTERFACE (MB64H173) .
12-1. Funetion of Each Block
12.2. Data Transfer Procedures . .
KEY MATRIX .
LED DRIVING CIRCUITS .
ANALOG CIRCUIT BLOCK DIAGRAM .
MUSIC LSI (uPD933) ........ :
DAC (Digital to Analog Converter)...
EXPANDER CIRCUIT
SAMPLE & HOLD CIRCUIT . 20. STEREO CHORUS CIRCUIT ........
20.
20-2. VCO (Voltage Controlled Oscillator)
203. BBD (Bucket Brigade Device). .
20-4. Compressor and Expander Circuits.
VOLUME CONTROL CIRCUIT . =.
REBET CIRCUIT, 0222002222 000205 48
MIDI & MT INTERFACE CIRCUITS
23-1, MIDI Interface
23.2. MT Interface Circuit...
24, ADJUSTMENT ...........
24-1. DAC Offset Voltage
242. Volume Adjustment
PARTS LIST.
EXPLODED VIEW .....
BRS
‘Three-Phase LFO (Low Frequency Oscillator) ...
agges
45,
aageaas 1. SCHEMATIC DIAGRAM
1A, Main POD (A) MBTEOMA IA 112, Min POB (8) MSTSS.NATME 14, MIDI and MT Control PC MSI52-MASM eviesisn goa Iron sang G37 “64 2
8
3
2
8
5
:
wef]
(reno es
(Corea oD
(01D
ziow
Tan 060194»
a
(unasenPr)
LED
=
MODULATION (eise[a ea) {2208} ong
Gres) oe}
f
faye
i
GAgaOR08
(aa
are
iTS] {Ew og d vISeW I>
LAr (1) PmoRAay, ssw]
ZANSLDN B04 (2 PHONE ZL
: eS:
——o
=
ee
[2550 1-13. Keyboard PCB M425-KY3
4 Ket (Kc10)
KB (Ko)
oO
Ko? (Ke8)
=13— 2. WIRING DIAGRAM Not!
R: Red
Y= Yelk
1. Wire Color Codes
low
BK: Black
GY: Gray
2. Terminal Readings
Signal Name
\
Les,
to
-vee
Wo: White BL: Blue
GR: Green PP: Purple
BR: Brown ©: Orange
PK : Pink E : Shielded wire
oiner (Flat Cable)
LS poor
7 [ate
Cone finer“ FP ct
Connector “8 Pin 7
Power connector D pin 2
eR | MASM |
Connect to PCB MA.2M through brown wire
“So [p02 [coz | asim
Connected to Connector D pin 2 on PCB ASM
3. Voltage Levels
voD) +8V For digital circuits
vou | +5v For LED driving
vow | +5v For LED driving (rises to +8V approximately
10 milliseconds after Power ON)
| voac | +8v For DAC (Digital to Analog Converter)
4vec | +16V_ | For analog circuits
=vec | -15V | For analog circuits
0G ov Digital ground
| FG ov Frame ground
DAG ov DAC ground ze
cG ov ‘Analog ground
VBR | +5VatPowerON | RAMs’ backup voltage
+43.9V at Power OFF,
16 — 3. PCB VIEW & MAJOR CHECKPOINT Gr
Wevneesisn soa ze
ay
BA 4. MAJOR WAVEFORMS:
Notes: Photographs marked (@) show stored waveforms in a memory scope.
The analog waveforms were observed via a 28 Kohm resistor.
Oscilloscope probe
28K
Checkpoint
Wy
© 1707811 cock puss @ wrosas cick pul
Pos weiss mate Pos MBis3.MAIM
74HCUOE pin 6 74HCUO2 pin 2
Ossi, 2V/di O.4aleiv, 2V/
@ ove @ vacourout © 008 ond G) DAC ourwuts
PCB M5ISSMAIM Pee weIs2MAIM Same conditions es (3) ond @)
10083 pin 22 TL082¢ pin? ‘except msi of sweep
NOysicv, BV/di tus, 6Via time and sing 3 memory scope.
Tone: Flute, Key: C8 Tone: Flute, Key: C4
~18- @
®
®
DAC output
PCB -MBIsaMAIM
L082: pin 7
2mu/div. BV/dN
Tone: Flute, Key: C8
Expander Gireuit output
PCB MSISS.MAIM
‘TL0823 pin 1
2ms/iv.,O5Vidl.
Tone: Flute, Key: CA
Master LSI DOE signal
PCB M5153: MAIM
uPD833-1 pin 22
Ousiav., 2V/v.
Master LSI SH signal
PCB MISS MAIM
P0322 pin 23
Oui, 2V/d.
-19
® Dac output nd ( Exoander
Gireut oupat
Same condition a+ () and
®
®
‘excopt using a mamary scope.
Mastor LSI SH signal
Poe MSISSMAIM
uPDE33-1 pin 23,
O.tps/div., 2 lv
Sample & Hold Greuit output
PCB SIS. MAIM
T0822 pin 7
ipsa, 2V/v.
Tone: Flute, Key: C7 RUAcay
aL nC
AA ACCEL EEE
@® Master Ls! SH signs! @ 04H. LO ouput
roe MStSSHuari Poe wstsenaan
P0881 pin 23 Totoee-t in
‘Ojai 2V/a Ody, 2vt
® Stave Lt SH signal @ 6.12 LFO ouput
Poo wsisowatna ro wsisoqaaut
109002 pn 23 To4oo0: pin
Toy, 2Vid Ort. 20
© Wires 06442 and 6:1He signals @ Fite Acutut
PCB M5159-MAIM Poe MSis3MAaM
‘Anode of VCO input diode NM4558.2 pin 7
‘wv, WV 2msiav, OSV
@ eed ourpur
Poe wsts2.MAIM
MN3208-1 pin
2msfdv., V/s
~20- pod
oS vu ‘ecco iuscos 04
ae
fy
ano mal = Wal (penal
ar eee Sno ie eis
a Ss :
ima faa
adoans
wae
er
gee | Vy
auaeoso4 eran eo se tal 10
now oat
aE
Wvuovia 19078 “s
on 6. DIGITAL CIRCUIT BLOCK DIAGRAM
=
sae ==
—
2
& 28
Invertace 28 Main RAM
zf oe
epee :
aaa
a
[> To enaog circuits
Function of each block:
MAIN CPU — Controls keys and switches scanning, sequencer, MIDI and cassette tape
player.
SUB-CPU — Mainly controls Music LSIs.
CPU Interface — interfaces between MAIN CPU and SUB-CPU,
Main RAM 1 — The first 2K bytes are for system execution and the rest of 6K bytes store
the sequencer data,
Main RAM2 — Stores the sequencer data.
Sub-RAM1 —— Having 2K-byte capacity, stores tone data for Memory Banks A and 8.
Sub-RAM2 _ — System execution area
Sub-RAM3. — Stores data fro Memory Banks Cand D. MAIN CPU (uPD7811-180)
PIN NO.| TERMINAL NAME | IN/OUT | FUNCTION
1~8 | PAO(S)~PA7(S7) | IN/OUT | Data bus for LCD and RAM pack. PAO~PAS also
generate key common signals.
P80 (SYNC) IN | Synchronous signal from CPU Interface
(MB64H173)
Bt (MT-0) OUT | Serial data output for cassette tape
" PB2 (INT) ‘OUT | SUB-CPU interrupt signal
12 PB (CONT) | IN/OUT | Control signal between MAIN and SUB-CPUS
13 PB4 (MT/0) | OUT | Remote control (start, stop) signal for cassette
tape recorder
14 PBB (B5) OUT | LCD unit control signal
15 BG (86) OUT | LCD Driver LSI chip select signal
16 P87 (87) OUT | LCD Driver LSI Readirte signal
"7 PCO(M.OUT) | OUT | MIDI (Musical Instrument Digital Interface)
data output
18 PCI (M-IN) IN | MIDI data input
19 P02 (Ce) OUT | RAM Pack (option) chip select signal
20 C3 (MT-I) IN. | Data input from cassette tape
21~24| PCA~ PCT OUT | Metronome (timing signal for music recording)
pitch signals
26 INTt IN | Interrupt from SUB-CPU.
28 RESET IN | Initializes the LSI’s internal circuits at Power ON.
31 x1 IN| 12MHz clock pulse
32 vss IN | Losic ground (OV) source
33 VSS. IN| Ground for the builtin ADC (Analog to Digital
Converter)
34 ‘ANO IN. | Bender wheel input. A voltage from the bender
wheel is converted into digital data by a builtin
ADC.
35 ANT IN| Modulator wheel input. A voltage from the
‘modulator whee! is converted into digital data by
a builtin ADC.
42 VREF IN _ | Reference voltage (+5V) for the builtin ADCs IN | +5V power souree for the built-in ADCs
OUT | Read signal. Drops to "L” when MAIN CPU
‘reads data from the ROM and the RAMS,
WR OUT | Write signal. Drops to “L” when MAIN CPU.
writes data into the RAMs,
ALE OUT | Address Latch Enable. When “H, data bus
DO ~ D7 becomes address bus AO ~ A7.
47 ~ 54] PFO(A8)~PF7(A15) | OUT | Upper address bus (A8 ~ A15)
85 ~ 62| PDO(D0)~PD7(07) | IN/OUT | Data bus (D0 ~ 07)
63, 64 | vop, vec IN | 45V power source
‘SUB-CPU (uPD7811-204)
PIN NO. | TERMINAL NAME J IN/OUT] FUNCTION
1~8 | PAO(LO)~PA7(L7) | OUT | LED drive signals
9 PBO IN| Data receive request from Master Music LSI
10 Pet IN | Data receive request from Slave Music LSI
" Pez OUT | Master Music LSI chip select signal
12 Pas OUT | Slave Music LSI chip select signal
13 Pea OUT | Write enable signal for Music LSIs
4 PBS OUT | 1D (Interrupt Disable) signal.
‘When SUB-CPU is busy, it sends ID signal to
‘Music LSIs s0 as not to be interrupted.
15 PB6 (LOC) | OUT | Stays "H level for approximately 830 milli-
seconds after the power switch is turned on in
order to avoid mistlighting the LEDs at Power
ON.
17_| Pco (TxD, L11) OUT | LED ative signal
18 | PCI(RXD,SYNC) | IN | Synchronous signal from MAIN CPU.
19 | PC2(SCK, CONT) | IN/OUT | Control signal between MAIN and SUB-CPUs
20 | Pc3(INT2) IN| Interrupt signal from Music LSis
21 | Pca (To) OUT | Metronome envelope signal
22~24 | Pes(La)~Pc7(L10) | OUT | LED drive signals
26 INT1 IN| Interrupt signal from MAIN CPU.
=a 28 RESET IN] AtPower ON, the terminal stays "L” level for a
while in order to initialize the internal circuits.
3 xt IN| 12MHz clock pulse
32 vss IN | Ground (OV) power source
44 RD OUT | Read signal. Drops to ““L"* when SUB-CPU reads
| data from the ROM, RAMs or Music LSIs.
45 wR ignal. Drops to "'L" when SUB-CPU writes
data into the RAMs or Music LSis.
46 ALE OUT | Address Latch Enable.
When "H", data bus PD9 (DSO) ~ PD7 (DS7)
becomes address bus ASO ~ AS7.
47~54 | PFO(ASIS) OUT | Upper address bus
~ PF7 (ASB)
85~62 | PDO(DSO) OUT | Data bus
~ Pb? (DS7)
63,64 vop, vec IN | #5V power source 9. MAIN RAMS & ROM ACCESS
ln
cc 8
ls Be
MAIN CPU 4O7811-180
‘The first 2K bytes of Main RAM T are the data area for system execution and. the rest of 6K bytes.
and the whole BK bytes of Main RAM 2 are the data area for programmed music,
‘The capacity of Main ROM is 32K bytes and contains the program for system execution.
‘The lower address bus AO ~ 7 is provided from CPU Interface LSI. When signal ALE from
MAIN CPU rises to “H, data bus (D0 ~ D7) becomes address bus (AO ~ A7} in CPU interface
LSI. The upper address AB ~ A15 is directly supplied from MAIN CPU.
Chip select signals are provided from signals A13~ ATS:
“us199, "8198 FUNCTION TABLE
‘A13] 14] AS sae
L | L |H [Main RANT chip selection TENABLE | SELECT
‘Main RAM? chip selection a
ourrur
X_|X | L_| Main ROM chip selection |
zazErerexxio
zaezessrea|g
xezrzszzzz|§
exzzzzezzz|$
‘Gi=G2A GIB
hip eas Clow lvl, een
-26- 10. SUB-RAMS & ROM ACCESS
Swann
SUB.CPU 4P07811.20¢
TC5BIGAP is a 2K-byte RAM while HN61364P is an BK-byte ROM.
‘Sub-RAM 1 — Tone data area for Memory Banks A and B.
Sub-RAM 2 — Data area for system execution.
Sub-RAM 3 — Tone data area for Memory Banks Cand D.
In the same procedures as for MAIN CPU, lower address bus ASO ~ AS7 is generated from data
‘bus DSO ~ DS7 in CPU Interface LSI when signal ALE is “1. Upper address signals AB ~ A15
are provided from SUB-CPU directly.
Decoder 74L$138-2 generates chip selection signals and other control signals from signals AS11
~ ASI6 as follows:
oI or
vaisice ——_[aalarslatlaralan fo] vi [va [va [va] ve [ve] v7
wsfer vo—al ela le fete elm [awl la || | wre orn
es ee pr CC CC CR
room erste pete farte peter effet | paseo SHO
anda top pe bp aac pape aL fost MN SF UEORT
aie we [w fw pw [wm [He [H | | Sub RAM2 chip selection
PE Twa befor wt So ANT pon
web [w Deep TD LC [RA cb ctor 11. MUSIC LsIS ACCESS
(62-5000 employs two Music LSis, Master LS! and Slave LSI, which are controlled by SUB.CPU.
Master US1
SUB-CPU uPD7811-204
(1) SUB _CPUcDMusie LSI
reer |i st cto tes — af
ATE i tt hf
SUR-CPO ws ta ning
‘yo war ¢ f
5 recing sts tam PROP
(2) Musie LSI = suB-cPu “deciinates wed US vents
roe ROT. ein cru
‘Upon cit of an nore a
752 PTT
UCP red tam the MeL 12. CPU INTERFACE (MB64H173)
orFisvnc)
1 (FT)
om 5
102 | aay
oe |
uoe [ai
10s
108
or 4
‘tos tate)
m0 5
(21820. ar
a2
00
ou fon
as
ae
cans
rer 1010
o20, rea (ais
et
toon | 822 oon
vf aes
on co 3
os, vex
a tox | 10)
7 eee ET
wie teu | 5)
out0, ‘eas
out
aso} our 1c 5
1 fou Teno
tasn | ove wa Ly
ous veo [oxi
ure rou
a7 oe
(ates FIG.
-20- FIL =
Decoder 1
Latch 1
Latch 2
Latch 3
Latch 4
Lateh 5
Funetion of Each Block
‘Set by the clock pulse ’O" and signal R2 from SUB-CPU, and generates signal SYNC.
which synchronizes MAIN and SUB-CPUs.
FUNCTION TABLE
[preser —ciean _etocx
x
— Generates clock pulses for the latches from signals AO ~ A3, A14, A15, RD
and WR
tunes | secegr
nour | input ourrur
v2 va ve V6
&
K
+82 = Ga +8
= Converts MAIN CPU's deta bus (00 ~ D7) into address bus AO ~ AZ, and
‘generates clock pulses ‘0’ ~ 6°.
= For the data transfer from MAIN CPU to SUB-CPU.
— Transfers the data from the pitch bender and modulator wheel to SUB-CPU.
— For the data transfer from SUB-CPU to MAIN CPU.
= Converts SUB-CPU's data bus (DSO ~ DS7) into address bus ASO ~ AS7.
FUNCTION TABLE (EACH LATCH) FUNCTION TABLE: (EACH FLIP-FLOP)
ENABLEE a BE ux,
a
nerslo
t
t
Latah Vand 5 Lath? ~ 4 12.2. Data Transfer Procedures
Mpeainn73
I
'
+f
sus.ceu i { MAIN CPU.
. u
ate 1
i
3)
iz
Decoder 1
<2 WT
Latch
2-3]
Gebel caine so se
roe
> en | 74181962
ot
adit
antag Decoders SF—> Az
TaLS382
at (1) eh ender & Modlatrt> SUB-CPU
© Voltage level from the pitch bender or the modulator is converted into digital dat inthe
CPUs builtin ADC (Ansiog to Digital Converter) and output frm data bus (00 ~ 07),
@ The dats entered into CFU Interface LS.
® sending signal R1, SUB-CPU sets Latch 3 and reads data periodically.
(2) MAIN cpu > suB-cpU
© Via Latch 1 and Decoder 1; MAIN CPU drop lock pulse 0 o “Lee
BY clock pulse 0, F/F 1 is preset to rise signal SYNC.
@ Main cPU puts data on data bus DO ~ D7, and atthe same time, clock pulse
“level
At the rising edge of clock pulse “ from MAIN CPU js set in Latch 2.
d
@ Main cru interrupt SUB-CPU from terminal P82, and simultaneously generates
signal CONT from terminal PBS
@ Generating signal R2 from Decoder 3, SUB-CPU reads the data from Latch 2via data bus
s0~ 087.
(© SUB-CPU sends signal ACK to MAIN CPU via Decoder 3 and F/F 2.
Upon receipt of signal ACK, MAIN CPU confirms that SUB.CPU hes recaved the data
and generates signal 616 in Decoder 2.
© When athe deta have sent to SUB-CPU by repeating the above procedures @)~ @)
MAIN CPU drops signal CONT to
Confirming that both CONT and SYNC are “L”, SUB-CPU determines that all the date
hhave been received.
main course [7] N M1
= )
5
gonT. (3) suocru C>MAIN PU.
© inthe same procedures as stated in the item (2), MAIN CPU sends “Request Command”
that inquires SUB-CPU to transmit data
@® Ue.cPu puts data on the data bus DSO ~ DS7 andl sts the detain Letch 4 by signal
W1. SUB-CPU then presets F/F 2 by pulse 64, causing signal ACK to be entered in MAIN,
cru.
® Acknowledging that the data is set in Latch 4 by signal ACK, MAIN CPU generates clock
pulse ‘2’, eausng the data from SUB-CPU to be put on MAIN CPU data bus D0 ~ D7.
‘After receiving the deta, MAIN CPU sends SUB-CPU an interrupt signal from terminal
P82, and by the interrupt signal, SUB-CPU confirms thatthe data is received by MAIN
cru.
© Repeating the above procedures @)~ @, SUB-CPU sends the next data to MAIN CPU.
=a (4) Key and switch scanning
inates 2 key or a switch
Receiving a key common signal from data bus, MAIN CPU diser
input.
© From signals PAO~ PAB of MAIN CPU, Aneto 16ne decoder 74L8164P.1 generates
key common signals KCO ~ KC14,
® nena key ora switch is hit, one ofthe input signals KIO~ KIS (for keys) or KI10~
15 (for switches) i entered in CPU Interface MBG4H173,
@ MAIN CPU generates the clock pulse '3' (for keys) or ‘4’ (for switches), causing the
tristate butters to be opened
® Tre input pulses entre io data bus,
MAIN CPU determines which key is hit.
© Discriminating the ecntons of the deta Gus
‘ourrur
7ALS154P Function Table 13. KEY MATRIX
au: | Kee
tress —[weiony —fwavont henry
seo | c | ore | 02 | om |e nunca | veanee. |" aaec:| " baneD
TONE | TONE ‘PRESET PRESET
ech | eve | ce | ome | Ma) aad ove: | to ag | Ome
ee eS Tone | you | Tone | Tone
2 | : ? ; 7
ENV STEP ENV POINT |ENVPOINT | VALUE ‘VALUE
Kee | | Oe | aay cow SUSTAIN) ENO | YSAVE ‘4 LOAD
ea | cr fom | oe | om [es |e | woo. perm ‘que’ [rontanenro| wr | eanrmioge
| |
wes | em [oe fom | al | am | ov | iwitinuee vienaro ME | ming | Nose
0651, )00 |, [news = lows Joan Loca
eee oe pre: a WAVEFORM ENV ‘KEVF ENV KEY ENV
Boe FOB Sloe soos oR ONT
ye ee Se Ae Ae WAVEFORM ENV KEVF ENV KEY ENV
Tce Tae rene
xce | c | ow | os,| ow |e | re | TAK | nerear ("eNO |TEWO | oeuere | perune
wo bem bee fom [oe [am Pew [THER | RRR taaee RAG [Tana] THA
RE THAER NEES TAAGK | TRESS] TRAE
«cio | C7 RESET, RECORD | MANUAL | REAL TIME ‘3 2
Baga RY] EMORY] FOOT
eb Ba] PPE Raa Latimer lean
By MODULATION
one I ON/OFF
i m3 TONE ‘KEY
cia @ | norma | TORE | EY | sequencer] sovo | mio
rorranentol euioe | _ wey | waste | Goupane)
isc ON/OFF ON/OFF | TRANSPOSE, TUNE RECALL eae
a rho eve tac se
Som oe toa ete
sae
oa
—
=
i
baer
Tivo
a
Td
cunt
=
=
Lee
voL2
NORMAL,
ea
ee
a
0.
paneer At
lo of Q efoe teint
‘hatte ngs Conlon ae
tines
4 = vanain rm om 0 nigh ee
‘CoAT
ae
|z454|
zg]
7ausi74
FUNCTION ARLE
(GACH FLIP FLOM)
TNT
LEAR clock 0] a Gt
74LS154P
FUNCTION TABLE
level.
‘Then, MAIN CPU generates clock signal
17 from signals AO ~ A3.
4 generates signals 617 ~ 919 and p1A~
1D which set Latches 5~ 11,
For lighting the LED NORMAL”, MAIN
(CPU raises signal DO which is inverted to
Combining the signals AO ~ A3, Decoder
DO (=""L") is set in Latch 5 dropping
signal L70
‘The LED “NORMAL” is lit when its
‘anode is connected to VDL? (+5V).
14. LED DRIVING CIRCUITS
high le = low lea, X= aoa ue aes te0 ea eva EET
18 - 6 tee PRESET BANK A, tfefefe
reap ——2 Jp vy 28° Tpraser oan cpe eye
cr] ude spo | paeser saNKe rt tete
co] rn ian By: rs PRESET BANK O cpt pete
zm 3 y4[ tumor panic chepe pe
3 vi Lo MEMORY BANK cheb be
s ee
z ou
San onan
& cm sau oun opapS To
S PF JA A Yo} Sa tye fete
Boas sv oi tpepe pe
ie us
’ le, va cp paye
tar] —2 Joan va ——* TLE pep
or ar chee pe
vector vs ce pepe
7) ate. treat
bag nat
ce earee on spare ye
s|- 32 oor er cc
a cs ‘Dewi KEY FOLLOW } tfheyate
4] woe DCAI KEY FOLLOW tleteye
5 ae. ‘CAT ENV Gc
rc) vo 0602 WAVEFORM tfelee
a che pe pr
ad Do0d KEY FOLLOW wpe Tee
z 9 AN? ‘Dew? ENV wie jel
ao] pt 10] Aya ‘DCA? KEY FOLLOW wiieyaye
rasp isp 8 Toca ew wpe pepe
® uu apo TeRATS cs
if ss i
vot
‘These LEDs are controlled by SUB-CPU.
For example, when SUB-CPU wishes to light the “PRESET BANK-A” LEO, it drops all the signals
LB~ L11. YO output of Decoder 5 drops to “L", causing the LED to be lit.
=e 15, ANALOG CIRCUIT BLOCK DIAGRAM
Master
Muse “| __
ust 01~003 SH
Sample
pos Expander 5
bors} PAC Fn FF) Atala
Giruit
San. Joo1~pos SH
Music
ts!
‘Master and Slave Music LSIs provide 12-bit digital sounds for DAC (Digital to Analog Converter)
By means of time sharing, DAC mixes the two different signals and converts into analog waveforms.
‘To obtain a wide dynamic range of the amplitude, Music LSIs' outputs are contracted and are
reformed into a proper waveform shape by Expander circuits. Sample & Hold circuit removes a
high frequency noise called as glitch contained in the DAC output,
‘Sample & Hold Circuit also separates the Master and Slave waveforms. 16.
MUSIC LSI (uPD933)
PIN NO. | TERMINAL NAME | IN/OUT | FUNCTION
1~8 B7 ~ 080 IN/OUT | Bit data bus between Music LSIs end
sua-CPU
9 S IN | Chip select terminal. At“L”, the LSI is
designated by SUB-CPU.
10 IN| Read deta terminal, At "L" the LSI sends
data to SUB-CPU.
Wn WE IN | Write enable terminal. At “L”, the LSI
receives data from SUB-CPU.
12 ws IN Write strobe terminal, SUB-CPU writes data
into Music LSI at the rising edge of the signal.
16 wis IN ‘Master or Slave determination terminal.
When “L", the LSI becomes Slave LSI while
itbecomes Master LSI when the terminalis
ae
17 SY _| IN/OUT | Synchronous signal input/output terminal.
‘The synchronous signal is sent from Master
LSI to Slave LSI
18 CLK IN| 4.48MbH2 clock pulse input
2 RST IN | Reset signal input. Normaliy the terminal
stays"L". At power ON, the terminal rises
10"H" level for a while and the internal
circuits of the LSI are initialized.
2 DOE IN/OUT | Data output enable terminal. At “H, digital
sound signals are output from Master LSI
while Slave LSI outputs sound signal at "L"
level
2B si OUT | 40KH2 sampling signal for Sample & Hold
cireuit
25~27 DO1~ Dos: OUT | Control signals for Expander circuit
28~ 39 D04~ DOI5, OUT | 12-bit digital sound signals
40 voo IN| _+5V power source 17. DAC (Digital to Analog Converter)
‘The two Music LSIs output different waveforms. When signal DOE is
'8 waveform while Slave LSI outputs a waveform at "L” level of DOE.
Master LSI outputs
vac (+5V)
To Expander
Circuit
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coe TTF LILI
en
Slave Ls!
Out] ahaa
Slave waveform
Mester wavetorm
-40- 18, EXPANDER CIRCUIT
In order to extend the dynamic range of the melody signal, a part of DAC output waveform is
contracted and expanded by Expander Circuit.
espana
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From DAC IN:
our
From Musi LSte
2
ae
«| ane:
In accordance with the voltage levels of the signals DO1, 002 and DO, one of the input
channels is turned on.
By the resistors connected to each channel, the amplitude of DAC output varies from 1 to
116,
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re.
psctnnn a Se cy
Combined resistances at each point are
ra = R1 (BKO) +A2 (SKN) = 10K
0 = Parallel connected ra (10K) and R3 (10K)
(6 ~ rh (SKM) + RA (KM) = 10K.
rd Parallel connected re (10K) and RS (10K) = SKS
re ~1d (5KQ) + RO (SKM) = 10K.
f= Parallel connected re (1OKQ) and R7 (10KA2)= SK
rg “rf (5KQ) +R (GK) = 10K.
=5Ka,
Each cutrent value i
be nena
ints 12 +122
ats 131 +132
Name, 111= 1/2
iti
Ws 1212= 18
Voltage level st each channel
(@hannel O: rg x 1 = TOKE |
(Channel 1: rex 111 = 10KD2 x U2
Channel 2: rex 121 = 10K x 4
Chane! 3: rax 191 = 10K x 1/8
Channel 4: RY 131 = BKA x 1/8= 10K x 118
input voltage is €:
(Channel 0 input voltage i E
Channel 1 input voltage ie €/2.
Channel 2 input voltage is E/4
Chance! 3 input voltage i E/8
‘Channa 4 input voltage is E/16.
‘Thus, output of DAC is expanded in accordance with the voltage levels of signals DO1, 002
and 003.
we 19, SAMPLE & HOLD CIRCUIT
‘Toto
w>—t
Signal SH from,
Slave LSh
The block eliminates a high frequency noise called as “Glitch” which appears at the end of the
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— :
a
When signal SH from Master LSI is "H", the
‘switch X in T4083 is contacted with the
terminal OX. This causes the input signal to
pass through, At this time, the voltage level
‘of the waveform is charged in the Hold
Capacitor.
On the other hand, while a glitch appears on
‘the waveform, the switch X is contacted with
the terminal IX. This results in cutting off
the glitch. Although no signal comes out of
‘C4053, the input of the opamp keeps the
‘same voltage level by discharging of the Hold
Capacitor.
‘Sampling or holding the slave waveform is
performed by the same procedures using
signal SH from Slave LSI and switch Z. 20. STEREO CHORUS CIRCUIT
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is Lapel
Function of Each Block:
Filter A
Filter 8
Compressor
‘Three-Phase LFOs
vos
BBDs
Filter ©
Expander
— Smoothes the stepped waveform of Samle & Hold Circuit output signal.
— As the BBD does not pass signals which exceed 20KHz, this block is 8
low-pass filter whose cutoff frequency is 20K Hz.
= Inaccordance with input signal level, this block controls the amplitude,
When the input signal is small, the circuit amplifies the signal whereas
‘the amplitude becomes smaller when the input isa large-level waveform.
‘The block is used for reducing the noise
= Generates low-frequency triangle signals of 0.6442 and 6.1H2,
‘The three outputs differ 120 degrees in phase.
— Voltage Controlled Oscillator which generates the clock pulses for the
BBDs. Their oscillation frequencies vary in accordance with the input
voltage level.
= Bucket Brigade Device. Stereo chorus effect is given by delaying the
right or the left sound.
— Since the output signal of the BED carries @ noise caused by elock pulses,
the filter removes the noise,
— Functions contrary to the Compressor. This circuit is also used for
reducing the ni 20-1. Three-Phase LFO (Low Frequency Oscillator)
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jon frequency is
The following shows the actual circuit of the Three-Phase LFO. The time lag is controlled by
the parallel connected capacitor and the resistors.
Model €Z-5000 employs two LFOs whose oscillation frequencies are 0.54Hz and 6.1Hz.
The output differs 120 degrees in phase.
Both 0.54Hz and 6.1 Hz triangle waveforms are mixed to give variational delays of the sound in
180K 5
racks ofS
ite .
cave Ae
‘The 0.54 Hz and 6.1 Hz waveforms are mixed in the ratio of 10:1 as they pass through 18Kohm
and 180Kohm resistors, respectively.
=45- 20-2. VCO (Voltage Controlled Oscillator)
‘The VCO is an oscillator whose oscillation frequency
varies in accordance with the input voltage level.
AIN
> ‘OUT nthe left figure, the voltage levels of the A-OUT and
the B-OUT are opposite.
i (1) When A-OUT is “H”, BOUT drops t0 "L".
ES (2) From A-OUT, electric current flows into B-IN via a
2 oly the A-IN voltage gradually rises,
aour>—th BIN
<__Threthola
AN level AB
a.
Aout sout>¥ ALIN
“- e N t
7
ein
(3) When B-IN becomes lower than the threshold level,
B-OUT rises to “H”.
When A-IN becomes higher than the threshold level,
A.OUT drops to”
(4) The circuit oscillates repeating the above operations.
sour
The following shows the actual circuit of VCO. When control terminal @) is GND (zero vol), i
takes approximately 15 microseconds forthe diferentaton circu to rech the threshold
vohtage
—w
Fram veo: [i> sour
Tenld
he
ePaon
FT.
f>—L. sour
— 48 - When the voltage of (A)is 2 volts, it takes only 9 microseconds to reach the threshold level.
‘Theothold level
ws!
GND» |
‘As VCO receives a triangle waveform from the Three-Phase LFO, it oscillates from 55.6 KHz to
33.3 KHz in accordance with the voltage level of LFO output.
20:3. BBD (Bucket Brigade Device)
bap
Clock
‘The BBD contains serial-connected delay elements. The input signal is shifted one step per one
‘clock pulse.
‘The clock pulse is generated in the VCO, and as it varies from 33.3KH2 to 55.
6KHz, the delay
time varies.
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‘Model C2-5000 employs three BBDs in order to give better stereo effect.
-a- 204. Compressor and Expander Circuits
| a sound signal passes through the BBD, a noise is carried on the signal especially when the
input level of the signal is low.
Lem iw JH |
+ When the level of input signal is low, the amplitude is large.
|f the input level is high, the amplitude decreases.
When the level of input signla is low, the amplitude is small.
‘The amplitude increases when the input level is high.
Taput Level
When a low signal does not pass through the Compressor and the Expander;
ZOD NR ee PP
a ee
When a low signal passes through the Compressor and the Expander;
Sepa ae 2
Noise
‘Thus, the S/N ratio of the circuit is heightened.
—48- 21. VOLUME CONTROL CIRCUIT
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1“ .
To
Powar Amp NuI13600
Electric current from pedal and main volume controls are amplified by transistors T4 and 73,
respectively, and become the base current of transistor T2. Collector current of T2 is applied
‘to NM13600's contro! terminals.
NJM13600 is a power amplifier with control terminals.
In accordance with the amount of the current applied to pins 1 and 16, the amplitude of the
amplifier varies. 22. RESET CIRCUIT
eae CE2 for Sub RAMs:
CEP tor Main RAMs
ast erates 23. MIDI & MT INTERFACE CIRCUITS
23-1, MIDI Interface Circuit
MIDI (Musical instrument Digital Interface) is an international standard for the external control
of electronic musical instruments. In other words, standardized input and output terminals are
‘equipped with musical instruments, rhythm machines, sequencers, etc. end the music information
which the machines send and receive via these terminals is made compatible by certain formatting.
‘This standard enables @ musical instrument to connect, synchronize, and sequence (memorize) to
‘other models and even to other brands,
woo
7811-180
MAIN CPU
Mibrour:
