0% found this document useful (0 votes)
66 views

ECE 213 Unit 2

The document discusses logic gates and Boolean algebra. It defines logic gates such as AND, OR, NOT, NAND, NOR, XOR, and XNOR. It explains how digital systems are constructed using logic gates and how logic gates are represented using truth tables. It also discusses Boolean algebra concepts like simplification using laws of commutation, association, distribution, De Morgan's laws, and conversion between sum of products and product of sums forms. Karnaugh maps are introduced as a method to simplify Boolean functions graphically.

Uploaded by

Bindu Vanga
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
66 views

ECE 213 Unit 2

The document discusses logic gates and Boolean algebra. It defines logic gates such as AND, OR, NOT, NAND, NOR, XOR, and XNOR. It explains how digital systems are constructed using logic gates and how logic gates are represented using truth tables. It also discusses Boolean algebra concepts like simplification using laws of commutation, association, distribution, De Morgan's laws, and conversion between sum of products and product of sums forms. Karnaugh maps are introduced as a method to simplify Boolean functions graphically.

Uploaded by

Bindu Vanga
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 37

LOGIC GATE

Boolean Algebra
Simplification
SOP-POS/Minterm-Maxterm
K-Map
Logic Gate
 Digital systems are said to be constructed by using logic gates.
 These gates are the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates.
 The basic operations are described below with the aid of truth tables
 Truth tables are used to help show the function of a logic gate

 Boolean functions practically implemented by using electronic gates

 Generally logic gate have 2 input 1 output


 Gate INPUTS are driven by voltages having two nominal values,
 0V logic 0 and 5V logic 1
 The OUTPUT of a gate provides two nominal values of voltage only
 0V logic 0 and 5V logic 1
Logic Gate
AND gate OR gate NOT gate

produces an inverted
high output (1) if one or version of the input at its
high output (1) only if all its more of its inputs are high.
inputs are high output.
Logic Gate
NAND GATE NOR GATE

AND gate followed by a NOT gate. OR gate followed by a NOT gate.

Low output (0) if one or


high output (1) only if all its more of its inputs are high.
inputs are low

NAND and NOR gates are called universal


Logic Gate
EXOR GATE/XOR EXNOR GATE/XNOR

high output (1) for different


input High output (1) for same
input
MULTI-INPUT LOGIC GATES
Practice Questions
Which of the following symbols represents a NOR gate?

Which one of the following truth tables represents the behavior a NAND gate?
Practice Questions

What type of logic gate does


this symbol represent?

What type of logic gate's


behavior does this truth table
represent?
Practice Questions
The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.

A. A = 1, B = 1, C = 0
B. A = 0, B = 0, C = 0
C. A = 1, B = 1, C = 1
D. A = 1, B = 0, C = 1
If the input to a NOT gate is A and the output is X, then ________.

A. X=A
B. X=~A
C. X=0
D. none of the above
How many inputs of a four-input AND gate must be HIGH in order for the output of
the logic gate to go HIGH?

A. any one of the inputs


B. any two of the inputs
C. any three of the inputs
D. all four inputs
Practice Questions
Which of the following gates is described by the expression ~(ABCD)
A. OR
B. AND
C. NOR
D. NAND
Circuit with Logic Gate
AB

AB  B  C
C

X Y

X
XY
Circuit with Logic Gate
A AB

AB  AB

AB
B

A B

( A  B )  BC

BC
Circuit with Logic Gate
AB
AB  C
C ( AB  C ). D

( AB  C ). D

Draw circuit for Y  AB  AC


Boolean Algebra
Analyze and simplify the digital (logic) circuits
Variable used can have only two values. Binary 1 for HIGH and Binary 0 for LOW

Commutative law

Associative law

Distributive law

AND law

OR law

INVERSION law
De Morgan Law
Simplification
Simplify C  BC
C  (B  C)
(C  C )   B 
1 B
1

Simplify F  ABC  A  ABC


AC ( B  B )  A
AC  A
A(C  1)
A
Simplification
Simplify F  ( A  B )  ( A  C )
 ( A  A)  B  C
 A B C

Pr ove that x  xy  x
x(1  y )  x
xx
Simplification
Simplify ( A  B  C )
A.B.C

Simplify and implement with min imum


number log ic gate
F  AB  BC ( B  C )
 AB  BC.B  BC.C
 AB  BC  BC
 AB  BC
 B( A  C )
Simplify and implement with minimum number of logic gates

Y  ABC  ABC  ABC  ABC


 C ( AB  AB)  AB(C  C )
 C ( A  B)  AB
Logic Gate Implement with NAND-NOR
SOP-POS
Boolean function is an algebraic form of Boolean expression

Sum-of-Products (SOP) - variables are operated by AND (product) are OR(sum) together
Product-of-sums (POS) - variables are operated by OR (sum) are AND (product) together

SOP Expression
Write AND term for each input combination produces HIGH
Write the input variables for 1 and compliment for 0.
OR the AND terms to obtain the output function.

F(SOP) = A’BC + AB’C + ABC ‘ + ABC

POS Expression

Write OR term for each input combination produces LOW


Write the input variables for 0 and complement for 1
AND the OR terms to obtain the output function

F(POS)= F = (A + B + C) (A + B + C ‘) (A + B’ + C) (A’ + B + C)

POS is compliment of SOP


Min Term –Max Term

Write SOP exp ression for min term F ( A, B, C )   m(1, 2,3)


In binary 01 10 11
 AB  AB  AB

Write POS exp ression for min term F ( A, B, C )   M (1, 2,3)


In binary  01 10 11
( A  B).( A  B).( A  B)
Write SOP exp ression for min term F ( A, B )   m(1, 2,3)
In binary 01 10 11
 AB  AB  AB

Write SOP exp ression for F ( A, B, C )   m(2, 4, 6, 7)


In binary 010 100 110 111
ABC  ABC  ABC  ABC
Write SOP exp ression for F ( A, B, C )   m(0,1,3,5)

Write SOP exp ression for F ( A, B, C , D )   m(2, 4,5, 7,8,9,10,13,15)


SOP-POS Conversion
Polling Questions
How many gates are required to realize Y = CD + EF

A) 2 AND 1 OR
B) 1 AND 2 OR

Which of following are known as universal gates?

A) NAND & NOR


B) AND & OR

The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH

A) AND
B) OR

Which of the following equations would accurately describe a 4-input OR gate when A = 1, B = 1,
C = 0 and D = 0

A) 1 + 1 + 0 + 0 = 1
B) 1 + 1 + 0 + 0 = 0
A small circle on the output of a logic gate is used to represent

A) NOT
B) BUF

Output will be a LOW for any case when one or more inputs are zero

A) AND
B) OR

3 input gate contains ___ number of entries in truth table


A) 8
B) 7

How many two-input AND and OR gates are required to realize Y = CD+EF+G
A) 2,3
B) 2,2

XOR output is high, if inputs are


A) Different
B) Same
Which is XNOR gate equation
A) AB +(~A)(~B)
B) ~AB + A(~B)

If one input of XOR gate is connected to high terminal, equivalent to


A) NOT
B) BUF

Compliment of XOR is
A) XNOR
B) XOR

Which is not correct


A) A.1=1
B) A+A=A
C) A+1=1
D) A.A=A

(A+B)(C+D) present
A) 2 OR gate ANDed
B) 2 AND gate ORed
POS is compliment of SOP
A) True
B) False

min term when x=0, y=0 and z=1


A) x'y'z
B) x+y+z’

number of max terms for an expression comprising of 3 variables?


A) 8
B) 3

Y=AB+BC+AC is
A) SOP
B) POS

Y=(A+B)(B+C)(C+A) shows
A) POS
B) SOP
KMAP
Karnaugh map is a tool for simplification of Boolean algebra
K-Map diagram is made up of squares
K-map is a graphical representation of SOP (Minterm)
K-Map extensively reduce the calculation and provides best minimized solution
K-map solve the expression with grouping of neighbor cells

3 variable
2 variable
3 variable
4 variable
Kmap Simplification Rule

1) Construct kmap and place 1’s in the squares according to the truth
table.
2) Groupings can contain only 1s
3) Groups can be formed only at right angles; diagonal groups are not
allowed.
4) The number of 1’s in a group must be a power of 2
5) The groups must be made as large as possible.
6) Groups can overlap and wrap around the sides of the Kmap.
7) Every group puts a term in the solution

Optimized Solution
Minimum number of group
Each group covers maximum possible squares
Kmap with Don’t Care
In a Kmap, a don’t care condition is identified by an X in the cell of the
minterm(s)
In simplification, we are free to include or ignore the X’s when creating our
groups.
X Z WZ

F(ABCD)=π(0,1,3) . d(5,7)

You might also like