BITS Pilani

BITS Pilani Sindhu S

EEE
Pilani Campus
MELZG 611
IC Fabrication Technology
Lecture No.1
Date . 24/07/2021
Contact Hour List of Topic Title Topic # References
(from content structure in Part A) (from content structure in (Chap/Sec)(Text
Part A) Book)
1 History and Development Crystal Structure and basics , T1 , R1
Crystal structure and basics .Concepts of Crystal Clean room
structure, Miller indices, orientation, defects. .
Introduction to clean room, Clean room basics, Clean
room attire, Standards of cleanrooms

2 Crystallography and crystal structure of Silicon, Crystal Crystal Growth and wafer T1
growth techniques preparation

Czochralski and FZ growth methods,

Wafer preparation and specifications, SOI wafer
manufacturing
3-4 Photolithography, Light sources, Wafer exposure Lithography processing 3.5
systems, Photoresists, Baking and development, Mask
making, Measurement of mask features and defects,
resist patterns and etched features

5-6 Chemical and physical vapour deposition,epitaxial Thin film deposition and epitaxy T2
growth, manufacturing methods and systems,
deposition of dielectrics and metals commonly used in
VLSI,Epitaxial process of Silicon wafers,Molecular
Beam epitaxy, Thin film characterization techniques.
 7 Types of oxidation, Thermal Oxidation, D-G Oxidation T3
model, dopant distribution in oxide layer,
growth of oxide layer. Wet and Dry oxidation,
growth kinetics and models, defects,
measurement methods and characterization.

8 Models for diffused layers, Characterization methods, Diffusion T7

Segregation, Interfacial dopant pileup, oxidation
enhanced diffusion, dopant-defect interaction. (4
lectures)

9 Basic concepts, High energy and ultralow energy Ion Implantation T7

implantation, shallow junction formation & modeling,
Electronic stopping, Damage production and annealing,
RTA Process & dopant activation. Channeling

10 Different types of etching, dry etching, wet etching, Etching T5

plasma etching, etching of materials using vlsi,
modelling of etching
11 Aluminium metallization, Copper metallization, Metallization T8
contacts, interconnects, multilevel interconnects

12 Chemical Mechanical Planarization process, Planarization T8

electrochemical mechanical planarization
13 Yield and reliability, bath tub curve yield T12
14-15 Assembly and packing Assembly and packing T13
INTRODUCTION
It is not sufficient any longer to think a silicon oxidation simply a chetmical reaction between
silicon and oxygen that grows SiO2.
Today we must understand that detailed bonding between silicon and oxygen atoms and
kinetics that drive this reaction on atomic basis.
•10 µm – 1971
•6 µm – 1974
•3 µm – 1977
•1.5 µm – 1982
•1 µm – 1985
•800 nm – 1989
•600 nm – 1994
•350 nm – 1995
•250 nm – 1997
•180 nm – 1999
•130 nm – 2001
•90 nm – 2004
•65 nm – 2006
•45 nm – 2008
•32 nm – 2010
•22 nm – 2012
•14 nm – 2014
•10 nm – 2016–2017
•7 nm – 2018–2019
•5 nm – 2020–2021
 1

IC Fabrication Technology: Brief History

 1940s - setting the stage - the initial inventions that made integrated circuits
possible.

 In 1945, Bell Labs established a group to develop a semiconductor replacement for

the vacuum tube. The group led by William Shockley, included, John Bardeen,
Walter Brattain and others.

 In 1947 Bardeen and Brattain and Shockley succeeded in creating an amplifying

circuit utilizing a point-contact "transfer resistance" device that later became known
as a transistor.

 In 1951 Shockley developed the junction transistor, a more practical form of the
transistor.

 By 1954 the transistor was an essential component of the telephone system and the
transistor first appeared in hearing aids followed by radios.
 2

The transistor invented at Bell lab.in 1947

In 1956 the importance of the invention of the transistor by Bardeen, Brattain and Shockley was
recognized by the Nobel Prize in physics.
 3

1958 - Integrated circuit invented

September 12th 1958 Jack Kilby at
Texas instrument had built a simple
oscillator IC with five integrated
components (resistors, capacitors,
distributed capacitors and transistors)

In 2000 the importance of the IC was

recognized when Kilby shared the
Nobel prize in physics with two
others. Kilby was cited by the Nobel
committee "for his part in the
invention of the integrated circuit

a simple oscillator IC
 4
1959 - Planar technology invented

 Kilby's invention had a serious drawback, the

individual circuit elements were connected together
with gold wires making the circuit difficult to scale up
to any complexity.

 By late 1958 Jean Hoerni at Fairchild had developed a

structure with N and P junctions formed in silicon. Over
the junctions a thin layer of silicon dioxide was used as
an insulator and holes were etched open in the silicon
dioxide to connect to the junctions.

 In 1959, Robert Noyce also of Fairchild had the idea to

evaporate a thin metal layer over the circuits created by
Hoerni's process.

 The metal layer connected down to the junctions

through the holes in the silicon dioxide and was then
etched into a pattern to interconnect the circuit. Planar
technology set the stage for complex integrated circuits
and is the process used today.
Planar technology

Lecture #1
 6
1963 - CMOS invented
 Frank Wanlass at Fairchild Semiconductor originated and published the
idea of complementary-MOS (CMOS).

 It occurred to Wanlass that a complementary circuit of NMOS and

PMOS would draw very little current. Initially Wanlass tried to make a
monolithic solution, but eventually he was forced to prove the concept
with discrete devices.

 Enhancement mode NMOS transistors were not yet available and so

Wanlass was used a depletion mode device biased to the off-state.
 Amazingly CMOS shrank standby power by six orders of magnitude
over equivalent bipolar or PMOS logic gates.

 On June 18, 1963 Wanlass applied for a patent. On December 5th 1967
Wanlass was issued U.S. Patent # 3,356,858 for "Low Stand-By Power
Complementary Field Effect Circuitry".

 CMOS forms the basis of the vast majority of all high density ICs
manufactured today.

Lecture #1
 7

1965 - Moore's law

 In 1965 Gordon Moore, director of
research and development at Fairchild
Semiconductor wrote a paper for
Electronics entitled "Cramming more
components onto integrated circuits".

 In the paper Moore observed that "The

complexity for minimum component
cost has increased at a rate of roughly a
factor of two per year". This
observation became known as Moore's
law, the number of components per IC
double every year.

 Moore's law was later amended to, the

number of components per IC doubles
every 18 months.
 Moore's law hold to this day.
Lecture #1
 8

1971 - Microprocessor invented

 The combination of the Busicom (Japanese calculator
company) and the Intel came together and by 1971 the 4004 the
first 4-bit microprocessor was in production. The 4004
processor required roughly 2,300 transistors to implement,
used a silicon gate PMOS process with 10µm linewidths, had a
108KHz clock speed. In 1974 Intel introduced the 8080, the
first commercially successful microprocessor.

1972 - Intel 8008

 The 8008 was the 8 bit successor to the 4004 and was used in
the Mark-8 computer, one of the first home computers.

 The 8008 had 3,500 transistors, a 200kHz clock speed and a

15.2mm2 die size.

Lecture #1
16
17
18
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27
28
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33
“Moore’s Law”

The number of transistors that can be

integrated on a single IC grows
exponentially with time.

“Integration complexity doubles every two years”

Gordon Moore
Fairchild Corporation - 1965
 11

Visualizing Moore’s Law in Action (1971-2019)

Course Outline
 Introduction to VLSI
 IC process flow
 Crystal growth and silicon wafers
 Lithography
 Oxidation
 Diffusion
 Ion implantation
 Etching
 Planarization and metallization
 Yield and reliability
 Assembly and packaging

 SZE S. M., “VLSI TECHNOLOGY”

 WOLF S. & TAUBER R.N. , “SILICON PROCESSING FOR THE VLSI ERA”
 CAMPBELL S., “THE SCIENCE AND ENGINEERING OF MICROELECTRONICS
FABRICATION”
 MAY & SZE, “FUNDAMENTALS OF SEMICONDUCTOR FABRICATION”
Introduction to VLSI
 Very Large Scale Integration.
 Packing more devices into smaller areas.
 Applications: High performance computing,
Telecommunication, Consumer electronics, MEMS
etc.
 Integration of more functions provides:
 Compactness : less area/volume..
 Less power consumption.
 High reliability due to improved on-chip interconnect.
 Higher speed due to reduction in interconnection length.
 Cost saving.
Some terms to be familiarized..
 Technology:
 collection and ordering of unit processes for making a
useful product.
 Unit process:
 basic steps for construction. (Mechanical analogy: forging,
cutting, drilling welding etc.)
 Single crystalline
 Materials with same orientation of planes throughout the
crystal.
 Polycrystalline
 Materials with different orientation of planes in same
crystal.
 First Transistor

1947

First transistor (germanium), 1947

John Bardeen and Walter Brattain
Bell Laboratories
This is what
U and I C
in an IC
SSI/MSI/VLSI/ULSI
No of transistors per Chip Technology Name

• Less than 100  Small Scale Integration

• 100 -- 10,000  Medium Scale Integration

• 10,000 -- 100,000  Large Scale Integration

• Greater than 100,000  VLSI

• Greater than 100 Million  ULSI

 How do I design a system…???

43
 Clean Rooms
 Wafer processing is carried out in special labs called clean rooms
which are often called ‘Fabs’.
 Motivation for clean rooms is dust particles which can settle on
wafers and cause defects in devices
 During wafer processing, or from ambient
 Humans emit thousands of particles every minute
 The total number of dust particles per unit volume needs to be
controlled along with temperature and humidity
 High Efficiency Particulate filters in the ceiling
 Perforated floors to allow continuous air flow

44
Clean Room Basics
 Clean Room
 A manmade mini-environment with low particle counts
 Started in medical application for post-surgery infection
prevention
 Particles kills yield
 IC fabrication must in a cleanroom, adopted by
semiconductor industry in 1950
 • Smaller device needs higher grade clean room
 • Less particle, more expensive to build
What is a Cleanroom?
 A clean area, that is designed to reduce the
contamination of processes and materials.
 This is accomplished by removing or reducing
contamination sources.
 That means clean air, stable temperature, stable
humidity, clean water, gases and chemicals, lighting,
processing- equipment, inspection and test equipment,
room infrastructure, etc.
Particles
• People ~75% • Environment
• Ventilation ~15% • Equipment
• Chemicals
• Room Structure ~5% • Process Primary
• Equipment ~5% Sources
• Exposed Skin/Hair / • Gloves
People • Tools
• Non-cleanroom Paper • Work Surfaces
• Floor
• Garments
• Vinyl, PVC, Rubber,
Ink
Particles

Example
Examples
• Particles as small as 1 micro-meter (micron) =>
0,0000001m
• The unaided eye can see particles as small as 50 microns
on a good background
• The thickness of a human hair is 100 microns
• Time to fall 1 meter in still air for a 10 micron particle is
33 seconds, for a 1 micron particle is 48 minutes
• Humans generate >1x105 particles per minute when
motionless (fully gowned)
• Humans can generate >1x106 particles when walking in
the Cleanroom
49
 Cleanroom Standards

50
 The manufacturing environment is critical for product
quality. Factors to be considered include:
• Light
• Temperature
• Relative humidity
• Air movement
• Particulate contamination

Uncontrolled environment can lead to poor product quality

=> loss of product and profit

51
 Parameters influencing the Cleanroom class
: • Number of particles in the air or on surfaces
• Number of air-changes for each room
• Air velocity and airflow pattern
• Filters (type, position)
• Air pressure differentials between rooms
• Temperature, relative humidity
• Facility Layout and Work-Flow Part of the Solution:
Air-Filtration-Systems, Air-Conditioning-Systems

52
 Air Handling Concepts & Devices

53
54
55
56
57
 Clean room attire

 Entire body is covered with special suit to prevent particle contamination

from human body
 Eye goggles, hand-gloves, and special boots to protect body from
chemicals and for preventing contamination
58 Cleanroom
MELZG 611
IC Fabrication Technology
Lecture No.2
Date . 31/07/2021
2
3
4
5
6
• An ideal crystal is a periodic array of structural
units, such as atoms or molecules.

• It can be constructed by the infinite repetition of these

identical structural units in space.

• Structure can be described in terms of a lattice, with

a group of atoms attached to each lattice point. The
group of atoms is the basis.
 Bravais Lattice
 An infinite array of discrete points with an arrangement
and orientation that appears exactly the same, from any of
the points the array is viewed from.

 A three dimensional Bravais lattice consists

 of all points with position vectors R that can be written as a
linear combination of primitive vectors. The expansion
coefficients must be integers.
Primitive Unit Cell
 A primitive cell or primitive unit cell is a volume of
space that when translated through all the vectors in a
Bravais lattice just fills all of space without either
overlapping itself or leaving voids.

 A primitive cell must contain precisely one lattice

point.
10
 Unit cell types
 Correspond to 6 distinct shapes, named after the 6 crystal systems

 In each, representations include ones that are:

 Primitive (P) – distance between layers is equal to the distance
between points in a layer
 Body-centered (I) – extra point in the center
 End-centered (A,B,C) – extra points on opposite faces, named
depending on axial relation
 Face centered (F) – extra points at each face
 c c c

b b
b
a
P a P a I =C
Triclinic Monoclinic
a  g a = g = 90o  
abc abc
c

b
a
P C F I
Orthorhombic
a =  = g = 90o a  b  c
 c
c

a2
a2
a1 a1 P or C
P I R
Tetragonal Hexagonal Rhombohedral
a =  = g = 90o a1 = a2  c a =  = 90o g = 0o a =  = g  90o
a1 = a2  c a1 = a2 = a3
a3 a.k.a. Trigonal

a2
a1
P F I
Isometric
a =  = g = 90o a1 = a2 = a3
MELZG 611
IC Fabrication Technology
Lecture No.3
Date . 07/08/2021
 Notation Summary
•(h,k,l) represents a point
•Negative numbers/directions are denoted with a bar on
top of the number
•[hkl] represents a direction
•<hkl> represents a family of directions
•(hkl) represents a plane
•{hkl} represents a family of planes
Defects
 Defects can keep moving…

Interstitial Frenkel
Vacancy
MELZG 611
IC Fabrication Technology
Lecture No.4
Date . 14/08/2021
Crystal Growth
 Basic process of IC fabrication

● Crystal growth

● Wafer preparation
● A crystal is a solid material whose constituent
atoms, molecules, or ions are arranged in an orderly
repeating pattern extending in all three spatial
dimensions.
● Study of crystals including process of
crystallization, internal structure, external
morphology, properties and classification of
crystals is known as Crystallography”.
● The study of the formation of crystals is covered
under the subhead “Crystal Growth”. The process
of crystal formation is known as crystallization.
Why do crystals form?
Crystals are orderly arrangements of pure
substances. For example, diamonds are pure
carbon, and quartz is pure silicon dioxide.
Crystals form as their component atoms move
closer and closer together. This can occur as
pressure and temperature decrease, or as a
solvent evaporates

What controls their shape and size?

Three aspects to the growth of a
crystal
 Nucleation: formation of a stable nucleus
 Diffusion of material to the nucleus
 Growth of the crystal by adding atoms

The slowest of these three aspects generally

controls the shape and size
 Different types of crystals
● If diffusion is slow, the crystal
grows spikes to get at the new
material needed & forms a dendrite
or a skeletal crystal

● If nucleation is the restriction (a)

spherulites can form (many radiating
crystals grow from one nucleus or
(b) a few large crystals

● If growth is the restriction (slow

crystallisation) then well formed
crystals develop
Silicon wafers

Silicon wafer

Microchips are made on silicon wafers.

Crystal Growth Techniques
➢ Bridgman technique
➢ This technique cannot be used for materials, which decompose before melting.
This technique is best suited for materials with low melting point.
➢ Czochralski technique
➢ the material to be grown is melted by induction or resistance heating under a
controlled atmosphere in a suitable non-reacting container.
➢ Kyropoulos technique
➢ the crystal is grown in a larger diameter . The major use of this method is
growth of alkali halides to make optical components
➢ Zone melting technique
➢ Zone melting (or zone refining or floating zone process) is a group of similar
methods of purifying crystals, in which a narrow region of a crystal is melted,
and this molten zone is moved along the crystal
➢ Verneuil technique
➢ The principle of the process involves melting a finely powdered substance using
an oxy hydrogen flame, and crystallising the melted droplets into a boule
Czochralski growth

● Technique for producing crystals from which

semiconductor wafers are cut.

● Developed by Czochralski in 1918.

● Main process: solidification of a crystal from a melt.

● Material used: Electronic Grade Polycrystalline

Silicon.
 Orientation
➢The processing characteristics and some material
properties of silicon wafers depend on its orientation.

➢ The <111> planes have the highest density of atoms on

the surface, so crystals grow most easily on these planes
and oxidation occurs at a higher pace when compared to
other crystal planes.

➢Bipolar devices are fabricated in <111> oriented crystals

whereas <100> materials are preferred for MOS devices.
 Electronics grade Silicon
➢ Electronic Grade Silicon (EGS), a polycrystalline material of high
purity, is the starting material for the preparation of single crystal
silicon.
➢ EGS is made from metallurgical-grade silicon (MGS) which in
turn is made from quartzite, which is a relatively pure form of
sand.
➢ MGS ( Metallurgical grade Silicon) is purified by the following
reaction
:Si(solid) + 3HCl (gas) →SiHCl3 (gas) + H2 (gas) + heat
➢ The boiling point of trichlorosilane(SiHCl3) is 32oC and can be
readily purified using fractional distillation.

➢ EGS is formed by reacting trichlorosilane with hydrogen:

2SiHCl3 (gas) + 2H2 (gas) →2Si (solid) + 6HCl (gas)
● Polycrystalline Si obtained.
● 99.999999% pure.
 Czochralski Growth

● Heat EGS around 15000C.

● Insert single crystal seed.
● Rotate and pull the seed.
● Pull rate decides the ingot size.
● Atom layer with same
orientation as that of seed is
developed.
● Diameter vary with speed of
pulling.
Wafers are cut from boules, which are
large logs of uniform silicon.
Pure Si ingots
CZ growth setup

● Apparatus: Puller

● Puller has 4 subsystems:

● Furnace
● Crystalpulling mechanism
● Ambient control
● Control system
 :
Furnace,Crucible, susceptor and rotation mechanisms, heating
element and power supply, and chamber.
● Crucible contains EGS melt
• Chemically unreactive to molten Si.
• Should have high melting point, thermal stability and
hardness.
• Inexpensive and reusable.
• Fused silica is used exclusively today.
• Reacts with silicon and releases silicon and oxygen into the
melt.
• Most of oxygen escapes from melt forming silicon
monoxide. It condenses on crucible wall creating
cleanliness problem.
• Alternate choice: Silicon nitride. (still developing)
Crystal pulling mechanism
● Minimum vibrations
● Control pull rate and maintain crystal
orientation precisely.
● Seed must be held precisely perpendicular
to the melt surface.
● Crystal leaves the furnace through a purge
tube.
● Ambient gas is directed along the surface
of crystal for cooling.
● Crystal enters an upper chamber
separated from the furnace through the
purge tube
Ambient control
● Growth must take place in an inert gas or
vacuum:
● Hot graphite parts must be protected
from oxygen to prevent erosion.
● Gases in ambience must not react with
molten Si.

Control system
■ Maintains process parameters:
temperature, crystal diameter, pull rate,
rotation speed etc.
■ Prefers a closed loop system
● Solidification: by reduction in temperature
● Increased pull rate: material cannot solidify as
heat will not be conducted away.
● Material near melt has higher density of point
defects.
● Hence cool quickly to prevent agglomeration
of defects.
● Point defects agglomerate and form most
commonly dislocation loops.
During the process…

● Considerable O2 is released from silica.

● 95% escape from surface as SiO.
● Reduction of O2 concentration: grow boule
under magnetic confinement.
● Field directed along the length of boule.
● Creates Lorentz force (qvB) which will change
the motion of ionized impurities in the melt in
such a manner so as to keep them away from
liquid-solid interface.
Dopant addition
● Dopant may be introduced in the melt.
● Wafer with desired resistivity.
● Boron and Phosphorous commonly for Si
● Complicated since impurities tend to
segregate at solid-liquid interface.
● Segregation co-efficient, k = CS/CL
● CS,CL – impurity concentration at solid &
liquid sides
Impurity Seggragation
➢Impurities, both intentional and
unintentional, are introduced into the silicon
ingot.
➢Intentional dopants are mixed into the melt
during crystal growth, while unintentional
impurities originate from the crucible,
ambient, etc.
➢All common impurities have different
solubilities in the solid and in the melt.
➢An equilibrium segregation coefficient ko
can be defined to be the ratio of the
equilibrium concentration of the impurity in
the solid to that in the liquid at the
interface, i.e. ko= Cs/Cl.
Impurity Distribution
Making silicon boules
Czochralski process:

Melting of Introduction Beginning of Crystal Formed

polysilico of seed crystal pulling crystal
n crystal growth
12” (30 cm) Boule
● The ends of the boule are richer in
impurities because of segregation effects.

● When the final amount of liquid solidifies,

all the remaining impurities are trapped.
 Wafer Finishing

● Boule characterized for resistivity (probe method) and

crystal perfection
● Mechanically trimmed into proper diameter
● Flats are introduced over the entire length of the boule
● Etching in HF-HNO3 to remove damage from
grinding
Wafers Cut from Boule & Polished
https://www.youtube.com/watch?v=A
MgQ1-HdElM

https://www.youtube.com/watch?v=Xb
Bc4ByimY8
Shaping operation:
● Remove seed and tang end.
● Remove ingot portions that fail in
resistivity and perfection evaluation.
● Surface grinding: defines diameter of the
wafer.
● Flats are ground along the length of the
ingot: primary flat & secondary flat.
(according to SEMI standard)
● Slicing.
● Determines surface orientation, thickness, taper and bow.
● Surface orientation analyzed by X-ray analysis.
● Two side lapping using Al2O3 and glycerin ensures
flatness of surface.
Shaping operation leaves the wafer surface and edges
contaminated and damaged…
● Damage depends on the specifics of machining operations.
● Such regions are removed by chemical etching.
● Mixtures of hydrofluoric, nitric and acetic acids:
● Nitric acid is the oxidant.
● HF dissolves the oxidized products.
● Acetic acid dilutes the system for better control on etching.
● Over the range of 30 to 500C, etching kinetics will be diffusion
controlled rather than reaction rate limited. Hence HNO3 rich
solutions are preferred to remove work damages.
● Potassium or sodium hydroxide (alkaline etching).
● Rate depends on surface orientation
● Reaction rate limited. Hence no wafer rotation.
● Excellent uniformity
Polishing
• Final step.
• Gives a smooth specular surface on which device features can be
photoengraved.
• Can be single wafer or batch wafer processing depending on equipment.
• Polishing pads made of artificial fabric and dripped with polishing slurry
and water.
• Wafers mounted on a fixture are pressed against the pad under high
pressure and rotated.
– Slurry: colloidal suspension of fine SiO2 particle in an aqueous solution
of sodium hydroxide.
– Heat generated due to friction helps sodium hydroxide to oxidize the Si
with the OH- radical. (chemical)
– Silica particle in the slurry abrades the oxidized silicon (mechanical).
Challenges associated with growth of GaAs:
● Vapor pressure of Ga is 0.001atm while that of As is ~ 10atm at
melting point (1238C).
● Arsenic evaporates and maintaining stoichiometry will be
difficult.
● The thermal conductivity of GaAs (0.07W/cm-K) is 1/3rd of
that of silicon (0.21W/cm-K)
● Heat dissipation is more difficult
● Critical resolved shear stress for creating dislocation is very
small (1/4th of silicon) at mp
● Very easy to create dislocations in GaAs

➢GaAs is typically grown by LEC or Bridgman methods

Bridgman technique : widely used
LEC for larger diameter ingots.
Liquid encapsulated Czochralski
● A sealant material such as B2O3
is used on top of GaAs to prevent
out diffusion of Arsenic.
● B2O3 melts at ~400C and seals
GaAs.
● Seed crystal is inserted through
sealant on to GaAs.
● Crystal growth occurs usually at
~20atm (high pressure LEC).
● Graphite crucible used.
● Segregation coefficient similar to
that of Si.
Liquid encapsulated Czochralski
● Sealant should have following properties:
● Impervious to As diffusion
● Chemical resistance to GaAs
● Optically transparent
● Lower density than molten GaAs (1.5gm/cc to 5.7gm/cc for GaAs)
● B2O3, CaCl2, BaCl2

● Less Ox contamination; but B gets incorporated

● As B2O3 increases heat transfer, increased chances for

defects
● Annealing or alloying with Indium reduces defects
Crystalline structure Amorphous structure

38
Wafer Fabrication
MELZG 611
IC Fabrication Technology
Lecture No.5
Date . 14/08/2021
 Example
Determining the Number of Lattice Points
in Cubic Crystal Systems
Question
Determine the number of lattice points per cell in the cubic
crystal systems. If there is only one atom located at each
lattice point, calculate the number of atoms per unit cell.
Example 3.1 SOLUTION
In the SC unit cell: lattice point / unit cell = (8 corners)1/8 = 1
In BCC unit cells: lattice point / unit cell
= (8 corners)1/8 + (1 center)(1) = 2
In FCC unit cells: lattice point / unit cell
= (8 corners)1/8 + (6 faces)(1/2) = 4
The number of atoms per unit cell would be 1, 2, and 4, for the
simple cubic, body-centered cubic, and face-centered cubic,
unit cells, respectively.
6
ETCHING

Class 6 , 22nd Aug

What is etching?
The process which can remove the
material from the surface
 Introduction
• After a thin film is deposited, it is usually etched to
remove unwanted materials and leave only the desired
pattern on the wafer
• The process is done many
• In addition to deposited films, sometimes we also need
to etch the Si wafer to create trenches (especially in
MEMS)
• The masking layer may be photoresist, SiO2 or Si3N4
• The etch is usually done until another layer of a different
material is reached
 What is Etching..

•Selective removal of unmasked areas

Purpose of Etch
• To remove material from areas identified by the
lithography process
– Areas of photoresist exposed to light
– Developing leaves only these areas open
– Etching removes substrate areas not masked
• To create structures for functional use
• To remove oxide layers below features to allow for
motion
• Introduction
• Basic Concepts
– Wet etching
– Plasma etching
• Manufacturing Methods
– Plasma etching conditions and issues
– Plasma etch methods for various films
• Measurements Methods
• Models and Simulations
• Limits and Future Trends
Introduction
• Note that
– There is undercutting, non-vertical sidewalls,
and some etching of the Si
• The photoresist may have rounded tops
and non-vertical sidewalls
• The etch rate of the photoresist is not
zero and the mask is etched to some
extent
• This leads to more undercutting
• Etch selectivity is the ratio of the etch rates
of different materials in the process
• If the etch rate of the mask and of the
underlying substrate is near zero, and the
etch rate of the film is high, we get high
selectivity
• This is the normally desired situation
• If the etch rate of the mask or the substrate
is high, the selectivity is poor
• Selectivities of 25 – 50 are reasonable
• Materials usually have differing etch rates due
to chemical processes rather than physical
processes
• Lithography provides a method to mask or open up certain areas
on a silicon wafer surface.
• When the resist layer that has been deposited on the substrate is
exposed to radiation through a mask, the resist changes
chemically.
• Subsequent development removes the exposed resist, leaving
these regions defined, but not permanently changed.
• The etch process removes the species from the exposed areas,
permanently changing the makeup of those areas.
• Connections to lower layers, subsequent patterning and layering
above these areas can define additional functionality in these
regions.
• In MEMS, features that were defined at the top level are
sometimes placed on top of a so-called sacrificial oxide layer.
Etching provides a method to remove this oxide so that the
features above can “move” on the surface. There is no parallel to
this in the semiconductor world.
Introduction
• Etch directionality is a measure of the
etch rate in different directions (usually
vertical versus lateral)
Introduction
• Other system requirements include
– Ease of transporting gases/liquids to the
wafer surface
– Ease of transporting reaction products away
from wafer surface
– Process must be reproducible, uniform, safe,
clean, cost effective, and have low particulate
production
Basic Concepts
• We consider two processes
– “wet” etching
– “dry” etching
• In the early days, wet etching was used
exclusively
• It is well-established, simple, and
inexpensive
• The need for smaller feature sizes could
only be met with plasma etching
• Plasma etching is used almost exclusively
• The first wet etchants were simple
chemicals
• By immersing the wafer in these
chemicals, exposed areas could be etched
and washed away
• Wet etches were developed for all step
• For SiO2, HF was used.
• Wet etches work through chemical
processes to produce a water soluble
byproduct
SiO 2  6HF  H 2SiF6  2H 2O
• In some cases, the etch works by first oxidizing
the surface and then dissolving the oxide
• An etch for Si involves a mixture of nitric acid
and HF
• The nitric acid (HNO3) decomposes to form
nitrogen dioxide (NO2)
Si  2NO2  2H2O  SiO 2  H2  2HNO2
The SiO2 is removed by the previous reaction
• The overall reaction is
Si  HNO3  6HF  H 2SiF6  HNO2  H 2O  H 2
• Buffers are often added to keep the etchants at
maximum strength over use and time
• Ammonium fluoride (NH4F) is often used with
HF to help prevent depletion of the F ions
• This is called Basic Oxide Etch (BOE) or
Buffered HF (BHF)
• The ammonium fluoride reduces the etch rate of
photoresist and helps eliminate the lifting of the
resist during oxide etching
• Acetic acid (CH3COOH) is often added to the
nitric acid/HF Si etch to limit the dissociation of
the nitric acid
• Wet etches can be very selective because
they depend on chemistry
• The selectivity is given by
r1
S
r2

• Material “1” is the film being etched and

material”2” is either the mask or the
material below the film being etched
• If S>>1, we say the etch has good
selectivity for material 1 over material 2
• We often deliberately build in some overetching
into the process
• This is to account for the fact that
– the films are not perfectly uniform
– the etch is not perfectly uniform
• The overetch time is usually calculated from the
known uncertainties in film thickness and etch
rates
• It is important to be sure that no area is under-
etched; we can tolerate some over-etching
• This means that it is important to have as high a
selectivity as possible to eliminate etching of the
substrate
• However, if the selectivity is too high, over-
etching may produce unwanted undercutting
• If the etch rate of the mask is not zero, what
happens?
• If m is the amount of mask removed, we get
unexpected lateral etching
Basic Concepts
• m is called “mask erosion”
• For anisotropic etching, mask erosion
should not cause much of a problem if the
mask is perfectly vertical
• Etching is usually neither perfectly
anisotropic nor perfectly isotropic
• We can define the degree of anisotropy by
rlat
Af  1 
rvert
• Isotropic etching has an Af = 0 while
anisotropic etching has Af = 1
• There are several excellent examples in
the text that do simple calculations of
these effects
• These examples should be studied
carefully
Example
• Consider the structure below

• The oxide layer is 0.5 m. Equal structure widths and spacings, Sf, are
desired. The etch anisotropy is 0.8.
• If the distance between the mask edges, x, is 0.35 m, what structure
spacings and widths are obtained?
Example
• To obtain equal widths and spacings, Sf, the mask width, Sm, must be
larger to take into account the anisotropic etching
• Since
Sm  S f  b
where b is the bias on each side, and
• Since
b
Af  1 
d

• Thus

S m  S f  2 x f 1  A f 
Example
• This result makes sense
– For isotropic etching, Af=0 and Sm is a maximum
– For perfectly anisotropic etching, Af=1 and Sm=Sf and is a minimum
• The distance between the mask edges (x) is the minimum feature size
that can be resolved
• But
x  2S F  S m

• Substitution and rearranging yields (note typo in text)

x  S f  2 x f 1  Af 
S f  x  2 x f 1  Af 
Example
• Substituting numbers for the problem

S f  0.35 m  20.5 m 1  0.8

 0.55 m
• This result shows that the structure size can approach the minimum
lithographic dimension only when the film thickness gets very small OR
as the anisotropy gets near 1.0
• Very thin films are not always practical
• This means we need almost vertical etching
• Wet etching cannot achieve the desired results
 What is Etched and Why?
• Silicon
– Pure silicon is highly reactive and forms SiO2 from
reaction with atmospheric oxygen
– Patterning and removal of bulk structures
– Sacrificial layer below moving features in MEMS
• Silicon Dioxide
– A hard coating layer used as an insulator or a doping
barrier
– A critical layer in the construction of MOSFET devices
• The silicon substrate that makes up a wafer is an insulator,
but can be doped with impurities to create conductive
species.
• Removal of certain areas to create transistor structures is
common.
• Silicon dioxide forms on a wafer surface due to the reactive
nature of silicon with atmospheric oxygen. It can serve as an
effective masking method for the doping process above.
• In order to create a region of desired conductivity, the SiO2
is etched from a given area defined by a mask.
• The doping process that follows occurs only in that area,
since the other areas are shielded by the SiO2 that remains in
the unexposed areas.
What is etched and Why?
• Silicon Nitride
– Hard, impervious protective layer
– Remove areas for connections
• Aluminum
– Conductor used for wiring
– Removed for patterning wires
• Tungsten
– Contact barrier/Interconnect/Via plug
• Silicon Nitride is a hard, scratch resistant
layer used in place of SiO2.
• Aluminum is often for wiring and
interconnections in a device, but is often
deposited in a bulk process that must later
be patterned to create the wires.
• Tungsten is used as an interconnect
between layers of a device, and also
requires patterning.
 Etch Process Properties
Any etch process is characterized by certain properties
Etch Rate- The amount of material removed from the
wafer over a defined period of time
Etch rate measures how fast the materials is removed
from the wafer surface

Etch Rate = d/t ( Å/m)

d = d0-d1 (Å) is thickness change and t is etch time
• In any etch process, we must look at certain key areas to
characterize its performance.
• The etch rate, often given in angstroms/minute,
indicates how quickly the process proceeds. In
determining throughput, this is a key indicator.
• The uniformity of the etch at different sites on the
wafer is checked to ensure that all devices on a wafer
will be processed in the same way.
• A non-uniform etch could overetch certain areas of the
wafer, removing protective masking or more of a layer
than necessary, while leaving other areas correctly
processed.
• In test wafers, measurements are typically made at
different points to identify the uniformity.
 Etch Process Properties
Selectivity
• The ability of the etch process to distinguish between
the layer to be etched and the material
• It is the ratio of etch rates of different materials not
to be etched
• Very important in patterned etch
• Selectivity to underneath layer and to photoresist

Selectivity S
= Etch rate of target layer/ etch rate of
other layer ( mask, substrate etc)
• The profile of the etch process defines what
features may be created by a given process.
• Isotropic etching proceeds in all directions. This is
sometimes undesirable if tall, narrow features,
such as gratings or combs are desired.
• Anisotropic etch processes remove more material
in one direction, generally in the vertical direction,
than in the other. So-called vertical sidewalls
characterize a commonly defined anisotropic etch
process.
• Any etch process is characterized by
certain properties
– Uniformity
• The evenness of the removal over the entire
surface of the wafer
– Profile
• Isotropic – Etching proceeds at equal rates in
both horizontal and vertical direction
• Anisotropic – Etching proceeds faster in one
plane than in another
 Etch Profiles

Isotropic Etch Profile Anisotropic Etch Profile

•The isotropic etch profile on the left shows that etching of the sidewalls has
occurred at a similar rate to the vertical etch. The round undercut shown is
commonly found in wet etching. This can actually be used to advantage in
creating some features, such as aluminum contacts.
•The anisotropic etch profile on the right shows that the sidewalls of the
feature are nearly vertical or perpendicular to the plane.
 Etching – Wet and Dry
• Wet Etch is performed by immersing entire wafers in
liquid etchant solutions.
– Reaction is between surface layer exposed and etchant
– Purely a chemical process
• Dry etching is performed by placing the wafer in a
chamber and pumping in chemical vapors or using
plasma
• Dry etching can be chemical, physical, or both in its
etch.
Wet etching is the oldest method of material removal still in use. The
entire wafer, or often a boatload of wafers, is immersed in a liquid
etchant solution, rinsed to remove traces of the etch solution, and
dried to remove water.
 Wet Etch
• Oxidation-reduction equations often define wet etch processes
– Silicon etch with HNO3 & HF
• Si + HNO3 & HF → H2SiF6 + HNO2 + 2H2O
• Most Wet Etch Processes are Isotropic
– Etch proceeds in both vertical and horizontal direction
– Etch mixtures can change the etch rate or profile depending
on silicon crystal orientation

Wet etch processes are typically very selective in nature, which is advantageous in
processing and are simpler to carry out than dry etching.
Oxidation-reduction chemical equations define many of the reactions that take place.
The etchant mix can be altered to change the rate of the reaction, and hence the
etch rate, but in most cases, wet etch processes are isotropic, removing as much
material horizontally as they do vertically.
Certain mixes of etchants can provide a degree of orientation of the etch direction
based on the crystal orientation of the silicon that they react with.
Wet Etch Process Steps

Rinse

Etch From MATEC Module 48 Dry

 Wet Etch (2)
• Wet Etch processes can be batch processes where multiple
wafers are etched at one time
• Wet etch processes are limited to feature sizes of 3uM
or larger, limiting their use in nanomanufacturing to bulk
processes
• Wet etch can be used to remove sacrificial layers present
in MEMS devices
• Wet etch is also used for resist stripping
Wet etch processes today find little application in feature definition, but are useful for
bulk operations.
 Practical dimensional limits of feature sizes 3uM and larger due to isotropic etching
with this process limits its usefulness for these applications.
Removal of the sacrificial layer below a MEMs device often entails etching away a
larger area of material. Wet etch is sometimes used for this purpose. Wet etch also
finds use for stripping photoresist from a wafer surface after an etch or deposition
process is completed, and is favored over dry etch methods when the features below
the photomask may be damaged by ion bombardment that occurs with those methods.
Creation and etch of Sacrificial Layer
• (a) Sacrificial Layer deposition

• (b) Patterning of layer

• (c) Metal Deposition

• (d) Etch of sacrificial layer to

free feature

In MEMS devices, such as the cantilever shown above, a sacrificial layer is
deposited above the substrate.
After patterned by photolithography and etching as shown in (b), a metal layer is
grown over the layer. Wet etching can be used to remove the sacrificial layer.
Now, the metal layer is affixed on one side but can flex on one side.

http://www.aero.org/publications/helvajian/helvajian-2.html
Dry Etch Methods
• Dry Etching can be a physical or chemical
process (or both)
– Ion Beam Etch - a physical etch process
– Gaseous chemical etch
– Plasma enhanced etch
– Reactive Ion Etch
– Deep Reactive Ion Etch
Physical Dry Etch
• Sputtering (Ion Milling or Ion Beam Etch)
– Reduced pressure environment (<50 mTorr)
• Increases mean free path between molecules
– Fewer collisions between molecules
– Inert gas injected at low pressure is used as
“milling” tool
– RF Plasma in chamber
• Energy transfer to gas molecules creates a plasma
of equal numbers of ions and molecules
• Positive ions bombard negatively charged target
(wafer), removing molecules from the surface
Plasma Etching
• Plasma etching has (for the most part) replaced
wet etching
• There are two reasons:
– Very reactive ion species are created in the plasma
that give rise to very active etching
– Plasma etching can be very anisotropic (because the
electric field directs the ions)
• An early application of plasma etching (1970s)
was to etch Si3N4 (it etches very slowly in HF
and HF is not very selective between the nitride
Plasma Etching
• Plasma systems can be designed so that
either reactive chemical components
dominate or ionic components dominate
• Often, systems that mix the two are used
– The etch rate of the mixed system may be much
faster than the sum of the individual etch rates
• A basic plasma system is shown in the next
slide
Plasma Etching
Plasma Etching
• Features of this system
– Low gas pressure (1mtorr – 1 torr)
– High electric field ionizes some of the gas (produces
positive ions and free electrons)
– Energy is supplied by 13.56 MHz RF generator
– A bias develops between the plasma and the
electrodes because the electrons are much more
mobile than the ions (the plasma is biased positive
with respect to the electrodes)
Plasma Etching
 Plasma Etching
• If the area of the electrodes is the same
(symmetric system) we get the solid curve
of 10-8
• The sheaths are the regions near each
electrode where the voltage drops occur
(the dark regions of the plasma)
• The sheaths form to slow down the
electron loss so that it equals the ion loss
per RF cycle
• In this case, the average RF current is zero
Plasma Etching
• The heavy ions respond to the average voltage
• The light electrons respond to the instantaneous
voltage
• The electrons cross the sheath only during a
short period in the cycle when the sheath
thickness is minimum
• During most of the cycle, most of the electrons
are turned back at the sheath edge
• The sheaths are thus deficient in electrons
• They are thus dark because of a lack of light-
emitting electron-ion collisions
Plasma Etching
• For etching photoresist, we use O2
• For other materials we use species containing halides such as Cl2, CF4, and
HBr
• Sometimes H2, O2, and Ar may be added
• The high-energy electrons cause a variety of reactions
• The plasma contains
– free electrons
– ionized molecules
– neutral molecules
– ionized fragments
– Free radicals
Plasma Etching
Plasma Etching
• In CF4 plasmas, there are
– Free electrons
– CF4
– CF3
– CF3+
– F
• CF and F are free radicals and are very
reactive
• Typically, there will be 1015 /cc neutral
species and 108-1012 /cc ions and
Plasma Etching Mechanisms
• The main species involved in etching are
– Reactive neutral chemical species
– Ions
• The reactive neutral species (free radicals
in many cases) are primarily responsible
for the chemical component
• The ions are responsible for the physical
component
• The two can work independently or
synergistically
Plasma Etching Mechanisms
• When the reactive neutral species act
alone, we have chemical etching
• Ions acting by themselves give physical
etching
• When they work together, we have ion-
enhanced etching
Remote Plasma Etch From MATEC Module 47

• Gaseous species entering

chamber pass by an externally
generated RF Field
• This causes the generation of free
radicals that are highly reactive
and speeds up the chemical
etch process
• No plasma in the chamber
can avoid damage due to ion
bombardment.

Remote plasma (outside the reaction chamber) causes the gases to disassociate
into ions and free radicals.
The free radicals are highly reactive and pass into the chamber where they react
with the surface to be etched.
Although this increases the reaction rate, it does not improve the isotropic
properties of the process.
Plasma etch can be used for photoresist stripping in place of a wet etch process.
Direct plasma etch with oxygen may also be used but concern for possible
damage to the layer below from ion bombardment is required.
Ion Milling (cont’d)
• Plasma etch has low
selectivity
• Plasma etch tends to be
anisotropic
• High RF levels can
cause damage to the wafer

The ion milling process is purely a physical process. It suffers from a lack of
selectivity compared to other processes. It does provide an anisotropic etch
profile with minimal undercutting.
Chemical Etching
• Chemical etching is done by free radicals
• Free radicals are neutral molecules that have
incomplete bonding (unpaired electrons)
• For example
e   CF4  CF3  F  e 

• Both F and CF3 are free radicals

• Both are highly reactive
• F wants 8 electrons rather than 7 and reacts
quickly to find a shared electron
Chemical Etching
• The idea is to get the free radical to react
with the material to be etched (Si, SiO2)
• The byproduct should be gaseous so that
it can be transported away (next slide)
• The reaction below is such a reaction
4F  Si  SiF4

• Thus, we can etch Si with CF4

• There are often several more complex
intermediate states
Chemical Etching
Chemical Etching
• Gas additives can be used to increase the
production of the reactive species (O2 in CF4)
• The chemical component of plasma etching
occurs isotropic ally
• This is because
– The arrival angles of the species is isotropic
– There is a low sticking coefficient (which is more
important)
• The arrival angle follows what we did in
deposition and there is a cosn dependence
where n=1 is isotropic
Dry Chemical Etch
• Gaseous forms of chemicals are injected
into a process chamber and the wafer is
heated. Temperature is critical to etch
rate.
• Reactivity between Fl with the surface
occurs example: Si + CF4→ SiF3 + F
• Generally isotropic in nature
• Although etching of the surface will
occur, a much higher etch rate can result
with plasma enhancement.
Reactive Ion Etch
• In RIE, a combination of
physical and
chemical etching
occurs.
• In this case, both Ar and
the chemical gas are used
• Ar performs an ion
milling physical etch and
the chemical etch proceeds
as well.
Reactive Ion Etch (2)
• RIE has the advantages of the physical ion
milling etching and those of the dry
chemical etch
– Anisotropic Profile
– Higher Etch Rate than either process
– Higher selectivity ratio than physical etch
– Smaller feature sizes possible
• RIE has become the process of choice
Deep Reactive Ion Etch
• High Aspect ratio features (narrow, tall)
require vertical sidewalls
• Bosch DRIE process uses alternative etch
and passivation technique to etch
vertically and protect sidewalls with
passivation coating
• Cryrogenic process uses low temperatures
and simultaneously passivates and etches
Dry Etch Parameters (1)
• Factors Influencing Dry Etch Process
• Etch rate
- RF Power level
- Gas formula
- Etch Temperature
• Pressure
- Extremely high pressure results in an isotropic etch
- Low pressure with high energy can damage
wafer

Slide directly taken from MATEC Module 47

• Etch Rate. The etch rate during a plasma etch is determined by system design,
pressure and chemical species density.
• Because there is a direct correlation between power level and gas dissociation,
higher power levels produce more ions and radicals.
• This in turn increases the rate of etch. The etch rate also can be influenced by
the gas formula.
• Finally, the dry etch temperature influences the etch rate. Increasing
temperature increases the etch rate.
• However, at temperatures exceeding 200ºC, the photoresist can bake, which
will eventually render it difficult to remove from the wafer.
• Pressure. Pressure levels also can influence the etch profile. If the pressure in
the vacuum chamber is too high, particles begin to collide with each other and
travel off in many directions.
• This results in an isotropic etch. In the pressure range of 0.4-50.0 mTorr,
particle collisions can be kept to a minimum and anisotropic profiles can be
achieved.
• However, low pressure and high energy in the vacuum chamber can cause
plasma radiation damage to the wafer. The resulting damage includes surface
leakage, changes in electrical parameters, degradation of the film on the wafer
and overexposure. It may also harden the photoresist, making it difficult to
remove
 Dry Etch Concerns
• Factors Influencing Dry Etch Process
• Micro-loading
- Different etch rates across wafer surface
- Ashing can occur
• Post-etch corrosion
- Due to residual etchant left on wafer after final
rinse
- Using a non- chlorine based etchant such as
fluorine.eliminates the problem.

Taken directly from MATEC Module 47

• Micro-loading is a problem that can affect selectivity during the
dry etch process. It occurs when the larger surface areas on the
wafer etch at a slower rate than do smaller areas.
• As the larger areas etch, an abundance of by-product is produced.
In turn, by-product slows down the etch rate.
• On the other hand, smaller areas are not affected by a buildup of
by-product. Thus, the smaller areas etch faster than do the larger
areas.
• In turn, the smaller areas are exposed to the chemical etchant for
a longer period of time. This decreases selectivity in that region
and promotes "ashing". Ashing occurs when the etch process
removes the resist.
• Post-etch corrosion. Another problem that can arise with dry
etch is post-etch corrosion. Post-etch corrosion occurs when
residue from the etchant is left on the wafer surface after the final
rinse. Often, this is a result of Chlorine (Cl) reacting with metals
on the wafer surface. Using a fluorine-based gas mixture instead
of a Chlorine-based gas mixture can eliminate this problem
• Etching Mechanism:
• Physical removal
• Chemical removal
• Combination of both
• Depending on environment used, 2
types of etching:
• Wet Etching : Chemical
• Dry Etching : Chemical and Physical
Figures of Merit
• Etch Rate (ER):
– thickness removed per unit time
– Dependent on etching process and film to be
etched
– Should not be too slow or too fast (poor control)
• Etch rate uniformity:
– Determines if the etch rate has any position
dependence on wafer
– Given by

– Low value indicates etch rate is same across

wafer
• Selectivity of Etch (S):

– Sfm: Ratio of etch rate of film to etch rate of hard

mask/ photo resist
– Sfs: Ratio of etch rate of film to etch rate of substrate
beneath it
– High selectivity desired
– Low selectivity results in etching of substrate or
resist above desired film
• Degree of Anisotropy (Af)

– Indicates the directionality of etch

– ‘l’ represents lateral undercut while ‘h’ represents film
height
Etch Directionality:
•Measure of relative etch rates in different
directions usually vertical vs. Lateral

•Isotropic Etching: Etch rates are same in all

directions. It is usually related to chemical
processes

•Anisotropic Etching: Highly directional

etching with different etch rates in different
directions. It is usually related to physical
processes such as ion bombardment and
sputtering
•Anisotropic etching is the preferred
process
•Advantageous for today’s shrinking
feature sizes
Wet Chemical Etching Mechanism:

• Diffusion of reaction species through boundary layer on to

wafer surface
• Reaction with desired film to form etch products
• Removal of etched products via diffusion through boundary
layer to bulk liquid
• Slowest one is the rate limiting step
• Transport of etchants:
– Etchants are in the solution.
– Solution layer adjacent to surface to be
etched is depleted of etchant material.
– Materials above this layer must diffuse to the
depleted area  Diffusion governs the
process.
– Gas evolution during surface reaction avoids
the need for this diffusion in certain cases.
• Surface reaction:
– Reaction rate depends on crystal orientation.

• Transportation of reaction products:

– Products must be removed for further
reaction to happen.
– Constant stirring/agitation.
• Etching of Si
– Two step process
• Conversion to SiO2
• Etching of SiO2
– Etchant: HNO3 + HF

• Etching of SiO2
– Etchant: Buffered HF
Controlling Etching
• Provide an etch-stopping layer.
• Orientation dependent.
• Controlling Doping of substrate.
• Heavy doping  Difficult to etch.
• Etch rate is high for:
• Thin films.
• Irradiated films.
• Films with some stress.
• Films with improper stoichiometry.
Metal film etching
• Aluminum and Gold.
• Etching Al is fairly simple.
• H3PO4 + HNO3
• Cannot be done if the substrate is GaAs. [HCl +
H2O]
• Gold etching:
• Aqua-regia can dissolve gold. But..
• Etchant: KI + I2 + H2O
• Solution is opaque due to iodine.
• Difficult to inspect.
• Alternative : “Lift-off”
WET ETCHING
• Lack of anisotropy
• Poor process control
• Excessive particle contamination.

• Highly selective.
• Less damage to substrate.
Example
• This result makes sense
– For isotropic etching, Af=0 and Sm is a maximum
– For perfectly anisotropic etching, Af=1 and Sm=Sf and is a minimum
• The distance between the mask edges (x) is the minimum feature size
that can be resolved
• But

x  2S F  S m

• Substitution and rearranging yields (note typo in text)

x  S f  2 x f 1  Af 
S f  x  2 x f 1  Af 
Ion-Enhanced Etching
• The ions and the reactive neutral species
do not always act independently (the
observed etch rate is not the sum of the
two independent etch rates)
• The classic example is etching of Si with
XeF2 and Ar+ ions are introduced
Ion-Enhanced Etching
Ion-Enhanced Etching
• The shape of the etch profiles are
interesting
• The profiles are not the linear sum of the
profiles from the two processes
• The profile is much more like the physical
etch alone (c)
Ion-Enhanced Etching
• If the chemical component is increased, the vertical
etching is increased, but not the lateral etching
• The etch rate is also increased
• The mechanisms for these effects are poorly
understood
• Whatever the mechanism, the enhancement only occurs
where the ions hit the surface
• Since the ions strike normal to the surface, the
enhancement is in this direction
• This increases the directionality
Ion-Enhanced Etching
Ion-Enhanced Etching
• Possible models include
– Enhancement of the etch reaction
– Inhibitor removal
• The reaction takes place only where the ions strike the surface
• Since the ions strike normal to the surface, removal is thus only
at the bottom of the well
• It is assumed that etching by radicals (chemical etching) is
negligible
• Note that even under these assumptions, the side walls may not
be perfectly vertical
Ion-Enhanced Etching
• Note that an inhibitor can be removed on
the bottom, but not on the sidewalls
• If inhibitors are deliberately deposited, we
can make very anisotropic etches
• If the inhibitor formation rate is large
compared to the etch rate, one can get
non-vertical walls (next slide)
Ion-Enhanced Etching
Types of Plasma Systems
• Several different types of plasma systems
and modes of operation have been
developed
– Barrel etchers
– Parallel plate systems (plasma mode)
– Parallel plate systems (reactive ion mode)
– High density plasma systems
– Sputter etching and ion milling
Barrel Etchers
• Barrel etchers were one of the earliest types of systems
• VT has a small one
• Here, the electrodes are curved and wrap around the quartz tube
• The system is evacuated and then back-filled with the etch gas
• The plasma is kept away from the wafers by a perforated metal
shield
• Reactant species (F) diffuse through the shield to the wafers
• Because the ions and plasma are kept away from the wafers, and the
wafers do not sit on either electrode, there is NO ion bombardment
and the etching is purely chemical
Barrel Etchers
Barrel Etchers
• Because the etches are purely chemical,
they can be very selective (but is almost
isotropic)
• The etching uniformity is not very good
• The systems are very simple and
throughput can be high
• They are used only for non-critical steps
due to the non-uniformity
• They are great for photoresist stripping
Parallel Plate Systems
• Parallel plate systems are commonly used
for etching thin films
Parallel Plate Systems
• This system is very similar to a PECVD
system except that we use etch gases instead
of deposition gases
• These systems are much more uniform across
the wafer than the barrel etcher
• The wafers are bombarded with ions due to
the voltage drop) the physical component of
the etch is found to be rather small and one
gets primarily chemical etching
 Parallel Plate Systems
• By increasing the energy of the ions
(increasing the voltage) the physical
component can be increased
• This can be done by decreasing the size of
the electrode on which the wafers sit and
changing which electrode is grounded
• In this configuration, we get the reactive
ion etching (RIE) mode of operation
• Here, we get both chemical and physical
etching
• By lowering the gas pressure, the system
can become even more directional
High-Density Plasma Etching
• This system is becoming more popular
• These systems separate the plasma density and the
ion energy by using a second excitation source to
control the bias voltage of the wafer electrode
• A different type of source for the plasma is used
instead of the usual capacitively coupled RF
source
• It is non-capacitively coupled and generates a very
high plasma density without generating a large
sheath bias
High-Density Plasma Etching
High-Density Plasma Etching
• These systems still generate high ion
fluxes and etch rates even though they
operate at much lower pressures (1—10
mtorr) because of the higher plasma
density
• Etching in these systems is like RIE
etching with a very large physical
component combined with a chemical
component involving reactive neutrals
• They thus give reasonable selectivity
Summary
Summary
Class 7
Thin film deposition
Ganesh Rajan, Ph.D.
[email protected]
Linked in: Ganesh Rajan
Member of technical staff, technology development for MRAM
Globalfoundries
 Type of semiconductor foundries

▪ Pure play
– Foundry focuses mainly on production of ICs.

▪ Integrated device manufacturing (IDM)

– Does both design and production of Ics.

Image courtesy: Wikipedia.org

 Type of semiconductor foundries

▪ Pure play
– Foundry focuses mainly on production of ICs.

▪ Integrated device manufacturing (IDM)

– Does both design and production of Ics.

Image courtesy: eenewseurope

How does it all fit together..

Image courtesy: Wikipedia.org

Image courtesy: slideplayer.com
Inside typical foundries

Image courtesy: Wikipedia.org

Basic FEOL process

https://www.iue.tuwien.ac.at/phd/rovitto
/node10.html
Simple subtractive patterning
 Epitaxial growth

▪ Growth of single crystal semiconductor layer over a

single crystal semiconductor substrate.
▪ Two types:
▪ Homoepitaxy.
▪ Heteroepitaxy.

▪ Substrate wafer acts as the seed.

▪ Common techniques:
– CVD
– MBE
CVD

▪ Chemical Vapour Deposition

▪ Method: chemical reaction between gaseous compounds.
▪ In cases where gas sources are not available, a carrier gas
such as H2 or N2 is bubbled through the liquid that carries
vapors to chamber
▪ Also known as vapour-phase epitaxy.
▪ Two variations:
– APCVD
– LPCVD.
CVD

APCVD

LPCVD
Example of CVD used in fabrication

▪ Dielectrics: HfO2, SiO2, TiO2

▪ Gate electrode: TiN, TaN
▪ Metal interconnects: Copper, polysilicon
▪ Diffusion Barriers: TiN, TaN
▪ Contact plugs: Tungsten (W)
▪ Silicides
Steps involved in CVD
▪ Transportation of reactants to substrate.
▪ Reactor adsorption
▪ Chemical reaction followed by epitaxial growth.
▪ Desorption of gaseous products.
▪ Transportation of reaction products from reaction chamber.
Analyzing CVD
▪ Although CVD process is quite
complicated, we can analyze by just
considering two important steps:
– Diffusion of reactants across boundary
layer (Flux F1)
– Reaction at surface (Flux F2)
▪ We can analyze the process at
equilibrium
– F1 = HG(CG – CS) where HG is the mass
transfer coefficient
– J2 = Ks CS where Ks is the surface reaction
rate
▪ In steady state, F1 = F2
▪ If kS << hG , then we have the surface
reaction controlled case
▪ If hG << kS, then we have the mass
transfer, or gas phase diffusion,
controlled case
Silicon CVD

▪ Main sources:
▪ Silicon tetrachloride
▪ Dichlorosilane
▪ Trichlorosilane
▪ Silane

▪ Commonly uses SiCl4high temp. process.

▪ Others used because of lower temperature.
SiCl4 + 2H2  Si (solid) + 4HCl (gas)
Accompanying reaction:
SiCl4 + Si (solid)  2SiCl2 (gas)
Gallium Arsenide CVD

▪ Similar to Si CVD process.

▪ Ga and As dissociates at high temperature.
▪ Use As4 and GaCl3 for both components.
Metal Organic CVD
▪ For elements:
– That do not form stable hydrides and halides.
– That form stable metal-organic compounds.
▪ Extensively for heteroepitaxial growth.
▪ Major problems with MOCVD has been carbon
contamination and particulates which are
detrimental to electrical characteristics (especially
for hot-wall reactors); the hazards of the reactor
gases is also significant
MBE
▪ Evaporation of Si (or any other
semiconductor) and desired dopants under
very high vacuum (10-8 Torr) and low Temp
(4000 - 8000C) higher temp gives better
properties
– Predominantly used for III-V semiconductors

▪ Atoms or molecules are directed to heated

substrate in ultra high vacuum (UHV)
▪ By utilizing very low growth rates (≈
1μm/hour) can tailor doping profiles and
composition on a monolayer scale.
▪ Advantages
– Low deposition temp
– Precise control of layer thickness and doping profile (excellent
uniformity)
– Versatile (used for fabricating heterostructures, quantum wells,
etc)
– In-situ cleaning and characterization
▪ High temp. baking to decompose native oxygen.
▪ Low energy ion beam of inert gas to sputter impurity.

▪ Disadvantage:
– Expensive (UHV), very slow deposition
▪ Lattice matched epitaxy:
homoepitaxy.
▪ Two cases of heteroepitaxy:
– Lattice matched.
– Strained-layer.
Defects in epitaxial layers

▪ Defects from substrates

▪ Defects from interface.
▪ Precipitates or dislocation loops.
▪ Misoriented areas of an epitaxial film (low angle grain boundary)
▪ Edge dislocation
▪ In heteroepitaxy of two lattice-mismatched semiconductor.
Step Coverage

▪ Relates surface topography of deposited film to various steps on

substrate.
– Conformal step coverage (ideal)
– Non-conformal step coverage.
Dielectric Deposition

▪ APCVD, LPCVD, PECVD

▪ PECVD: plasma enhanced reaction.
▪ Energetic ion bombardment.
▪ High density plasma helps to improve electrical and mechanical
properties.
SiO2
▪ Quality not upto that grown by thermal oxidation.
▪ Insulator for multilevel metalization, masking ion
implantation and diffusion.
▪ Low temperature process: film is formed by reacting
silane, dopants and oxygen.
– Suitable for deposition over Al.
▪ Intermediate temperature process: decomposition of
TEOS.
▪ At higher temperatures, deposited oxide film will be
structurally similar to that grown by thermal
oxidation.
Si3N4

▪ Simple thermal nitridation: slow growth rate, high growth

temperature.
▪ Two methods for deposition:
– Intermediate temperature LPCVD
▪ High density stoichiometric film.
▪ Application: device passivation, mask for selective oxidation of Si.
– Low temperature plasma assisted CVD.
▪ Lower density non-stoichiometric film.
▪ Application: final passivation layer.
Metallization - PVD

▪ Ti, Al, Cu, TiN, TaN

▪ Methods:
– Evaporation
– E-beam evaporation
– Plasma spray deposition
– Sputtering.

▪ Evaporation:
– Source heated in an evacuated chamber.
PVD - E-beam evaporation
▪ Target material is bombarded
with an electron beam given off
by a charged tungsten filament
under high vacuum.
▪ The electron beam causes
atoms from the target to
transform into the gaseous
phase.
▪ They precipitate into solid form,
coating everything in the
vacuum chamber (within line of
sight) with a thin layer of the
anode material.
PVD - E-beam evaporation

Formula to calculate dep rate

▪ V=deposition rate
▪ R0= Evaporation rate
▪ Θi= angle between evaporation source normal and substrate
surface normal.
▪ Θk= angle between substrate surface normal and line connecting
evaporation source and a point on the substrate.
▪ N=density of the deposited film.
 PVD - Ion beam sputtering
▪ Ion current and energy adjusted.
▪ Other sputtering techniques:
▪ Magnetron sputtering
▪ Reactive sputtering

https://www.youtube.com/embed/L6ZIkmIVm6c?rel=0
 PVD – DC magnetron sputtering

https://www.youtube.com/embed/L6ZIkmIVm6c?rel=0
PVD – RF sputtering
Metallization - CVD

▪ Conformal coating.
▪ High throughput.
▪ LPCVD: conformal step coverage over wide range with lower
electrical resistivity.
▪ Application: refractory metal deposition.
CVD Tungsten

▪ W: as contact plug and as first-level metal.

▪ Source gas: tungsten hexafluoride (WF6)
▪ Can be reduced by Si, H2 or SiH4
▪ WF6 + 3H2  W + 6HF ---- rapid process, conformal
coverage
▪ 2WF6 + 3Si  2W + 3SiF4
▪ 2WF6 + 3SiH4  2W + 3SiF4 + 6H2 ---- high
deposition rate, high density

▪ W CVD SiH4 reduction followed by H2 reduction

CVD TiN

▪ Diffusion barrier.
▪ Can be deposited by sputtering and CVD.
▪ CVD provides better step coverage
▪ Source : TiCl4
▪ 6TiCl4 + 8NH3  6TiN + 24HCl + N2
▪ 2TiCl4 + N2 + 4H2  2TiN + 8HCl
▪ 2TiCl4 + 2NH3 + H2 2TiN + 8HCl
TiN-W usage
Aluminum Metallization

▪ Aluminum was most popular choice till late 90’s

– Has low resistivity (2.7μohm-cm)
– Good adhesion to SiO2
– Simple deposition (PVD usually)
– Dry or Wet etch possible
Aluminum Metallization

▪ Can be deposited by PVD or CVD.

▪ Problems associated: Junction Spiking, Electro-migration, Low
melting point.
▪ Spiking due to eutectic characteristics
▪ Spikes can short junctions or cause excess leakage
Electro-migration

▪ Transport of material caused by the gradual movement of the ions in

a conductor due to the momentum transfer between conducting
electrons and diffusing metal atoms
▪ leads to the eventual loss of one or more connections and
intermittent failure
Copper

▪ Advantages with Copper (Cu)

– Lower resistivity than Al (1.7) which leads to reduction in delays
– Higher melting point (~1080C) than Al
– Higher electro migration resistance than Aluminum
▪ Disadvantages / Challenges
– Highly reactive or corrosive
– Difficult to etch
– Deposition challenges
– Poor adhesion to dielectrics
– High diffusivity in Si
Solutions to problems with Cu.

▪ Fast diffusion of Cu into Si and SiO2

▪ Poor oxidation/corrosion resistance
▪ Poor adhesion to SiO2

Diffusion Barrier / Adhesion Promoter

▪ Difficulty of applying conventional etching technique

Use CMP  Damascene process

Damascene Process
▪ Pattern dielectric
▪ Deposit Cu in the trenches
▪ CMP to remove excess Cu.
Applications of thin films

Application Field Examples

Antireflection coating; on lenses or solar cells, ..

Reflection coatings for mirrors.
Coatings to produce decorations (color, luster, ...),
Optics
Interference filters.
CD's, DVD's and upcoming D's.
Waveguides.
Photosenistive coating of "analog" film for old cameray
Diffusion barriers.
Protection against corrosion / oxidation.
Chemistry
Sensors for liquid / gaseous chemicals.
"Hard" layers (e.g. on drill bits).
Mechanics Adhesion providers.
Friction reduction.
Hard disks, read write heads
Magnetics Video / Audio tape, MRAMs,
"SQUIDS"
Electricity Insulating / conducting films; e.g. for resistors, capacitors.

(without semiconductors) Piezoelectric devices

Q & A

▪ About Thin Film

▪ About various processes in foundry
▪ About foundry life
Lithography
Ganesh Rajan, Ph.D.
[email protected]
Linked in: Ganesh Rajan
Member of technical staff, technology development for MRAM
Globalfoundries
 Type of semiconductor foundries

▪ Pure play
– Foundry focuses mainly on production of ICs.

▪ Integrated device manufacturing (IDM)

– Does both design and production of Ics.

Image courtesy: Wikipedia.org

How does it all fit together..

Image courtesy: Wikipedia.org

Image courtesy: slideplayer.com
Inside typical foundries

Image courtesy: Wikipedia.org

Basic FEOL process

https://www.iue.tuwien.ac.at/phd/rovitto
/node10.html
Simple subtractive patterning
SEM image of a transistor to metal 2 of
some shorted bits
Multiple layers of devices and metallization…
(cross section TEM image)
Types of lithography

•Photolithography

•Electron beam lithography

•X-Ray lithography

•EUV lithography

•Ion beam lithography

Photolithography…
Photo-resist

▪ Is a radiation sensitive material which changes chemically on exposure to

light.
▪ Usually a carbon based organic molecule.
▪ Two types of resist:
– Positive
▪ Regions of resist exposed to light dissolve quickly in ‘developer’
▪ Unexposed regions remain unchanged and are not removed by developer
▪ Most popular: DQN
– Negative
▪ Regions exposed to light are hard to remove by developer
▪ Unexposed regions are easily removed by developer

▪ Positive resists result in better resolution than negative resist

Spin coating of photo-resist:

https://www.youtube.com/watch?v=veqnjuXBPA8
Positive Lithography
Negative Lithography
MASK: Chrome coated quartz plate
Mask:

▪ Same size as final chip or an integral factor of final chip.

▪ During exposure, the image size is reduced.
▪ Made of fused silica.
▪ Essential properties:
– High degree of optical transparency.
– Small thermal expansion coefficient.
– Flat and polished surface.
– Resistant to scratches.
– Typically 0.6 cm thick in ordered to reduce pattern placement errors due to substrate distortion.

▪ Opaque layer: Chromium.

Aligning the masks

▪ Each successive layer has to be aligned with the previous layer.

▪ Each mask layer consists of alignment marks which help in aligning
the layers on top of each other.

Example of
alignment mark
Important alignment features:

▪ Resolution:
– ability of PR to accurately transfer patterns on to film underneath.
– Is the minimum feature size that can be transferred with minimal tolerance

▪ Registration:
– measure of how accurately patterns on successive masks can be aligned

▪ Throughput
– Number of wafers processed per hour
– For industry, this number has to be sufficiently high while maintaining good resolution and
registration
Lithography optical Contact printing

E-beam

X-ray
Proximity printing

Projection printing
Optical lithography

▪ Most popular and oldest.

▪ Follows four basic steps.
▪ Contact printing:
▪ Wafer in contact with mask.
▪ High resolution.
▪ Life of mask is less.
▪ Contamination from dust on the wafer
Optical lithography

▪ Proximity printing:
▪ Mask close to wafer.
▪ No contact (10 to 25 μm)
▪ Lesser resolution
▪ Higher mask life
▪ Minimum linewidth = critical dimension (CD) = 𝜆𝑔.
– 𝜆=wavelength
– g=gap between mask and wafer including resist thickness

▪ Projection printing:
▪ Mask kept at higher distance.
▪ Highly focused image.
▪ Higher mask life.
▪ Compromise on cost.
𝜆
▪ 𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 𝑙𝑚 = 𝑘1
𝑁𝐴
▪ NA = n sin 𝜃
Mask Aligner
Defects in photolithography

https://www.
ymsmagazin
e.com/wp-
content/uplo
ads/magazin
e_summer00
_coverstorys
u00.pdf
 E-beam lithography

▪ Optical lithography: ~0.5 microns

▪ For sub-micron fabrication: e-beam lithography.
▪ Size < 1 μm possible.
▪ Direct writing.
▪ Easy automation.
▪ Greater DOF.

SEM working principle

https://training.aarc.ua.edu/mod/book/view.php?id=66&chapt
erid=96
HOW…

▪ E-beam diameter: 0.01 to 0.5 microns.

▪ Focused on substrate.
▪ Scanned over required area.
▪ Substrate placed on movable table.
– After one scan field, need to move wafer for next imprinting.

▪ For higher resolution– smaller diameter.

▪ Smaller diameter low throughput.
▪ Minimum feature size ~ 4 x diameter.
▪ Scan field ~ 2000 x diameter.
▪ Hence higher time.
E-beam resist

▪ Basically organic polymers.

▪ 2 types : +ve and –ve
▪ Positive resist
▪ Softens with e-beam.
▪ Chemical bond breaking.
▪ Better resolution.
▪ Poor sensitivity.

▪ Negative resist:
▪ Hardens when exposed to radiations.
▪ Cross-linking.
▪ Increase in molecular weight.
▪ Poor resolution due to swelling.
Issues regarding e-beam lithography

▪ Slow process.
▪ Proximity effect.
▪ Due to electron scattering.
▪ Inter proximity effect.
▪ Intra proximity effect.

▪ USED MAINLY FOR MASKS

Issues regarding e-beam lithography

▪ Slow process.
▪ Proximity effect.
▪ Due to electron scattering.
▪ Inter proximity effect.
▪ Intra proximity effect.

▪ USED MAINLY FOR MASKS

X-ray lithography

▪ An extension of optical lithography.

▪ No direct writing.
▪ Proximity printing.
▪ Distance – 40 to 50 μm
▪ Characteristics
– Faster throughput.
– Good resolution.
– No proximity effect.
– No effect of dirt.
– Straight walls due to low absorption.
 X-ray Lithography

▪ X-ray lithography is superior to optical lithography because of the use of

shorter wavelengths and a very large DOF( depth of focus), and because
exposure time and development conditions are not as stringent.
▪ Another important benefit is that x-ray lithography is immune to low-
atomic-number particle contamination (dust).
▪ With an x-ray length on the order of 1 nm or less, diffraction effects
generally negligible, and proximity masking can be used, increasing the
lifetime of the mask.
HOW…

▪ Electron beam focused to water cooled Palladium target.

▪ Generates x-rays ( λ=4.37 angstrom)
▪ Passed through beryllium window and sent to chamber.
▪ Chamber filled with He.
▪ He doesn’t absorb x-rays.
▪ Mask and substrate kept at close proximity.
▪ Substrate is developed by x-rays.
▪ Smaller λ  higher resolution.
▪ X-ray mask: thin membrane coated with gold.
▪ All e-beam resist can be used as x-ray resist.
▪ Mainly PMMA
 1.)1Gbit SiC X-Ray mask. Photo Courtesy IBM.

2.) X-Ray Lithography process latitude in resist SAL601 available from Shipley
Company.
SEM courtesy of Mr. Deguichi, NTT, LSI Research Laboritories, Japan.

3.) SAL XRS 2000 X-Ray Lithography stepper.

www.vhti.org/images/ salpicture03.gif
www.fzk.de/imt/bereiche/ images/efe1_s3.gif
Q & A

▪ About lithography
▪ About various processes in foundry
▪ About foundry life
MELZG 611
IC Fabrication Technology
Lecture No.9
Date . 10/09/2021
OXIDATION
Content
• Properties of SiO2 • Factors affecting oxidation
• Oxidation Process • Doping
• Substrate Orientation
• Functions of SiO2 • Pressure
• Equipment for Si Oxidation • Chlorine addition
• Mechanism of Si Oxidation • Dopant Redistribution
• Polysilicon Oxidation
• Additional Oxidation Processes
Thermal SiO2 Properties
Oxidation Process
 Conceptual Si Oxidation System
Thermal Oxidation
• Heat is added to the oxidation tube during the reaction
..between oxidants and silicon
- 900-1,200C temperature range
- Oxide growth rate increases as a result of heat
• Used to grow oxides between 60-10,000Å
Thermal Oxidation Process
Wafers are placed in wafer load station
• Dry nitrogen is introduced into chamber
- Nitrogen prevents oxidation from occurring
• Nitrogen gas flow shut off and oxygen added to chamber
- Occurs when furnace has reached maximum temperature
- Oxygen can be in a dry gas or in a water vapor state
• Nitrogen gas reintroduced into chamber
- Stops oxidation process
• Wafers are removed from furnace and inspected

Dry Thermal Oxidation Characteristics

• Oxidant is dry oxygen
• Used to grow oxides less than 1000Å thick
• Slow process
- 140 - 250Å / hour
• Cleaned wafers are placed in the wafer load station where dry nitrogen (N2) is
introduced into the chamber.

• The nitrogen prevents oxidation from occurring while the furnace reaches the
required temperature.
•

• Once the specified temperature in the chamber is reached, the nitrogen gas flow is
shut off and oxygen (O2) is added to the chamber.

• The source of the oxygen can be gas or water vapor state depending upon the
process being used.

• After the oxidation is complete and the oxide layer is the correct thickness, nitrogen
is reintroduced into the chamber to prevent further oxidation from occurring.
• The wafers are then removed from the chamber and following their inspection, they are ready for further
processing.

•During dry oxidation, dry oxygen is introduced into the process tube where it reacts with silicon.

•Since dry oxidation is a slow process, it is only used in industry to grow thin oxides (<1000Å). In dry oxidation,
the amount water in the processing tube is kept at a minimum.

•If the water level exceeds 25-50ppm, the oxidation rate increases and a thick layer of poor quality oxide is
produced
Dry Thermal Oxidation Process
Thin Oxide Growth
• Thin oxides grown (<150Å) for features smaller than 1 ..million
- MOS transistors, MOS gates, and dielectric components
• Additional of chemical species to oxygen decreases ..oxide growth rate (only in special cases)
- Hydrochloric acid (HCI)
- Trichloroethylene (TCE)
- Trichloroethane (TCA)
• Decreasing pressure slows down oxide growth rate

Growing thin oxides is important in the manufacture of MOS transistors, MOS gates, and dielectric components of devices.

Many of these features are smaller than 1 micron, requiring oxides less than 150 Å thick. High quality thin oxides are difficult to grow
because under normal manufacturing conditions the oxidation growth rate is too fast to control.

Therefore, in order to grow a high quality thin oxide, the oxidation process must be adjusted to slow down the oxide growth rate.

The dry oxidation process allows control over the growth of thin oxides. Introducing hydrochloric acid (HCl), trichloroethylene
(TCE) or trichloroethane (TCA) with oxygen into the oxidation tube slows down the oxide growth rate.

Other adjustments, such as reducing the pressure level, or lowering the temperature while increasing the pressure, also slows down
the oxide growth rate and improves the quality of the oxide.

For example, 300 Å of oxide can be grown under high pressure (10atm) at low temperatures (750ºC) in thirty minutes].
Wet Thermal Oxidation
Wet Thermal Oxidation Characteristics
• Oxidant is water vapor
• Fast oxidation rate
- Oxide growth rate is 1000-1200Å / hour
• Preferred oxidation process for growth of thick oxides

The silicon dioxide growth rate is faster during wet oxidation.

Wet oxidation is therefore the preferred method to grow thick oxides. During wet oxidation, water vapor is introduced
into the heated oxidation tube.

 Because water molecules are smaller in size than oxygen molecules, they diffuse faster in silicon dioxide and the
oxide growth rate increases.

 As the silicon dioxide forms, it traps the hydrogen atoms within it.

These hydrogen atoms are released in subsequent processing steps and do not affect the quality of the oxide
Goal of Oxidation Process
The goal of oxidation is to grow a high quality oxide
layer on a silicon substrate

Oxidation is a process used in wafer fabrication to layer materials onto a wafer.

During oxidation a chemical reaction between the oxidants and the silicon atoms produces a layer
of oxide on the silicon surface of the wafer.

It is the first step in wafer fabrication and will be repeated multiple times throughout the fabrication
process.

In semiconductor manufacturing silicon dioxide (SiO2) is the most frequently grown oxide and
serves multiple purposes during wafer fabrication and device operation.
Functions of Oxide Layers (1)
Passivation
• Physically protects wafers from scratches and particle
..contamination
• Traps mobile ions in oxide layer

Passivation.
A thick protective oxide layer is grown at the beginning of wafer fabrication, and again at the
end.
The final oxide layer will continue to protect the transistor during packaging and device
operation.
During oxidation, mobile ions present on or near the silicon surface become trapped within the
growing oxide.
The oxide layer isolates these ions from the silicon and prevents them from disrupting the
performance of the device
Function of Oxide Layers (2)
Masking
• During Diffusion, Ion Implantation, and Etching

SiO2

Masking.
A layer of oxide grown on a wafer prior to the diffusion and ion implant process steps will act as a mask.
During diffusion, only those areas not covered by an oxide layer will be penetrated by the dopants.
These areas are typically the gate, source and drain regions of transistors. Since the diffusion rate of the
dopants is slower in silicon dioxide than silicon, the oxide layer prevents the dopants from reaching the
underlying silicon.
The thickness of the oxide layer is critical to its effectiveness as a mask and is determined by the diffusion
rate of the dopant [5]. Therefore, when dopants with a relatively fast diffusion rate are used, a thicker layer of
oxide is grown.
This graphic demonstrates how an oxide layer acts as a mask during diffusion. The dopants will penetrate the
region of the wafer not covered by the oxide layer.
Function of Oxide Layers (3)
Insulating Material
• Gate region
- Thin layer of oxide
- Allows an inductive charge to pass between gate
metal and silicon

A thin layer of oxide is grown in the gate regions of a

transistor.
A thin oxide layer still acts as a dielectric, but allows a small
electrical charge to pass between the gate metal and the
silicon.
This charge, called an inductive charge, opens up the gate
to allow an electrical current to flow between the source and
drain.
Function of Oxide Layers (4)
Dielectric Material
• Insulating material between metal layers
- Field Oxide

Silicon dioxide acts as an insulator when grown between two

metal layers in a device.
 A thick oxide, referred to as a field oxide, prevents electrical
charges from passing between different metal layers and minimizes
the chance for an electrical short to occur in the transistor.
Function of Oxide Layers (5)
Dielectric Material
• Tunneling oxide
- Allows electrons to pass through oxide without resistance

 Tunneling oxides are thin oxide layers grown between

superconducting materials in ROM devices.
 Due to the thinness of the oxide, electrons can pass through it
with zero resistance
Functions and Thickness of Oxide Layers
Thermal Oxidation Equipment
Oxidation occurs in tube furnace
- Vertical Tube Furnace
- Horizontal Tube Furnace

Thermal oxidation can be carried out in either a horizontal or vertical tube furnace.

Both furnaces have the same heating systems and operate in the same manner, but differ in their geometrical orientation. Vertical
furnaces are more prevalent in industry today because they require less floor space and eliminate many of the problems associated
with horizontal furnaces, namely uneven temperature and gas flow. Regardless of the furnace, the oxidation process is the same.
Wet Thermal Oxidation Techniques
Bubbler

Bubblers. A glass flask, referred to as a bubbler contains deionized water and is attached to the oxidation tube. The water is
heated (90-99º C), and water vapor forms above the deionized water level. A carrier gas, nitrogen, is bubbled through the deionized
water. As it passes through the vapor it becomes saturated with water. The vapor travels into the oxidation tube, where with
additional heating it turns into steam and oxidation occurs. A consistent oxide growth rate is hard to maintain with the bubbler
method because of the difficulties involved in controlling both the amount of water vapor entering the oxidation tube and the
temperature of the water. The risk of contamination is also high.
Wet Thermal Oxidation Techniques
Flash System

Flash System.
A flash system is similar in design to a bubbler. A small amount of deionized water is dropped
onto a heated quartz surface where it instantly turns into steam. A carrier gas moves the steam
into the heated oxidation chamber. As with the bubbler, it is very difficult to achieve a constant rate
of oxide growth. Unlike a bubbler, however, the flask is never opened in a flash system so the risk
of contamination is low.
Wet Thermal Oxidation Techniques
Dryox System

Dryox System. In a dryox system, oxygen and hydrogen directly enter a heated
oxidation tube. In the heated oxidation tube, the two gases mix and form water as
steam. The dryox system is preferred oxidation method for advanced devices because
the oxide growth rate can be precisely controlled. Mass Flow Controllers regulate the
gas flow into the tube, insuring uniform oxide growth. Contamination of the oxide is
limited since these gases are clean. One major disadvantage of dryox system is the
explosive nature of hydrogen at high temperatures. Safety precautions must be taken
to minimize the risk of a hydrogen explosion.
Thickness of Si consumed during oxidation

As a general principle, the amount of silicon consumed in the

oxidation reaction is 45% of the final oxide thickness. For
example, growing 10,000 Å of oxide consumes 4,400 Å of
silicon.
Kinetics of SiO2 Growth - Oxide Growth Mechanism
1. Oxidant (O2) reacts with silicon atoms
2. Silicon atoms are consumed by reaction
3. Layer of oxide forms on silicon surface

The Linear Parabolic Model

developed by Deal and Grove (1965)
demonstrates how silicon dioxide is
grown on a silicon substrate during
oxidation under both wet and dry
conditions.
The model identifies and defines two
different stages in the oxidation of
silicon: Linear and Parabolic.
Oxide Growth Mechanism (1)
Linear Parabolic Model
• Linear (first) Stage of Oxidation
- Chemical reaction between silicon and oxidants at wafer surface
- Reaction limited by number of silicon atoms available to react with oxidants
- During the first 500Å of oxide growth, the oxide grows linearly with time
- Growth rate begins to slow down as oxide layer grows

 As the first phase in oxide growth, the Linear Stage refers to the chemical reaction
resulting from the direct contact between the silicon and the oxidants at the surface of the
wafer. The reaction is limited by the number silicon atoms available to react with the
oxidants.
 For approximately the first 500 Å, the oxide grows linearly with time. From that point on,
the reaction rate begins to slow down as a direct result of the silicon dioxide layer covering
the silicon atoms.
 As the silicon dioxide layer grows, it eventually prevents the oxidants from coming in direct
contact with the silicon atoms and the Parabolic Stage of oxidation begins.
 When a thin oxide layer is needed, as in the oxidation of MOS gates, the oxide is only
grown during the Linear Stage. The reaction of the oxygen at the silicon/silicon dioxide
interface controls the oxide growth in this stage.
Oxide Growth Mechanism (2)
Linear Parabolic Model
• Parabolic Stage
- Begins when 1,000Å of oxide has been grown on silicon
- Silicon atoms are no longer exposed directly to oxidants
- Oxidants diffuse through oxide to reach silicon
- Reaction limited by diffusion rate of oxidant

 The Parabolic Stage of oxidation begins when approximately 1,000 Å

of silicon dioxide has been grown on the silicon substrate.
 At this point, the silicon atoms are no longer exposed to the oxidants
and the oxidants begin to diffuse through the silicon dioxide in order to
reach the silicon.
 The oxidation of silicon during this stage occurs at the silicon/silicon
dioxide interface. As oxidation continues, the silicon dioxide layer
thickens, and the distance the oxidants must travel to reach the silicon
increases.
 The reaction during this stage is limited by the diffusion rate of the
oxidants through silicon dioxide
Deal-Grove Model (1)
CLASS 12
16/10/2021
Ion Implantation

2
A comparison with Ion-
Implantation:

• Advantages of implantation over

diffusion;
– Lesser contamination.
– Better control over the process.
– Room temperature process.
– Better flexibility.
– Not governed by solid solubility or
concentration gradient.
• Disadvantages of Implantation over
diffusion:
– Expensive.
– Damage creation.
• Can be annealed out. But high temperature is
disadvantageous
Introduction
• Dope semiconductor
• Two way to dope
– Diffusion
– Ion implantation
• Other application of ion implantation

5
Dope Semiconductor: Diffusion
• Isotropic process
• Can’t independently control dopant
profile and dopant concentration
• Replaced by ion implantation after its
introduction in mid-1970s.

6
Dope Semiconductor: Diffusion
• First used to dope semiconductor
• Performed in high temperature furnace
• Using silicon dioxide mask
• Still used for dopant drive-in
• R&D on ultra shallow junction formation.

7
 BASICS
• Ionized impurity atoms are
accelerated by an electrostatic field
and made to strike the surface of
wafer
• By measuring ion current and
adjusting electrostatic field, the
penetration depth and dose can be
controlled
 Dope Semiconductor: Ion
Implantation

• Used for atomic and nuclear research

• Early idea introduced in 1950’s
• Introduced to semiconductor
manufacturing in mid-1970s.

9
 Dope Semiconductor: Ion
Implantation
• Independently control dopant profile (ion
energy) and dopant concentration (ion
current times implantation time)
• Anisotropic dopant profile
• Easy to achieve high concentration
dope of heavy dopant atom such as
phosphorus and arsenic.

10
Misalignment of the Gate

11
Ion Implantation, Phosphorus

12
Comparison of
Implantation and Diffusion

13
 Comparison of
Implantation and Diffusion
Diffusion Ion Implantation

High temperature, hard mask Low temperature, photoresist mask

Isotropic dopant profile Anisotropic dopant profile

Cannot independently control of the dopant Can independently control of the dopant
concentration and junction depth concentration and junction depth

Batch process Both Batch and single wafer process

14
Ion Implantation Control
• Beam current and implantation time
control dopant concentration
• Ion energy controls junction depth
• Dopant profile is anisotropic

15
 Other Applications
• Oxygen implantation for silicon-on-
insulator (SOI) device
• Pre-amorphous silicon implantation on
titanium film for better annealing
• Pre-amorphous germanium implantation
on silicon substrate for profile control
• …...
16
Process
• Energetic ion beam injected into semiconductor surface.
• Collision with target results in energy loss.
• Energy loss due to two mechanisms
– Electronic stopping – interaction with electron cloud around
target atom
• Collisions with electrons around atoms transfers momentum
and results in local electronic stopping

– Nuclear stopping – interaction with nucleus of target

Stopping Mechanism
• Ions penetrate into substrate
• Collide with lattice atoms
• Gradually lose their energy and stop
• Two stop mechanisms

18
• Nuclear stopping
– Collision with nuclei of the lattice atoms
– Scattered significantly
– Causes crystal structure damage.
• Electronic stopping
– Collision with electrons of the lattice atoms
– Incident ion path is almost unchanged
– Energy transfer is very small
– Crystal structure damage is negligible
THEORY OF STOPPING MECHANISM:
Doping profile
• With perfectly amorphous target, profile will
follow a gaussian distribution

• Why amorphous?
– Crystalline targets have regular arrangement of
atoms which can aid in uninterrupted
movement of incident ions.
– Long distance movement without collision.
Projected range
• The total distance traveled by the ion
before it stops is called range R.

• Rp is the distance travelled in the

direction of incident beam.

• Fluctuations in projected range

modeled by its mean value is
Straggle, ∆Rp.
Distribution profile
Peak concentration:
• Dopant concentration can be expressed as a
function of depth:

• Where Φ is the dose.

Two Stopping Mechanism
• Nuclear stopping
– Collision with nuclei of the lattice atoms
– Scattered significantly
– Causes crystal structure damage.
• electronic stopping
– Collision with electrons of the lattice atoms
– Incident ion path is almost unchanged
– Energy transfer is very small
– Crystal structure damage is negligible
26
Stopping Mechanism
• The total stopping power
Stotal = Sn + Se
• Sn: nuclear stopping, Se: electronic
stopping
• Low E, high A ion implantation: mainly
nuclear stopping
• High E, low A ion implantation,
electronic stopping mechanism is more
important 27
 Stopping mechanism:
• Depends on beam’s
range of energy.
• When ion is entering, it
has maximum energy
and transfer to lattice
atoms is relatively
slow.
• Ec: Critical energy
• Ec<E => electronic
stopping. R α E1/2
• Ec>E => Nuclear
stopping. R α E
Stopping Mechanisms

29
Implantation Processes: Channeling
• If the incident angle is right, ion can travel
long distance without collision with lattice
atoms
• It causes uncontrollable dopant profile

30
Ion channeling:
• When the ion direction is such that it orients
itself along major crystallographic direction,
ions travel a great distance before stopping
– Results in Deep junctions
– For each species such as B, P, etc, there
is a critical angle when this begins

• Avoided by implanting at small angle ~ 7º tilt

• By using a thin screening layer of PR or SiO2

Channeling Effect

32
Post-collision Channeling

33
Post-collision Channeling
Collisional Channeling Collisional
Dopant Concentration

Distance from surface

34
Implantation Processes: Channeling

• Ways to avoid channeling effect

– Tilt wafer, 7° is most commonly used
– Screen oxide
– Pre-amorphous implantation, Germanium
• Shadowing effect
– Ion blocked by structures
• Rotate wafer and post-implantation
diffusion 35
Damage Process
• Implanted ions transfer energy to lattice
atoms
– Atoms to break free
• Freed atoms collide with other lattice atoms
– Free more lattice atoms
– Damage continues until all freed atoms stop
• One energetic ion can cause thousands of
displacements of lattice atoms
36
 Lattice Damage With One
Ion

Light Ion

Damaged Region

Heavy Ion

Single Crystal Silicon

37
Implantation Processes: Damage
• Ion collides with lattice atoms and knock
them out of lattice grid
• Implant area on substrate becomes
amorphous structure

Before Implantation After Implantation

38
 Implantation Processes: Anneal

• Dopant atom must in single crystal

structure and bond with four silicon atoms
to be activated as donor (N-type) or
acceptor (P-type)

• Thermal energy from high temperature

helps amorphous atoms to recover single
crystal structure.
39
 Thermal Annealing

Lattice Atoms Dopant Atom 40

 Thermal Annealing

Lattice Atoms Dopant Atom 41

 Thermal Annealing

Lattice Atoms Dopant Atom 42

 Thermal Annealing

Lattice Atoms Dopant Atom 43

 Thermal Annealing

Lattice Atoms Dopant Atom 44

 Thermal Annealing

Lattice Atoms Dopant Atom 45

 Thermal Annealing

Lattice Atoms Dopant Atom 46

 Thermal Annealing

Lattice Atoms Dopant Atoms 47

 Implantation Processes:
Annealing

Before Annealing After Annealing

48
Rapid Thermal Annealing (RTA)

• At high temperature, annealing out pace

diffusion
• Rapid thermal process (RTP) is widely
used for post-implantation anneal
• RTA is fast (less than a minute), better
uniformity, better thermal budget control,
and minimized the dopant diffusion
49
RTP and Furnace Annealing
Question and Answer
• Why can’t the furnace temperature be
ramped-up and cooled-down as quickly
as RTP system ?
• A furnace has very large thermal capacity,
it needs very high heating power to ramp-
up temperature rapidly. It is very difficult to
ramp up temperature very fast without
large temperature oscillation due to the
temperature overshoot and undershoot .
51
 SYSTEM SET-UP
• Consists of:
Ion source,
Acceleration tube,
Mass Analyzer,
End station
• Ion source:
– Consist of a dopant source and ionization
scheme (electronic discharge).
– Ionized dopants are expelled through the
outlet to next stage.
• Accelerator:
– Imparts energy to ion beam.
MASS ANALYZER
• The ion beam is passed through a magnetic sector that selects a
particular ionic species
• An ion of mass M and charge q moving at a velocity v in a circular
path will experience a force:

» According to the mass, the trajectory will be different

– a slit is used at the appropriate place to extract
desired species

• The kinetic energy of the ion is given by its extraction voltage:

• Ions are accelerated after mass separation.
• Acceleration done in vacuum to avoid collisions.
• Neutral species undesirable as they cannot be
deflected by electrostatic potential during scanning
 will get implanted near center of wafer.
• Each species will have a different mass.
• Neutral species are removed by deflecting the ions
(or bending the ion beam) so that the neutrals will
not respond to the electrostatic field and will
travel straight and strike a beam stop.
BASIC ARRANGEMENT:
Controlling dose:
• Done in first stage.
• Let beam current be I, and no. of
ionization states be n.
– No. of ions hitting target per unit time =
I/nq.
– If ionization is done for time t, total ions =
It/nq.
– Total no. of ions incident on target per
unit area
ie: dose, ϕ = It/nqA
=> Dose can be controlled by controlling,
current or exposure time or both.
Damages:
• Common for implantation since
ions are physically hitting the
wafer surface.
• If incident ion is having energy E0
and energy needed to dislodge
target atom is Ed,
– E0<Ed => no displacement
– E0>Ed => single displacement
– E0>2Ed => multiple displacements
• Estimation
– Visual inspection
– Electron microscopy
Factors affecting Implant damage:

• Light ions and heavy ions cause different type

of damage profiles. Dose also affects the
profile.
Amorphisation :

• Large dose of heavy ions makes the

material lose its crystal structure.
• Lesser channeling.
• Precise control over doping profile.
• This is why it is preferred to do pre-
amorphisation before implantation.
Annealing:
• High temperature treatment for
rectification of damages.
• Damages will be closer to surface rather
than the region of peak concentration.
• Hence need not have complete recovery
of lifetime
• Annealing time and temperature
depends on dose and orientation
Annealing

Pre-amorphised material Without pre-amorphisation

• T≤400oC • Low dose, light ions
– 20-30% recovery – Full recovery of all
• T<600oC parameters @ 800-900oC
– Recrystallization due to • Low dose, heavy ions
solid state epitaxy. – ~1000oC for recovering all
– 50-90% carrier activation. parameters.
• T>950oC • Heavy ions, high dose
– Lifetime recovery. – Difficult to recover.
Annealing:
• Removes implant damage
• Restores crystalline structure
• Activates dopants
• Done usually at 850 – 1000ºC in N2 ambient
• Long times (>30min) help remove defects
completely
– But cause significant dopant diffusion

• Secondary defects start forming at

about 500-600ºC
– Removed at 850 – 1000ºC
• Amorphous layer recrystallizes when
annealed at 600ºC for 30min (called
solid phase epitaxy)
A silicon wafer, 200mm in diameter, is implanted with
100 keV boron ions to a dose of 5 x 1015 cm-2 .
Determine the projected range (Rp), projected straggle
or standard deviation (p), and peak concentration
(no), assuming that the implant distribution is
Gaussian. Calculate the required beam current if the
implantation time is 90 seconds.
Metallization

Class 13
Metallization refers to the “wiring” of the various
components together to get a functioning circuit

 In the first IC fabricated (by Jack Kilby)

metal connections were made by external
wiring (aluminum).
 Future devices, starting from the

modifications made by Robert Noyce, had

metal lines that were fabricated along with the
IC.
 Two Types of Thin Film
Dielectric Film (CVD Process)
Oxide
Nitride
Epitaxial silicon
Conducting Film (PVD Process)
Aluminum alloy
Ti,
TiN
Silicides
Copper (CVD or electroplating)
Tungsten (Metal CVD)
Polysilicon (LPCVD)
 Integrated circuit fabrication

 FEOL (Front end of the line) - these refer to the

fabrication of the active and passive elements of the
circuit. These are the resistors (or conductors),
capacitors, diodes, and transistors that make up the
various elements of the IC.
 Gate and electrodes Polysilicon Polycide
 BEOL (Back end of the line) - these are the metallic
layers that are used to make the interconnections
between the various components fabricated in FEOL
and also to the connections for the external devices.
 Interconnection,Silicides,Barrier,ARC

Current metallization in the IC industry is based on copper, which is a deep defect

forming impurity in Si. Thus, Cu contamination in Si can destroy device functionality.
By separating the fabrication into two segments, it is possible to isolate the Si
processing from the metals (primarily Cu) and prevent contamination. There are strict
process and physical separation between the FEOL and BEOL.
Typical steps in patterning a metal layer are
shown
 With increase in level of integration, the
metallization materials have changed.

 At the same time, the number of metal layers

required have also increased(due to decrease in
available area between the components).

 In MSI (medium scale integration), a single

layer of metallization was sufficient . But with
increase in integration level, the number of
metal layers have also increased
 Two level metallization scheme is shown below.
The first level of metals

 provides the connection to the semiconductor

i.e. the source, drain, and gates of a transistor.
This is done by creating contact holes, using a
photomask,a process called contact masking.

 Then, metal lines are vapor deposited and the

excess metal is removed during lift-o. Usually,
there is also a post annealing step for alloying.
A two level metallization scheme.
The first layer of metal makes contact with the junctions in the device, while the
second layer of metal makes contact with the first layer and also with the external circuit. The
connections are made by defining trenches, called vias, which are separated by dielectrics.
Adapted from Microchip fabrication - Peter van Zant.
A four level metallization scheme. With increase in integration the number of metal
layers also increases. This is because the individual contacts are spaced closer and
hence there is not enough area to make all the electrical connections in one level.
Adapted from Microchip fabrication -Peter van Zant.
 Silicides
 To reduce contact resistance of metal/semiconductor
interface
 TiSi2,WSi2 and CoSi2 are commonly used materials
 Self- aligned-silicide-process (Salicide)
Barrier Layer
 To prevent aluminum diffusion into silicon
(junction-spiking)
 TiN is widely used barrier material
Barrier layer

 To prevent aluminum diffusion into silicon

 TiN is widely used barrier material
ARC (anti reflective coating) to reduce “notching”
during photolithography process
TiN is widely used material
The metal lines are then further connected to each other, to form
circuits, and then to the external devices by using a second level
of metallization.

 The two levels are separated by interlayer dielectrics to prevent

shorting. This is called intermetallic dielectric layer (IML).

 The levels can be extended to more than two, depending on the

integration level.

 A four layer scheme is shown . Current IC technology (28 nm

technology) has eleven layers of metallization. A cross sectional
image of the metal layers is shown in figure .
Eleven layers of metallization. The Si transistor is right at thebottom and in
terms of scale much smaller than the top metal layers. Thetop layer makes
contact with the leads for connections to external devices.
Source http://electroiq.com/chipworks real chips blog/2012/12/11/intel-
details-22nm-trigate-soc-process-at-iedm/
 Materials used for Metalliztion
Aluminium
 The original metal used for wiring was pure Al.
 The main advantage of using Al is that it can be easily vapor deposited (simple thermal
evaporation will work since Al has a low melting point)
 It also has good adhesion to SiO2, low contact resistance, and it is easy to pattern

Al-Si Alloy

 The problem with pure Al is that it has a low melting point of 660 C.
 When Al in contact with pure Si is heated, it forms an alloy with an eutectic point
of 577 C. This leads to dissolution of metal, especially in the formation of
shallow junctions, and can lead to shortening of the contacts

Contact issues in Al-Si contacts. (a) Excess alloying leads to melting of the Al(b) Silicide formation in
the metal layer, by using a Al-Si alloy (c) Barrier metal is usually deposited to prevent reaction between
Al and Si. Adapted from Microchip fabrication - Peter van Zant.
 This shortening can be rectified
 One is to use a barrier metal that does not alloy with Al or Si and
separates the two.
 The barrier metal should not significantly reduce the
conduction through the channel.
 Typically, high temperature metals like Ti and W or
compounds like TiN are used.
 These are sputter deposited on the wafer.

 Another option is to use Al with 1-2% Si as the contact material.

 This minimizes Al alloying with the Si wafer but does not
eliminate it completely.
 Thermal evaporation of Al-Si might now work due to the large
difference in the melting points of the two elements and other
techniques like sputtering or e-beam evaporation are needed to
maintain compositions of the contact
AL-Cu Alloys
 Device integration from MSI to LSI and VLSI
 the thickness of the metal layers decreases.
 This leads to the problem of electromigration, especially in thin Al layers.

 This is because thin films with an electrical field gradient, due to the

applied voltage, also develop a thermal gradient due to resistive heating.

 The thermal gradient is acute for thinnerlayers since their resistance is

higher.
 This causes local heating and migration of material from thinner areas of
the wire, which can cause an open circuit.
 To reduce electromigration, 0.5-4% Cu is usually added to Al. Cu
alloys with Al, to form CuAl2 precipitates (GP zones).
 These precipitates pin the grain boundaries and reduce
electromigration.
 Sometimes Si is also added to prevent Si dissolution from the wafer.
The typical alloy composition for a metal layer is Al-1.5%Si-4%Cu.
Pure Cu
 With smaller metal layers, Al-Cu has a high resistance (high resistivity of Al
alloy) and hence to increase wire conductance pure Cu replaced Al as the
metallization layer.
 Pure Cu contacts were introduced by IBM in 1990s and the standard was
quickly adopted across the industry.
 Cu can be easily metallized. It can be deposited by thermal evaporation, but
more importantly, it can be electroplated on the wafer, which decreases the
cost, since expensive vacuum chamber equipment is not needed.
 The biggest problem is that Cu diffuses into Si and SiO2. These form deep
level defects in Si which can ‘kill’ the device.
 Hence, a barrier metal, usually TiW or TiN or TaN or metal silicides, is
needed. These can be deposited by sputtering or for deep trenches, can be
deposited by chemical vapor deposition.
 As mentioned earlier, the use of Cu separates the wafer manufacturing into
FEOL and BEOL, with strict physical separation between the two to prevent
contamination.
 Usually, equipment involved in FEOL and BEOL are placed in different
locations in the fab and special clothing is used for people working with BEOL
tools.
Outline
 Introduction
 PhysicalVapor Deposition
 Chemical Vapor Deposition
 Aluminum Metallization
 Copper Metallization
 Basics

 To form low-resistance interconnections

 Types:
 Physical vapor deposition (PVD) – evaporation or

sputtering
 Chemical vapor deposition (CVD) – involves a
chemical reaction
Uses
 MOS gates

 Contacts

 Interconnect
Requirements
 Uniformity and conformal coating
 A Conformal coating is a protective chemical coating or polymer
film 25-75µm thick (50µm typical) that 'conforms' to the circuit board
topology. Its purpose is to protect electronic circuits from harsh
environments that may contain moisture and or chemical
contaminants.

 High conductivity

 High reliability
Outline
 Introduction
 Physical Vapor Deposition
 Chemical Vapor Deposition
 Aluminum Metallization
 Copper Metallization
Basics
 Also called “evaporation”
 Goal: evaporate metal; condense on wafer
surface
 Procedure:
 Convert metal from solid to vapor phase
(melt + evaporate or direct sublimation)
 Transport gaseous material to substrate

 Condense gaseous material on substrate

 Conditions:
• High temperature
Evaporation Equipment • Low pressure (10-6 –
10-7 torr)

 Target material is bombarded

with an electron beam given off
by a charged tungsten filament
under high vacuum.
 The electron beam causes atoms
from the target to transform into
the gaseous phase.
 They precipitate into solid form,
coating everything in the
vacuum chamber (within line of
sight) with a thin layer of the
target material.
Vacuum evaporation system
Achieving Low Pressure
 Evaporation chamber must be “pumped down”

  St  Q
P(t )  P0 exp  
 V  S
where: P(t) = chamber pressure at time t, P0 = initial
pressure, S = pumping speed, Q = rate of
outgassing, V = volume of chamber
 Pumping apparatus has 2-stages:
1) roughing pump: atm -> 10-3 torr
2) diffusion pump: 10-3 -> 10-6 torr
Kinetic Gas Theory
 Ideal gas law: PV = NavkT
where: k = Boltzmann constant, Nav = Avogadro’s #
(6.02 x 1023 molecules/mole), P = pressure, V =
volume, T = temperature

 Concentration of gas molecules given by:

n = Nav/V = P/kT
Deposition Rate
 Impingement rate of gas molecules hitting surface:
P P
F  2.63 10 20
molecules/cm2-s
2mkT MT
where: P = pressure (N/m2), M = molecular weight
(g/mole), T = temperature (oK)
 Time to form one monolayer
t = Ns/F
where: Ns = # molecules/cm2 in the layer
Geometric Variation
 Deposition rate has
radial dependence: Deposition source

D0
D( R)  3/ 2
  R 2  H
1    
  H  
R

where: D0 = deposition
rate at center of wafer
wafer
Surface Profiometry

stylus

film

substrate

 Used to measure deposited film thickness

 Precision = 2 Å
Limitations of Evaporation
1. Low melting point of Al
2. Difficult to achieve very large or small thicknesses
(typical range = 0.05 - 5 mm)

 Alternative = sputtering
 Advantages:
 Better step coverage
 Less radiation damage then e-beam

 Better at producing layers of compound

materials
 Thickness measurement: in-situ technique using
quartz crystal
 Variation in resonant frequency proportional

to mass deposited.
 Cosine rule for deposition:
RT
D  2 cos  cos 
r
 D=deposition rate
 Rt= rate of mass lost from source

 If substrate is placed on spherical

RT
surface D 
4r 2
 Sputtering
 Ion current and energy
adjusted.
 Physical etching at metal
disk.
 Advantageous for alloy
deposition.
 Ion damages associated can
be annealed out.

 Source of ions is accelerated toward the target

and impinges on its surface
Outline
 Introduction
 Physical Vapor Deposition
 Chemical Vapor Deposition
 Aluminum Metallization
 Copper Metallization
Advantages
 Conformal coatings
 Good step coverage
 Can coat a large number of wafers at a time
 Lower electrical resistivity films than PVD
 Allows refractory metal (like W) deposition
Basic Set-Up
CVD Tungsten
 W: as contact plug and as first-level metal.
 Source gas: tungsten hexafluoride (WF6)
 Can be reduced by Si, H2 or SiH4
 WF6 + 3H2  W + 6HF ---- rapid process, conformal

coverage
 2WF6 + 3Si  2W + 3SiF4

 2WF6 + 3SiH4  2W + 3SiF4 + 6H2 ---- high

deposition rate, high density

 W CVD SiH4 reduction followed by H2 reduction
 CVD TiN
 Diffusion barrier.
 Can be deposited by sputtering and CVD.
 CVD provides better step coverage
 Source : TiCl4
 6TiCl4 + 8NH3  6TiN + 24HCl + N2

 2TiCl4 + N2 + 4H2  2TiN + 8HCl

 2TiCl4 + 2NH3 + H2 2TiN + 8HCl

Outline
 Introduction
 Physical Vapor Deposition
 Chemical Vapor Deposition
 Aluminum Metallization
 Copper Metallization
Properties
 Can be deposited by PVD or CVD
 Al and its alloys have low resistivity (2.7
mW-cm for Al and up to 3.5 mW-cm for
alloys)
 Adheres well to silicon dioxide
 Use with shallow junctions can create
problems, such as spiking or
eletromigration
 Eutectic Characteristics
 Addition of either component lowers Al-Si
system melting point below that of either
metal (660 °C for Al and 1412 °C for Si)
 Eutectic temperature (577 °C) corresponds
to 11.3% Al and 88.7% Si.
 Al deposition the temperature must be less
than 577 °C.
 Solubility of Al in Si
 Si dissolves into Al during
annealing
 After time t, Si diffuses a distance
of (Dt)0.5 along Al line from the
edge of the contact
 Depth to which Si is consumed
given by

 HZ   r Al 
b  2 Dt  S 
 A   r Si 

where: r = density, S = solubility of Si,

and A = ZL
Junction Spiking

 Dissolution of Si take place at only a few points, where spikes are

formed
 One way to minimize spiking is to add Si to the Al by co-
evaporation. Another method is to introduce a barrier metal (such
as TiN) between the Al and Si
 Electromigration
When current is passing through a conductor, the
electrons move from one end to the other end. They
transfer some of their momentum to the metal atoms
and gradually the metal atoms also move. This is called
electromigration. This phenomenon is not of much
importance when the current densities are low. In IC
chip the current densities are very high and
electromigration can cause failure of a circuit.
 Schematic of electromigration causing failure. (a) Early stages. Wire occupies the entire space and the current
goes through the metal. Current density is moderate (b) Void formation leads to decreased area available for
conduction and increased current density. Acceleration of failure.

In the beginning, the metal would fill the space between the insulators and the current density
would be at a certain level (fig a)

If sufficient atoms move due to electromigration, then a small void will form.
Now the all current has to go through the metal and hence near the void region, the current
density will increase.
The electrical resistance of the metal line is also higher now, because the electrical
resistance is inversely proportional to the cross sectional area.
This results in larger heat release and hence higher local temperature.
At higher temperatures, the metal atom diffusivity is higher, which makes it easier to ‘push’
the atoms.
The increased current density and higher temperature accelerates the formation of voids
and finally results in the circuit failure
Mean Time to Failure
 MTF due to electromigration is be related to the
current density (J) and activation energy by
1  Ea 
MTF ~ 2 exp  
J  kT 
 Experimentally, Ea = 0.5 eV for aluminum
 Electromigration resistance of Al can be increased
by alloying with Cu (e.g., A1 with 0.5% Cu),
encapsulating the conductor in a dielectric, or
incorporating oxygen during deposition.
Outline
 Introduction
 Physical Vapor Deposition
 Chemical Vapor Deposition
 Aluminum Metallization
 Copper Metallization
 Motivation
 High conductivity wiring and low–dielectric-constant
insulators are required to lower RC time delay of
interconnect.
 Copper has higher conductivity and electromigration
resistance than Al.
 Cu can be deposited by PVD or CVD,
 Downside:
 Cu tends to corrode under standard processing
conditions
 Not amenable to dry etching

 Poor adhesion to SiO2

Damascene Technology
Current IC fabrication uses the Cu metallization process that has replaced the use
of Al-Cu alloys.
Cu has a lower resistivity and lower electromigration effect as compared to Al.
 But copper
 is hard to remove by etching and can diuse easily through the SiO2 layer
and form deep defects in Si.
Cu also has poor adhesion on SiO2 so this cancause structural issues,
especially when used in multilayers.
The damascene process is a unique series of steps that was developed for copper
metallization, for large scale production.
It features a lithography process, followed by a low-k dielectric or barrier
layer deposition, separating the metal layers, copper electroplating, and
chemical mechanical polishing of the metal.
The schematic of the damascene process is shown
In the case of organic low k dielectrics, it is spun on and patterned.
For oxide layers, CVD is used for deposition though it is harder to
integrate this with conventional lithography

The various steps involved in this process are

 The dielectric layer is first deposited.

 The metal layer is then deposited, by electroplating.
 A barrier layer(tungsten or metal silicide) is first deposited followed by the seed layer.
Then electroplating is used to deposit the rest of the metal.
 CMP process is used to remove the excess metal and achieve planar
Surface.
The process is then repeated for multiple layers.
For multilayer metal connections, the metal from one layer needs to be connected to the metal
layer from the preceding layer and to any subsequent layers. This is done using vias
. For making electrical connections between
metals in the same layers, trenches are fabricated. In the damascene pro-
cess, both the trenches and vias and lled together in one step, this is the
reason it is called a dual damascene process. The patterning can be either
trench rst or via rst. A via rst process is shown in gure15. Here, the vias
are rst patterned and opened in the low k dielectric. Then, the trenches are
patterned. After that, both vias and trenches are lled with metal and then
excess removed by CMP. In trench rst, the trenches are rst patterned and
a second patterning opens the vias in them.
 Trenches for metal lines defined and etched in
interlayer dielectric (ILD)
 Metal deposition of TaN/Cu (TaN serves as a
diffusion barrier to prevent Cu from penetrating
the dielectric)
 Excess Cu on the surface is removed to obtain a
planar structure.
Graphical
Representation
Chemical Mechanical Planarization

Class 14
23/10/2021
• The Chemical Mechanical Polishing (CMP)
• smooth surface topography.
• Additionally, new materials such as Cu and W,
introduced in ULSI fabrication, also require extensive
use of the CMP process to form inlaid interconnect
structures.
• A fundamental understanding of the CMP process is
essential to improve process optimization and control,
and to increase the process yield and throughput in
the continuous integration and miniaturization in the
semiconductor industry.
Cross section of mulilayer metal structure planarized by CMP
What is Planarised
 Methods of Planarisation

 Thermal flow
CVD and reflow
RIE Etchback of sacrificial layer
Spin-on-glass (SOG)
Variation of above

CMP
Why is CMP imp?
 Why do we need to planarize
High density circuits

• Sub-micron features require the highest resolution imaging

techniques. This implies short wavelength and high numerical
aperture lenses resulting in small depth of focus.

CMP provides a flat surface so small depth of focus is not an issue.

• Sub-micron devices require shallow trench isolation which

requires CMP

• Sub-micron devices at high packing density require more than

three levels of sub-micron interconnect wiring which requires
CMP.
It is an adaptation of the lapping technology used to polish plate glass.
 The wafer to be polished is mounted on a wafer carrier via back pressure or
via surface tension by wetting its back surface.
 The wafer is pressed down against a rotating platen, which holds a
compliant polishing pad.
 The wafer slides on the pad surface with a relative velocity generated by the
rotation of the carrier and the platen.
 Concurrently, the abrasive slurry drips onto the platen surface and dispenses
through the wafer/pad contact interface.
 The chemical slurry and abrasive particles retained on the porous pad
surface remove the material on the wafer surface
• There are two major applications of CMP in ULSI manufacturing: to
smooth surface topography of inter-level dielectrics (ILD, usually silicon
dioxide), or to remove excess material to produce inlaid metal structure or
isolation trenches.
• The inter-level dielectric CMP is applied in conventional aluminum
metallization, where aluminum is deposited on the oxide ILD layer,
patterned, and etched to form interconnects.
• Another layer of oxide is then deposited to insulate the aluminum
interconnects. Thus three-dimensional electrical wiring is constructed.
• Device elements, such as resistors, capacitors and transistors, are
connected to
• build up ICs.
• In this practice, CMP is employed on at least the top few layers of each
ILD surface to provide a smooth surface for aluminum deposition and to
provide a field flat enough that contact vias and metal wires can be
patterned by lithography.
• The desired process end-point is determined based on the surface planarity
and the thickness of the ILD layer required for electrical isolation of
 Need for CMP
• Oxide: (or any other insulator/ dielectric)

• Consider the following example: Process steps for ‘tapping’ the ‘gate’
and ‘source/ drains’

Gate(P+)

(Source)P+ (Drain)P+
 Need for CMP
• 1. Deposit oxide (insulator/dielectric)
• 2. Coat photo resist and .... bring the mask to focus
• Focus on which plane?

Top Plane
Bottom plane

Gate(P+)

(Source)P+ (Drain)P+
 Need for CMP
• Solution: Deposit oxide and then PLANARIZE it

• Planarization removes or decreases ‘topography’

• It also removes some material from the ‘lower’ regions

Gate(P+)

(Source)P+ (Drain)P+
Sample Image

Table
Quill (Wafer Carrier)
Schematic
 Background

• Used to polish ‘bare wafer’

• IBM pioneered
• Uses particles. Class 100 or Class 1000 clean room

• Pad
• soft pad, hard pad, stacked pad
• hard pad with perforations, grooves
• Quill
• surface tension, vacuum
• Slurry
• abrasive, chemicals
 Removal Mechanism

Copper
No Removal in this region

Removal in these regions

Pad

• ==> non planar surface --> planar surface

 What is CMP?

• Polishing of Layer to
Remove a Specific
Material, e.g. Metal,
dielectric
• Planarization of IC
Surface Topology
• What is CMP?
• How does CMP work?
• Why do we need CMP?
• How do we describe CMP?
• What are the problems associated with the CMP process?
• What are the environmental impacts of CMP?
• How can we alter the environmental impacts of CMP?
CMP Basics
• What is CMP?
– CMP is a physico-chemical process used to make wafer surfaces locally
and globally flat.

– Chemical action
• hydroxyl ions attack SiO2 in oxide CMP, causing surface
softening and chemical dissolution
• oxidants enhance metal dissolution and control passivation in
metal CMP

– Mechanical action
• polisher rotation and pressure

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 CMP Basics (cont’d)

• How does CMP work?

– A rotating wafer is pressed face-down against a
rotating polishing pad; an aqueous suspension of
abrasive (slurry) is pressed against the face of the
wafer by the pad.

– A combination of chemical and physical effects

removes features from the wafer surface.

Beaudoin, et al.
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CMP Basics (cont’d)
• Why do we need CMP?
– for precise photolithography for advanced devices
– for advanced multilevel metallization processes
(Damascene)
• How is CMP described?
– key parameter: post-polish nonuniformity (NU)
• NU = ratio of the standard deviation of the post-polish
wafer thickness to the average post-polish wafer
thickness
• caused by variations in local removal rate
– important parameter is removal rate (RR)
• RR = average thickness change during polishing divided
byEngineering
NSF/SRC polishing time
Research Center for Environmentally Benign Semiconductor Manufacturing
Beaudoin, et al.
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 Metal Damascene Process
• Trenches/vias etched into ILD (interlayer dielectric)

• Metal deposition

• Metal CMP

• Repeat for multiple levels of metal

Beaudoin, et al.
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CMP Consumables

• Slurries for oxide (SiO2) polishing

– colloidal suspension of silica particles in alkaline
medium
– hydroxyl ions attack SiO2, causing softening and
chemical dissolution (mechanism unverified)
– particles range from 10 to 3000 nm, mean size 160
nm
– 12% (wt) particles, KOH used to set pH ~11
– other concerns: particle size distribution
(scratching), particle shape, particle agglomeration
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 CMP Consumables (cont’d)
• Slurries for metal (W, Al, Cu) polishing
– oxidants cause metal dissolution and passivation
(reactions to form protective layer on metal surface)
– typically alumina particles (a or g), 100 to 2000 nm in
diameter, 12% (wt) particles, pH 3 to 4
• alumina-peroxide
– 1 part slurry, 1 part 50% H2O2, pH 3.7-4.0
• alumina-ferric nitrate
– 6% alumina solids, 5% ferric nitrate, pH 1.5
• alumina-potassium iodate
– 6% alumina solids, 2-8% potassium iodate, pH
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4.0 26
 CMP Consumables (cont’d)

• W polishing
– pH 4 with H2O2 or KIO3
– pH 1.5 with ferric nitrate
– pH 6 with potassium ferricyanide, potassium acid
phosphate and ethylene diamine
• Al polishing
– peroxide or iodate-based slurries
• Cu polishing
– ammonia-based solutions, passivating agents

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 CMP Consumables (cont’d)

• Polish pads
– cast polyurethane or felt impregnated with polyurethane,
thickness~ 1-3 mm
– hardness affects planarization and nonuniformity
– surface treatment (conditioning) required to control polish
rate and slurry transport
• scraping pad surface with hard edge to remove debris,
open pores
– pads wear out quickly (100-1000 wafers/pad!)
– perforated, grooved pads coming into use (improved slurry
transport/uniformity)
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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CMP Consumables (cont’d)
• Carrier Films
– hold wafers onto polish head (carrier)
– porous polymeric materials
• held onto carrier by vacuum, thermal processing,
adhesive
– average roughness ~1-20 microns
– compressibility range 1-25% under 10 psi load (typical
of CMP conditions)
– thickness ~ 0.1-1 mm
– profound effect on polishing performance

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 CMP Requirements

• Stable, predictable, reproducible process

• Removal rates >1700 Å/min for SiO2 and >2500 Å/min for W
• Independent of device/circuit design, substrate
– good selectivity between metal and dielectric and similar
polishing rates for metals and liners
• Few defects (scratches, peeling, particles)
• Low NU
– less than 5% variation in film thickness across wafer
• 3-6 mm edge exclusion

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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Preston’s Equation
• Simplest CMP model
• Expresses polishing rate in terms of applied pressure and relative
velocity between polishing pad and wafer
– RR = Kp•P•S
• Kp = Preston coefficient (inversely proportional to elastic
modulus of material being polished)
• P = down pressure
• S = pad-wafer relative speed
– can predict general trends
– observed RR usually proportional to P and S
– cannot predict within wafer NU, feature effects, or variations due
to pattern density effects

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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CMP Process Variables
• Tool
– Pressure (down force)
– Platen and carrier speeds
– Platen temperature

• Slurry
– Flow rate (150-300 ml/min)
– Slurry age
– Temperature

• Pad conditioning

Beaudoin, et al.
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CMP Processing Problems

• Particle contamination on wafers

– slurry particles, pad material, abraded films
• Chemical contamination on wafers
– metal ions (K+, Fe3+, Ni2+)
– anions (SiO32-, WO42-, IO32-)
– surfactants
• Mechanical damage to wafers
• Nonuniform polishing
• RR variations with time during processing

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 Particle Contamination

• Electrostatic effects can cause particles to be attracted to wafer

– depends on zeta potential of particle, pH, ionic strength of
solution
– can be attractive or repulsive
• Once particles are near wafer, Van der Waals interactions
(always attractive) enhance adhesion
• To minimize particle contamination, particle and surface must
have same charge

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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Minimization of Particle Contamination:
Additives to Alumina Slurry

• Isoelectric point of: Alumina 8 - 9

W 2.0 - 2.5
SiO2 2-3
Minimization of particulate contamination may be achieved by
choosing a pH such that the surface charge (and zeta potential) of
tungsten, silica, and alumina bear the same sign.

• Two strategies possible:

– Both alumina and tungsten bear a positive surface charge (ferric
nitrate based slurries @ pH 1.5 - 2.0)
– Both alumina and tungsten are negatively charged (anionic
additives such as anionic surfactants and polyanions to slurries @
pH 3.5 - 4.0)

Beaudoin, et al.
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Mechanical Contamination

• CMP can induce rearrangement of the structure of the

metal or SiO2 wafer surface
• Can extend tens of nm into the wafer
• Highly strained structures, broken networks and loss of Si
atom tetrahedral coordination

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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https://www.youtube.com/watch?v=KV2k2Ydk
QXI
Chemical Contamination

• Chemicals in solution change oxidation state based on pH,

potential of the solution
• Reactivity also changes
• Solubility and partitioning of chemical species can vary
considerably with oxidation state and reactivity changes
• Corrosion may occur depending on redox potential of
exposed metals (TiN-W system of concern)

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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CMP Control Issues:
Polishing Nonuniformities
• Dishing
– reduction in thickness of large metal features towards the center
of the features
– caused by differences in polishing rates of metal, liner, and
insulator

• Pattern erosion
– thinning of oxide and metal in a patterned area
– increases with pattern density

• Edge effect, “racetrack” NU

– variations in removal rate due to stress variations with radial
distance across wafer

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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CMP Control Issues:
Removal Rate Drift

• As pads wear, RR decreases

• Occurs even with conditioning
• Coincident with increasing NU over time
• Solutions
– substantial use of monitor wafers to check
performance
– increase polish time over time to achieve
desired removal
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 Post CMP Cleaning
• Remove particles and chemical contamination following polishing

• Involves buff, brush clean, megasonic clean, spin-rinse dry steps

• Buffing
– after main polish , wafers “polished” using soft pads
– used following metal CMP
– oxide slurries, DI water, or NH4OH used
• changes pH of system to reduce adhesion of metal particles
• removes metal particles embedded in wafers
– can reduce cleaning loads

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 Post CMP Cleaning (cont’d)
• Brush cleaning
– brushes made from PVA with 90% porosity
– usually double sided scrubbing, roller or disk-type
– brushes probably make direct contact with wafer
– NH4OH (1-2%) added for particle removal (prevents redeposition), citric
acid (0.5%) added for metal removal, HF etches oxide to remove subsurface
defects

• Megasonic cleaning
– sound waves add energy to particles, thin boundary layers
– cleaning chemicals added (TMAH, SC1, etc.)
– “acoustic streaming” induces flow over particles
– importance uncertain

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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 Brush Box

Upper Brush Assembly

Chemical Drip Manifold

Lower Brush Assembly

Roller
Water Inlets
Rotating Wafer

Beaudoin, et al.
43
 Double Side Scrubbing (DSS)
System Configuration

Wet Sand Dual Brush Rinse, Spin Edge User

Indexer Module Dry Station Handling Interface
(Megasonic) Receive
Station
(OnTrak Systems, Inc.)

Beaudoin, et al.
44
 Post CMP Cleaning (cont’d)

• Spin-rinse drying
– following cleaning, wafers rotated at high speed
– water and/or cleaning solution (SC1) sprayed on wafer at
start
– hydrodynamics drain solutions from wafer
– probably no effect on cleaning, but ensures that particles
dislodged from wafer during preceding steps do not resettle
on wafer

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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CMP Environmental Problems
• Huge quantities of waste generated
• Polishing
– consumables (slurry, pads, water, chemicals)
– monitor wafers (used for testing purposes)
– killed wafers
– rinse water used during process
• Post-CMP cleaning
– consumables (chemicals, water, brushes, buff pads)
– post-CMP cleaning rinse water
– killed wafers

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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Waste Problems
• Slurry
– solids present in waste
– highly basic or acidic solutions cause pH changes in natural waters
• kills organisms
• enhances sediment dissolution, diminishes precipitation
– oxidizers toxic to wildlife

• Rinse waters
– large volumes tax wastewater treatment systems
– water purification wastes are significant (ion exchange wastes,
membranes, energy)

NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingBeaudoin, et al.
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Quantities of Wastes
• Typical polisher processes 40 wafers/hr. with 65% overall equipment
efficiency
• Aqueous process wastes
– 190 gallons slurry/day/machine
– 180 gallons DI rinsewater/day/machine
• Solid wastes
– 3-4 monitor wafers/pad for break in (RR drift?)
– 1-2 pads/machine/day (not including buff pads)
• Cleaning wastes
– 190 gallons rinsewater/day/machine
– cleaning chemicals highly variable

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Packaging and Assembly
The interconnect is manufactured by depositing thin films of materials.

selectively removing or changing the properties of these materials in certain areas.

A new level of thin film is deposited on top of old films and the process is repeated many
times until the interconnect is complete
.
The goal of the CMP process is to planarize step heights caused by the deposition of thin
films over existing non planar features, so that further levels may be added onto a flat
surface
Damascene process, as well as its upgraded generation – dual-damascene,is the
critical technology in the transition from aluminum to copper interconnects in
semiconductor manufacturing.

There are two primary factors driving this transition: the lower resistivity and the
increased electromigration resistance that copper offers relative to Aluminum.

In the copper interconnect fabrication process, a simpler dielectric etching replaces
metal-etch as the critical step that defines the width spacing of the interconnect lines,
while the burden of planarization shifts to the metal deposition
and CMP steps.
 Need for CMP
 Where is CMP used?
 To planarize oxide, tungsten or copper

 Why planarize?
 Oxide: need planar surface for photolithography
 Copper: no other way to remove excess copper and form the wires
(shape)
 W: relatively easy method
https://www.youtube.com/watch?v=u-Ld9o-
NdHI
Yield and Reliability

Class 15
23/10/2021
 Introduction
• In integrated circuit, manufacturing involves
– design,
– fabrication,
– assembly, and
– test processes.

• Besides keeping the facility clean and free-off contamination, the

other aspect is to ensure that each process step conforms to
specifications.
• Thus, it is necessary to implement quality control scheme.
• Quality control monitoring/checking has become an important process
and is normally imposed at the end of certain critical process steps.
Besides the quality control at in process step, quality control procedure is
also required to be implemented at the incoming material inspection
stage
• Monitor the process stability/reliability and
process capability of the machine/equipment
used to process the device
• control static electricity damage to the
integrated circuit by discharging away the
static electricity generated by human being
handling the circuit.
 Yield
• In the modern sub-micron integrated circuit
fabrication, it requires a multimillion dollar
facility that consists of equipment for various
fabrication process steps, cleaning station, and
the source material.
• Beside the equipment, stations, materials are
people who are the working in the facility
• The primary quality requirement for the integrated circuit IC facility
is cleanliness.

• The facility is subjected to too many sources of contaminant, which

is harmful to device under fabrication.
– Contaminant has a size large enough to cover the active area of a sub-
micron device.
– If such type contaminant is resided on the active area of the device
during fabrication, the consequence is malfunction of the device.
– Thus, it is necessary for a modern integrated circuit fabrication facility
to keep the contaminants or particles level below part per million ppm
or part per billion ppb level

• In modern IC facility set-up, it employs three-tiered approaches to

control the particles level and contaminant level, which are clean
facility, wafer cleaning, and gettering
 Reliability
• Reliability
– study of probability that a component such as integrated circuit, equipment, or
system will satisfactorily perform the intended function under given
circumstances, such as environmental conditions, limitations as to operating
time, and frequency, and thoroughness of maintenance, for a specified period of
time.
• An integrated circuit designed for the operation in the space for a period of
15 years and if this integrated circuit can live up with the intended period
then one can say that this integrated circuit is reliable.
• Here
– learn the definition of failure rate, the statistical distribution models used to
calculate the reliability function, the failure rate, and the cumulative fail function
of the device/system.
• The student will also learn the failure rate for the lifetime of the device and
the accelerated test methods used to wipe-out unreliable device earlier
instead of waiting for a long time before failure is shown up under normal
operation conditions.
 Yield loss mechanisms
• Mainly due to three factors:
– Processing problems
– Circuit design problems
– Random point defects in the circuit.
• Processing effects:
– Variation in thickness of oxide or polysilicon layers
– In the resistance of implanted layers
– In the width of features defined by lithography
– Registration of mask with respect to previous masking
operation
• Circuit sensitivity:
– Major reason: not considering variations in device
parameters
– most important parameters for MOS circuit design
• Speed increases as they decrease
• Circuit usually simulated for high speed and low speed
conditions.
– Other parameters: resistance of implanted region,
capacitance of conductors to substrate, contact
resistance and leakage current.
– Redesign to compensate for sensitivity parameters
results in high yield and low cost.
• Point defects:
– Region of the wafer where processing is imperfect.
– Causes yield loss even when all processing factors are
with in the expected range.
– Most common is dust or other particles in
environment.
– Can occur on lithography mask as well as on Si wafer.
– Monitoring done using SEM observation of circuit
quality during all fabrication steps.
 Modeling yield-loss mechanism
• Helps predict the cost and availability of
future circuits.
• Processing quality of different process lines
can be compared if yield modeling parameters
are known.
• Most modeling predicts that yield decreases
as area of chip increases.
• Processes can be improved or eliminated once
their yield limiting features are identified.
• Uniform density of point defects:
– If n defects are distributed randomly among N chips,
probability Pk that the given chip contains k defects is
given by binomial distribution
n! 1
Pk   n ( N  1) n k
k! ( n  k )! N
– When N and n are both large and n/N=m remains
finite, this can be approximated to Poisson distribution:

mk
Pk  e m
k!
– Probability that chip contains no defects:
Y1  P0  e  m
– Probability that chip contains one defect:
P1  me m
 Failure distribution, reliability, and failure
rates
• Reliability: probability that the item will perform
a required function under stated conditions for
stated period of time.
– Required function: satisfactory and unsatisfactory
operation(failure)
– Stated condition: physical environment, mechanical,
electrical and thermal conditions expected
– Stated period of time: time during which satisfactory
operation is required. Vary depending on usage of
system.
• CDF (common distribution function):
– Suppose a system is operating at t=0
– Probability that the device will fail at or before time t is given by the
function F(t).
F (t )  0; t  0
0  F (t )  F (t ' );0  t  t '
F (t )  1; t  

• Reliability function R(t):

– Probability that the device will survive to time t without failure
R (t )  1  F (t )
• Failure rate: 1 R (t )  R (t   )
AverageFailureRate 
 R (t )
1 dR (t ) f (t ) d
 (t )      ln R (t )
R (t ) dt R (t ) dt
• MTTF (mean time to failure):
– Device’s average age at failure for a population whose reliability is represented
by R(t) with pdf f(t) 
MTTF   tf (t )dt
0
Common Distribution Functions
• Initially failure rates are high, but decreases with time:
Early failure.
– Due to manufacturing defects.
• Low and constant rates during mid-life
– Failure due to unrelated causes
• Wear-out period towards the final stage
– Reasons like corrosion
• Exponential distribution function:
– Characterized by constant failure rate over the lifetime of
the device.  (t )    const.
0

R (t )  e 0t
F (t )  1  e 0t
f (t )  0e 0t

1
MTTF   t0e 0t
dt 
0
0
– Weibull Distribution Function: failure rate varies as a
1
power of device age  t 

  1 
R (t )  e
 (t )  t
 F (t )  1  e
1
 t


• β<1 : early failure period

  1  1 t 
• β>1 : wear-out period. f (t )  t e
• β=1 : constant failure rate. Exponential 
distribution is a special case of MTTF   1  (1  1 )

Weibull distribution.
• Duane plotting:
– graphical analysis technique.
– Evaluation of prototype systems.
– Plots log of average failure rate vs log time.
• Log normal distribution function:
– Used successfully over long periods of time.
1  1  ln t    2 
f (t )  exp     
t 2  2    
 1 1 t  
2

t50  e 
1
 exp    ln  
t 2  2   t50  
 Two failure populations
• Failure rate study is complicated due to the
existence of multiple failure mechanisms.
• Can use log normal distribution
– σ, µ: different for each mechanism.
• Two modes:
– Short median life.
• Small percentage of total population: sport population.
• Represents early failure mechanism.
– Long median life
• Represents steady state failure mechanism.
 Accelerated testing:
• Under normal operating condition, the time
required to observe failure in a device is very
high.
• Accelerated testing: to study the failure chara by
accelerating the mechanisms that cause devices
to fail.
– Temperature
– Voltage
– Current
– Humidity
– Temperature cycling
 Temperature acceleration
• Major cause of failure: chemical, physical
processes.
• Accelerated by temperature.
• If R is the reaction rate at which these
processes proceed,
R  R0 exp(  Ea kT )
t1  Ea  1 1 
AccelerationFactor   exp    
t2  kT  T1 T2 
• Assumes failure reaction is linear in time.
Voltage and current acceleration
• Accelerates failure caused by dielectric breakdown,
interface charge accumulation, charge injection, corrosion.
• Variations applicable for voltage is limited as most ICs
doesn’t work properly if applied voltage is beyond the
specified range.
• Studies indicate that R of failure mechanism is
proportional to a power of applied voltage.
 (T )
R(T ,V )  R0 (T )V
• Different stages in case of dielectric breakdown. Operation
at an increased voltage is more in the nature of burn-in.
• Current acceleration: for failure due to electromigration.
Same relationship for R as above.
 Stress dependent activation energy.

• Eyring model: to understand thermally and

stress activated failure mechanisms.
– Assumes that the energy required for the reaction
to take place is affected by applied stress(V or I).

 a (T ) S   Q 
R sinh   exp  
 kT   kT 
a (T )  kT (T )
Q  Ea 0  a (T ) S B
 Humidity-Temperature acceleration
• Possible failure mechanism: presence of water
vapor in the chip.
– Permeates plastic packaging material in two steps
• Transports contaminants from the surface of package
through plastic and leaches impurities from packaging
material itself.
• Diffusion of contaminated water vapor through
passivation layer of chip. Slow process. Determines
reaction rate of failure mechanism.
• Causes electrochemical corrosion.
 Burn-in
• Manufactured device shows existence of early
failure.
• Photoresist or etching defects (open or shorts).
• Contamination on chip or in package
• Scratches.
• Weak chip or wire bonds
• Partially cracked chip or package
• Burn-in: operation of device for a period of time
during which most of the devices subjected to
early failure actually fails.
• Acceleration depends on mechanism contributing
to early failure.
 Failure mechanisms
• Electrostatic discharge damage:
• Voltages higher than breakdown voltage of gate oxide may
be placed on the device during handling.
• Major source: triboelectricity.
• Burn-in cannot reduce this. Actually can increase early
failure rate.
• Input and output terminals are designed with protection
network to provide path for discharge of current and
protect gate oxide.
• Alpha particle induced soft errors:
• Emitted by U and Th occurring in packaging materials.
• Soft errors: random failure not related to physically
defective device.
• Eg: Loss of information stored.
 Failure Rate
• Failure Rate
– A system such as a calculator that made of many
semiconductor devices is put in operation for the
purpose of calculation, would have a certain failure
rate ,
– which means it may fail after certain number of
operating hour. Thus, a calculator (system) has failure
rate with respect to operating time. The question is if
such failure is acceptable to end-user.
– Let’s take another example. A certain failure rate of
the system in a commercial aircraft is it acceptable to
airtravelling passengers?
• The failure rate () of a semiconductor device
implemented in the system is defined as
= No of Failure/No of transistor x period of operation

• If a system contains 100,000 transistors then the failure

rate () from one month operation is equal to
= No of Failure/No of transistor x period of operation
= 1 Failure/1x10-5x720hrs

which is equal to 14x10-9 Failure/Device-hour.

• If the unit of failure is defined to be 1 Failure Unit = 1
FIT = 1 Failure/10-9 Device-hour

• If one now considers a system that has 225 integrated

circuits and the failure rate of integrated circuit is 100
FIT. One can calculate the mean time to a failure using
above equation.
• Thus,
Period of operation< 1 Failure/ No of transistor x  =
1Failure/225 x100 x 10-9 = 4.44x104 hrs, which
is equal to 5.13 years.
• The percentage of failure per month shall be
100x10-9 x225x720x100% = 1.62%.
• Based on the above discussed example, one would see that it is
time consuming before a failure is shown out. We cannot be waiting
for 5.13 years to see a failure is shown out to calculate the failure
rate of a system.
• One ought to have a developed method by sample testing to
predict the failure rate of the system. In this section, it discusses the
methods to quantitatively measure and predict device failure rate,
and to identify and eliminate the failure mechanism.

• If a device or system is operating at time t = 0. The probability that

the device will fail at or before time t is given by the function F(t).
This is a cumulative distribution function cdf with the following
properties.
•

The reliability function R(t) is a probability that the device will

survive to time t without failure. Thus, the reliability function
R(t) is related to fail function by equation below
 R(t) = 1- F(t)
• The derivative of fail function F(t) with respect
to time is known as the probability density
function pdf and is represented by f(t). Thus,
the pdf is related to the cdf by
F(t) =d/dt F(t)
or the cumulative function
• Similarly the reliability function

And

The term failure rate is referred to as instantaneous fail rate and not average

The fraction of devices that are good at time t and that fails by time t+Δt is given by
F(t+t) –F(t) = R(t) – R(t+  t)
The average failure rate during the time interval  is given by
Average failure rate =1/  (R(t) – R(t+ t)/R(t)
In the limit as  approaches zero, this becomes the instantaneous failure rate () (t), which is
given by

Integrating equation it becomes

Thus, the reliability function R(t) is given by

A common measure of reliability is the mean time to failure

(MTTF) of the device or system, which is defined as

MTTF is the device’s average age at failure for a population whose

reliability function is R(t) with probability density function f(t).
• During the early life of the device, the failure rate is high but it
decreases as time passed. The failure during this period is called
infant mortality failure.
• The causes of the early failure are generally fabrication and
assembly related defects such as wire problem, micro-crack, over
etch, photoresist residue, contamination, electrostatic defect etc.
The defects can be wiped out by accelerated life test and followed
by a final test to segregate them.
• The steady useful life period, the failure rate is normally low and
the rate of failure is also fairly constant. Device failure in this period
is a result of a large number of fabrication and assembly unrelated
causes such as mishandling, applying wrong stimulant etc.
• The wear out period is the old age period, whereby the device has
reached the end of its life.
• The steady useful life period, the failure rate is
normally low and the rate of failure is also
fairly constant.
• Device failure in this period is a result of a
large number of fabrication and assembly
unrelated causes such as mishandling,
applying wrong stimulant etc. The wear out
period is the old age period, whereby the
device has reached the end of its life
 Problems
1. A disk drive's MTBF number may be 1,200,000 hours
and the disk drive may be running 24 hours a day, seven
days a week. One year has 8,760 hours. Calculate the
percentage failure? ( Ans-0.73%)
• A disk drive's MTBF number may be 700,000 hours and
the disk drive may be running 2400 hours a year.
Calculate the percentage failure ? ( Ans-0.34%)
2. Define the following terms: Failure Rate; Cumulative
distribution function; Density function; Mean time
between failure. 3
3. Define the relationship between cumulative
distribution function (cdf) F(t) and the density function
f(t).
MELZG 611
IC Fabrication Technology
Lecture No.11
Date . 03/10/2021
Steady-state diffusion across a thin plate
Steady-State Diffusion

6
Example: Chemical Protective Clothing (CPC)

• Methylene chloride is a common ingredient of paint

removers. Besides being an irritant, it also may be absorbed
through skin. When using this paint remover, protective
gloves should be worn.If butyl rubber gloves (0.04 cm thick)
are used, what is the diffusive flux of methylene chloride
through the glove?
• Data:
• diffusion coefficient in butyl rubber:
D = 110 x10-8 cm2/s
• surface concentrations:
C1 = 0.44 g/cm3
C2 = 0.02 g/cm3

10
11
Diffusion and Temperature

12
Diffusion

13
Example: At 300ºC the diffusion coefficient and activation energy for Cu in
Si are
D(300ºC) = 7.8 x 10-11 m2/s
Qd = 41.5 kJ/mol
What is the diffusion coefficient at 350ºC?

14
Example (cont.)

15
Where erf is the error function which varies for different material
Non-steady State Diffusion
• An FCC iron-carbon alloy initially containing 0.20 wt% C is
carburized at an elevated temperature and in an
atmosphere that gives a surface carbon concentration
constant at 1.0 wt%. If after 49.5 h the concentration of
carbon is 0.35 wt% at a position 4.0 mm below the surface,
determine the temperature at which the treatment was
carried out.

C( x, t )  Co  x 
 1  erf  
Cs  Co  2 Dt 

18
19
Example: Chemical Protective Clothing (CPC)

• Methylene chloride is a common ingredient of paint removers. Besides

being an irritant, it also may be absorbed through skin. When using this
paint remover, protective gloves should be worn.
• If butyl rubber gloves (0.04 cm thick) are used, what is the breakthrough
time (tb), i.e., how long could the gloves be used before methylene
chloride reaches the hand?
• Data
• diffusion coefficient in butyl rubber:
D = 110 x10-8 cm2/s

20
A comparison with Ion-Implantation:

• Advantages of implantation over diffusion;

• Lesser contamination.
• Better control over the process.
• Room temperature process.
• Better flexibility.
• Not governed by solid solubility or concentration
gradient.
MELZG 611
IC Fabrication Technology
Lecture No.10
Date . 18/09/2021
Deal-Grove Model (1)
Deal-Grove Model (2)
Deal-Grove Model (3)
Deal-Grove Model (4)
Effect of Xi on Wafer Topography (1)
Effect of Xi on Wafer Topography (2)
Factors that Affect Oxidation
High Doping concentration effect

Dopants in silicon
• Dopants increase oxide growth rate
- During Linear Stage of oxidation N-type dopants increase growth rate
• Dopants cause differential oxidation
- Results in the formation of steps
- Affects etching process
•When high concentrations of dopants are present in silicon
wafers, they tend to increase the oxide growth rate
.
•During the Linear Stage of oxidation, the presence of N-type
dopants can increase the oxide growth rate. For example,
throughout the Linear Stage of oxidation, doped phosphorous
continually moves from within the silicon to the silicon surface
of the wafer.

•This constant supply of phosphorous on the silicon surface

increases the oxide growth rate.

•Once the Parabolic Stage begins, the presence of phosphorous

at the silicon/oxide interface no longer impacts the growth rate.

• Instead, it is the presence of P-type dopants in the silicon

dioxide layer that influences the growth rate.
•During the Parabolic Stage of oxidation a dopant, such as boron, moves
from the silicon into the silicon dioxide layer where it weakens the bond
structures.

•The weakened bonds allow oxygen and water to diffuse faster through the
silicon dioxide resulting in a faster oxide growth rate.

•Since oxide grows faster in doped regions of the wafer, the oxide will not
be of uniform thickness across the wafer.
•
•This results in differential oxidation and produces unwanted steps on the
wafer as oxidation occurs at unequal rates across the wafer.

•As the thicker oxide layers consume more silicon, steps are formed which
may affect the operation of the device. The variation in oxide thickness
across the wafer must also be taken into consideration during future
etching.
•
•The etch process must be designed to remove the thicker oxide layers,
without overetching the areas with thinner oxide layers
Growth Rate Dependence on Si Substrate Orientation

Wafer Orientation
• Oxide grows faster on <111> wafers
- more silicon atoms available to react
with oxidant
• Affects oxide growth rate during Linear
Stage

 The orientation of the silicon crystals impacts the rate of oxide growth during the Linear Stage of oxidation, but not during the
Parabolic Stage.
 As discussed previously, the growth rate during the Parabolic Stage is determined by the oxidant's rate of diffusion through the
silicon dioxide layer, and therefore it is not affected by the silicon crystal orientation.
 The oxide grown during the linear stage of oxidation is greatly influenced by the crystal orientation of the wafer because the oxide
growth rate is based on the number of atoms available to react with the oxidants.
 The wafer having the most atoms available for reaction with the oxidant has a faster oxide growth rate. The silicon crystals in
<111> wafers are parallel to the wafer surface, making them readily available to react with the oxidant. The angle the silicon crystals
make with the wafer surface in <100> wafers limits their availability for reactions.
Effect of High Pressure Oxidation
Atmospheric pressure
- Slow oxide growth rate
• An increase in pressure increase oxide growth rate
• Increasing pressure allows temperature to be ..decreased
- Oxide growth rate remains the same
- For every 10atm of pressure the temperature can be reduced 30°C
•Dry Thermal oxidation
- Pressure in oxidation tube increased
• Wet Thermal oxidation
- Steam pressure introduced into oxidation tube

Oxidation of silicon can occur under atmospheric or high-pressure conditions. Under atmospheric conditions,
the oxide grows at a slow rate. As the pressure increases, the oxide growth rate increases, during both the
Linear and Parabolic Stage of oxidation. By increasing the pressure during oxidation, the temperature can be
decreased and less strain placed on the wafer. By lowering the temperature and increasing the pressure, the
oxide growth rate remains the same. For every increase of 10 atm of pressure the temperature can be
reduced by 30ºC.
During wet oxidation, steam pressure is used. Steam pressure, generated in a high-pressure steam
generator that is external to the furnace, is then introduced into the oxidation tube. Pyrogenic steam can also
be used. Pyrogenic steam requires pressurizing water and oxygen to more than 25 atm and then pumping
the steam into the process tube.
Chlorine added with Oxidants
Chlorine species
- Anhydrous chloride (CI2)
- Anhydrous hydrogen chloride (HCI)
- Trichloroethylene – TCE
- Trichloroethane – TCA
• Oxide growth rate increases
• Oxide cleaner
• Device performance is improved

Chlorine can be added to the process as anhydrous chlorine (Cl2), or anhydrous hydrogen chlorine (HCl).
Anhydrous hydrogen chlorine is very corrosive, therefore substitute chemicals, such as trichloroethylene
(TCE) or trichloroetheane (TCA) are often used. Although both trichloroethylene (TCE) and trichloroethane
(TCA) produce high quality oxides, their use is limited because TCE is carcinogenic and TCA turns into a
poisonous gas at high temperatures. Chlorine can be added to the oxidation tube to improve the cleanliness
of the oxide, increase the oxide growth rate, and improve the performance of the device. As chlorine is
added with oxygen to the tube furnace, the oxide growth rate during the Parabolic Stage increases.
Chlorine in the oxidation tube also reacts with any heavy metals present and prevents them from
contaminating the oxide. When chlorine is used in the oxidation process, performance of the device is
improved for the following reasons: the mobile ionic charge in the silicon dioxide layer is reduced; structural
defects in the silicon dioxide and silicon are reduced; and the number of charges at the oxide/silicon
interface are decreased.
.
Oxidation With Cl Containing Gas
Local Oxidation of Si (LOCOS)
Local Oxidation
Dopant Redistribution During Thermal
Oxidation (1)
 What happens to the impurities in the wafer?
 These will be redistributed in a way which reflects whether or not
they are more likely to "dissolve" in the oxide or the silicon.
 The redistribution occurs close to the oxide-silicon interface, and
is influenced by temperature, the relative diffusion rates of the
impurity in Si and SiO2, and the oxide growth rate.
 The redistribution is described by a coefficient, m, known as the
segregation coefficient.

 In very broad terms, if m > 1, the impurities will stay in the silicon, while
if m < 1, the impurities will be taken up in the oxide. The effect of
segregation on the impurity concentration profile after oxidation is
illustrated in the figure.

 Thus, for m > 1, the impurity concentration close to the oxide-silicon

interface is enhanced, while for m < 1, the concentration is depleted
below its bulk value.
Dopant Redistribution During Thermal Oxidation (2)

Dopants affect device performance

- The change in dopant location and concentration during oxidation can affect
the device operation
- N-type dopants move deeper into silicon so high concentration at
the silicon/silicon dioxide interface
- P-type dopants move into the silicon dioxide and deplete the silicon
layer
Oxidation affects the electrical performance of the semiconductor device as well. N-type
dopants have a higher solubility in silicon (Si) than in silicon dioxide (SiO2). Therefore as the
silicon dioxide (SiO2) layer grows during oxidation, the N-type dopants (phosphorous,
arsenic, antimony) move into the silicon (Si) layer and away from the oxide layer. This results
in a higher concentration level of N-dopants in the silicon (Si) layer, and a build up of N-
dopants between the silicon (Si) and silicon dioxide (SiO2) layer. On the other hand, P -type
dopants (boron (B)) are drawn into the silicon dioxide layer and actually deplete the silicon
(Si) layer of P-dopants. Since the location and concentrations of dopants can affect the
performance of a device, the movement of dopants during oxidation must be monitored.
Upon completion of the oxidation process, wafers undergo inspection techniques that
evaluate the location and concentration of dopants to ensure that the functioning of the
device will not be disrupted.
• Oxidation affects the electrical performance of the semiconductor device as well.

• N-type dopants have a higher solubility in silicon (Si) than in silicon dioxide (SiO2).
•

• Therefore as the silicon dioxide (SiO2) layer grows during oxidation, the N-type dopants
(phosphorous, arsenic, antimony) move into the silicon (Si) layer and away from the oxide layer.
This results in a higher concentration level of N-dopants in the silicon (Si) layer, and a build up of
N-dopants between the silicon (Si) and silicon dioxide (SiO2) layer.

• On the other hand, P -type dopants (boron (B)) are drawn into the silicon dioxide layer and
actually deplete the silicon (Si) layer of P-dopants. Since the location and concentrations of
dopants can affect the performance of a device, the movement of dopants during oxidation must
be monitored. Upon completion of the oxidation process, wafers undergo inspection techniques
that evaluate the location and concentration of dopants to ensure that the functioning of the device
will not be disrupted.
Oxide inspection techniques

Surface Inspection
Oxide Thickness
Oxide Cleanliness
DIFFUSION
Dope semiconductor
• Two way to dope

• Diffusion
• Ion implantation

26
 Dope Semiconductor: Diffusion
• Isotropic process

• Can’t independently control dopant profile

and dopant concentration

• Replaced by ion implantation after

its introduction in mid-1970s.
27
 Dope Semiconductor: Diffusion

• First used to dope semiconductor

• Performed in high temperature furnace
• Using silicon dioxide mask
• Still used for dopant drive-in
• R&D on ultra shallow junction formation.

28
Dopant Oxide Deposition

Deposited Dopant Oxide

SiO2

Si Substrate

29
Oxidation

SiO2

Si Substrate

30
Drive-in

SiO2
Doped junction
Si Substrate

31
Strip and Clean

SiO2
Doped junction
Si Substrate

32
 Diffusion Phenomena
 Diffusion is a process of mass transport by atomic
movement under the influence of thermal energy and a
concentration gradient.
Atoms move from higher to lower concentration region.
If this movement is from one element to another e.g. Cu
to Ni, then it is termed inter-diffusion. If the movement
is within similar atoms as in pure metals, it is termed self-
diffusion
https://www.youtube.com/watch?v=mvZ1dJuv
enw
 Requirements to package
• Protect circuit from external environment
• Protect circuit during production of PCB
• Mechanical interface to PCB
• Interface for production testing
• Good signal transfer between chip and PCB
• Good power supply to IC
• Cooling
• Small
• Cheap
 Materials
• Ceramic
– Good heat conductivity
– Hermetic
– Expensive ( often more expensive than chip itself !)
• Metal (has been used internally in IBM)
– Good heat conductivity
– Hermetic
– Electrical conductive (must be mixed with other material)
• Plastic
– Cheap
– Poor heat conductivity
Can be improved by incorporating metallic heat plate.
 Cooling
• Package must transport heat from IC to
environment
• Heat removed from package by:
– Air: Natural air flow, Forced air flow
improved by mounting heat sink
– PCB: Transported to PCB by package pins
– Liquid: Used in large mainframe computers

Resistive equivalent

Heat sink
IC dice Package
I = heat power
V= temperature
R = K/watt

PCB
• Package types: 60 layers MCM substrate

– Below 1 watt: Plastic

– Below 5 watt: Standard ceramic
– Up to 30 watt: Special

Active heat sink Water cooled mainframe computer

Passive heat sink
 Chip mounting
• Pin through hole
– Pins traversing PCB
– Easy manual mounting
– Problem passing signals between pins on PCB (All layers)
– Limited density
• Surface Mount Devices (SMD)
– Small footprint on surface of PCB
– Special machines required for mounting
– No blocking of wires on lower PCB layers
– High density
 Traditional packages
• DIL (Dual In Line) Package inductance:
• Low pin count 1 - 20 nH

• Large
• PGA (Pin Grid Array)
• High pin count (up to 400)
• Previously used for most CPU’s
• PLCC (Plastic leaded chip carrier
• Limited pin count (max 84)
• Large
• Cheap
• SMD
• QFP (Quarter Flat pack)
• High pin count (up to 300)
• small
• Cheap
• SMD
 New package types
• BGA (Ball Grid Array)
• Small solder balls to
connect to board
• small Package inductance:
1 - 5 nH

• High pin count

• Cheap
• Low inductance
• CSP (Chip scale Packaging)
• Similar to BGA but smaller and thinner
• Very small packages
• MCP (Multi Chip Package)
– Mixing of several technologies in same component
– Yield improvement by making two chips instead of one

P6: processor + second level cache

 Chip to package connection
• Wire bonding
– Only periphery of chip available for IO connections
– Mechanical bonding of one pin at a time (sequential)
– Cooling from back of chip
– High inductance (~1nH)

• Flip-chip
– Whole chip area available for IO connections
– Automatic alignment
– One step process (parallel)
– Cooling via balls (front) and back if required
– Thermal matching between chip and substrate required
– Low inductance (~0.1nH)
 TAPE AUTOMATED BONDING
• IC assembly technique based on mounting and interconnecting ICs
on metalized flexible polymer tapes.
• One end fully automated bonding of an etched copper beam lead
to an IC, and other end of the lead to a PWB ( printed wiring board).
• 1966 – commercialized by General Electric Research Laboratory
– First used in small-signal integration devices (1-40 transistors, 14 I/Os)
• 1970 – strong consideration and attention but little experienced
expect in Japan
• 1980 – the most widespread adoption
• Up to now- used in high density I/O and high speed circuitry of VLSI
• Applied to variety of consumer, medical, security computer,
peripheral, telecommunication, automotive and aerospace
products.
 (Dis)advantages
• Some of the advantages of TAB:
– Ability to handle small bond pads and finer pitches on the IC
– Elimination of large wire loops
– Low profile interconnection structures for thin packages
– Improved electrical performance
– Ability to handle high I/O counts
– Reduced weight
• Some of the disadvantages of TAB:
– Package size tends to increase with larger I/O counts
– Little production infrastructure
– Difficulty in assembly rework
– System testability
– Large capital equipment investment required
Structure and Processes
 Electrical performance
• TAB interconnections have improved electrical performance.
• Short circuit lead lengths between the chip and substrate reducing the
impedance and signal delays.
• On the other side, wirebond have long wire loops between the chip and
package lead frame, increasing line impedance and signal delays.

parameter wirebond TAB

Resistance 0.38mΩ 0.31mΩ

Inductance 10nH 6.7nH

Capacitance 0.21pF 0.11pF

 Examples
• Tape Ball Grid Array – developed by IBM.
– Area array first level interconnections and a standard ground plane
– Lower lead inductance, lower power-supply inductance, lower signal
delay
• TapePak – developed by National Semiconductor.
– Fully testable, plastic model, quad-flat-pack
– Leads on all four sides of the surface mountable package
• Pentium TCP – by Intel
– For notebooks, laptops, palm top computers, related portable
products.
• ETA Supercomputer – by ETA Systems
– Implemented one of the first TAB applications in the 1970.
– Packages were 248 pin quad flat packs.
 Summary
• Tape Automated Bonding is an interconnect technology
between the substrate and the IC, using a prefabricated
carrier with copper leads adapted to the IC pads instead
of single wires.
• Today TAB is well introduced in Japan and Taiwan and it features
many benefits in applications like LCD drivers, high speed circuits,
high pin count circuits or very low profile designs.
• Japanese expression created:”Keihakutansho” meaning “light, thin,
short, strong”.
• Has better electrical performance than wirebonding technology.
• Microprocessors and ASICs benefit from TAB in the fields where
high frequencies, high pin counts or high power dissipation are
concerned.
 FLIP CHIP
• Developments to improve cost, reliability and productivity in the
electronic packaging industry – flip chip technology.
• Introduced as the Solid Logic Technology by IBM in 1962.
• In 1970, converted into Controlled Collapse Chip Connection (C4)
• Flip chip = Advanced form of SMT (Surface Mount Technology),
in which bare semiconductor chips
are turned upside down and bonded
directly to PCB.
• Initially applied to peripheral contacts,
but quickly progressed to area arrays
which allow for high I/O counts at
larger pitches.
 Concept
• Flip chip is the connection of an integrated circuit chip to a carrier
or substrate with the active face of the chip facing toward the
substrate.
• The basic structure of flip chip consists of an IC or chip, an
interconnection system, and a substrate.

• The IC can be made of silicon, gallium-arsenide, indium-phosphide.

• Substrate material could be ceramic, epoxy-glass laminate, ceramic
thick-film and many more
 IC Bond Pad Interface
• The interconnection system is subdivided into four functional areas:
– Under bump metallization (UBM)
– Chip bumps
– Encapsulation
– Substrate metallization
 Flip Chip Processing
• Solder Interconnection Processing
– (a) Wetted controlled Collapse solder interconnection
(High Temp.)
– (b) Solid state bond (Similar to wirebonds)
– (c) Cap reflow configuration (Two metals)

• Isotropic and compressed anisotropic Adhesives

 Flip Chip on Organic Substrate
• Benefits
– Cheaper
• Fall backs
– High CTE
– Fatigue
– Bad joints

• IBM and Hitachi discovered that using polymer

underfills reduce strain on solder
Underfill Encapsulants and Processing

• Advantages to underfills
– Compensate for thermal expansion differences
between chip and substrate
– Avoid solder corrosion
– Protect from environmental effects such as
moisture
– Absorb α particle emissions from lead in solder
Flip Chip Assembly Processes
 Electrical Performance
• Flip chip provide shortest chip-to-package
connections
• Minimal resistance
• Minimal capacitance
• Minimal inductance
• Layout and materials effect the performance
 Reliability
• Range from highly reliable to adequate
• Flip chips on ceramic have high reliability
• Underfilled flip chips have better reliability
• Alpha particle emissions (cause soft errors)
• Increased sensitivity to electrostatic discharge
 Failure Modes
• Delamination
– Increases solder joint stress
– Allows solder to move into voids

*C-mode scanning acoustic microscope (C-SAM

 Failure Modes
• Solder migration
– Can cause shorts by bridging
 Failure Modes
• Die cracking
– Catastrophic failure
– Edge cracks
– Center die cracks
 Failure Modes
• Fillet Cracking
– Chip side cracks
– Board side cracks
– Complete cracks
– Can lead to delamination
 Failure Modes
• Solder fatigue cracking
– Can create opens
• Bulk underfill cracking
– Typically between joints
– Potential to cause shorts
 Speed up Flip Chip Process
• Use fast flow snap-cure underfills
• No flow underfills (adhesives)
• Remove steps from standard process
– Do not use flux
– Do not place explicit underfill fillets
 Summary and Future Trends
• Currently wirebonds is the most used
technology
• Currently the flip chip process doesn’t have
the infrastructure to be mass produced
• Flip chip will have the best electrical
characteristics
Yield and Reliability

Class 16
30/10/2021
 Introduction
• In integrated circuit, manufacturing involves
– design,
– fabrication,
– assembly, and
– test processes.

• Besides keeping the facility clean and free-off contamination, the

other aspect is to ensure that each process step conforms to
specifications.
• Thus, it is necessary to implement quality control scheme.
• Quality control monitoring/checking has become an important process
and is normally imposed at the end of certain critical process steps.
Besides the quality control at in process step, quality control procedure is
also required to be implemented at the incoming material inspection
stage
• Monitor the process stability/reliability and
process capability of the machine/equipment
used to process the device
• control static electricity damage to the
integrated circuit by discharging away the
static electricity generated by human being
handling the circuit.
 Yield
• In the modern sub-micron integrated circuit
fabrication, it requires a multimillion dollar
facility that consists of equipment for various
fabrication process steps, cleaning station, and
the source material.
• Beside the equipment, stations, materials are
people who are the working in the facility
• The primary quality requirement for the integrated circuit IC facility is
cleanliness.

• The facility is subjected to too many sources of contaminant, which is

harmful to device under fabrication.

– Contaminant has a size large enough to cover the active area of a sub-micron
device.
– If such type contaminant is resided on the active area of the device during
fabrication, the consequence is malfunction of the device.
– Thus, it is necessary for a modern integrated circuit fabrication facility to keep
the contaminants or particles level below part per million ppm or part per
billion ppb level

• In modern IC facility set-up, it employs three-tiered approaches to control

the particles level and contaminant level, which are clean facility, wafer
cleaning, and gettering
 Reliability
• Reliability
– study of probability that a component such as integrated circuit, equipment, or
system will satisfactorily perform the intended function under given
circumstances, such as environmental conditions, limitations as to operating
time, and frequency, and thoroughness of maintenance, for a specified period of
time.
• An integrated circuit designed for the operation in the space for a period of
15 years and if this integrated circuit can live up with the intended period
then one can say that this integrated circuit is reliable.
• Here
– learn the definition of failure rate, the statistical distribution models used to
calculate the reliability function, the failure rate, and the cumulative fail function
of the device/system.
• The student will also learn the failure rate for the lifetime of the device and
the accelerated test methods used to wipe-out unreliable device earlier
instead of waiting for a long time before failure is shown up under normal
operation conditions.
 Yield loss mechanisms
• Mainly due to three factors:
– Processing problems
– Circuit design problems
– Random point defects in the circuit.
• Processing effects:
– Variation in thickness of oxide or polysilicon layers
– In the resistance of implanted layers
– In the width of features defined by lithography
– Registration of mask with respect to previous masking
operation
• Circuit sensitivity:

– Major reason: not considering variations in device

parameters
– most important parameters for MOS circuit design
• Speed increases as they decrease
• Circuit usually simulated for high speed and low speed conditions.
– Other parameters: resistance of implanted region,
capacitance of conductors to substrate, contact resistance
and leakage current.
– Redesign to compensate for sensitivity parameters results
in high yield and low cost.
• Point defects:
– Region of the wafer where processing is imperfect.
– Causes yield loss even when all processing factors are
with in the expected range.
– Most common is dust or other particles in
environment.
– Can occur on lithography mask as well as on Si wafer.
– Monitoring done using SEM observation of circuit
quality during all fabrication steps.
 Modeling yield-loss mechanism
• Helps predict the cost and availability of
future circuits.
• Processing quality of different process lines
can be compared if yield modeling parameters
are known.
• Most modeling predicts that yield decreases
as area of chip increases.
• Processes can be improved or eliminated once
their yield limiting features are identified.
• Uniform density of point defects:
– If n defects are distributed randomly among N chips,
probability Pk that the given chip contains k defects is
given by binomial distribution

– When N and n are both large and n/N=m remains

finite, this can be approximated to Poisson distribution:

– Probability that chip contains no defects:

– Probability that chip contains one defect:
 Failure distribution, reliability, and failure
rates
• Reliability: probability that the item will perform
a required function under stated conditions for
stated period of time.
– Required function: satisfactory and unsatisfactory
operation(failure)
– Stated condition: physical environment, mechanical,
electrical and thermal conditions expected
– Stated period of time: time during which satisfactory
operation is required. Vary depending on usage of
system.
• CDF (common distribution function):
– Suppose a system is operating at t=0
– Probability that the device will fail at or before time t is given by the
function F(t).

• Reliability function R(t):

– Probability that the device will survive to time t without failure

• Failure rate:

• MTTF (mean time to failure):

– Device’s average age at failure for a population whose reliability is represented
by R(t) with pdf f(t)
Common Distribution Functions
• Initially failure rates are high, but decreases with time:
Early failure.
– Due to manufacturing defects.
• Low and constant rates during mid-life
– Failure due to unrelated causes
• Wear-out period towards the final stage
– Reasons like corrosion
• Exponential distribution function:
– Characterized by constant failure rate over the lifetime of the device.

– Weibull Distribution Function: failure rate varies as a power of device

age

  1
 (t )  t


• β<1 : early failure period

• β>1 : wear-out period.
• β=1 : constant failure rate. Exponential
distribution is a special case of
Weibull distribution.
• Duane plotting:
– graphical analysis technique.
– Evaluation of prototype systems.
– Plots log of average failure rate vs log time.
• Log normal distribution function:
– Used successfully over long periods of time.
1  1  ln t    2 
f (t )  exp     
t 2  2    
 1 1 t  
2

t50  e 
1
 exp    ln  
t 2  2   t50  
 Two failure populations
• Failure rate study is complicated due to the
existence of multiple failure mechanisms.
• Can use log normal distribution
– σ, µ: different for each mechanism.
• Two modes:
– Short median life.
• Small percentage of total population: sport population.
• Represents early failure mechanism.
– Long median life
• Represents steady state failure mechanism.
 Accelerated testing:
• Under normal operating condition, the time
required to observe failure in a device is very
high.
• Accelerated testing: to study the failure chara by
accelerating the mechanisms that cause devices
to fail.
– Temperature
– Voltage
– Current
– Humidity
– Temperature cycling
 Temperature acceleration
• Major cause of failure: chemical, physical
processes.
• Accelerated by temperature.
• If R is the reaction rate at which these
processes proceed,

• Assumes failure reaction is linear in time.

Voltage and current acceleration
• Accelerates failure caused by dielectric breakdown,
interface charge accumulation, charge injection, corrosion.
• Variations applicable for voltage is limited as most ICs
doesn’t work properly if applied voltage is beyond the
specified range.
• Studies indicate that R of failure mechanism is
proportional to a power of applied voltage.

• Different stages in case of dielectric breakdown. Operation

at an increased voltage is more in the nature of burn-in.
• Current acceleration: for failure due to electromigration.
Same relationship for R as above.
 Stress dependent activation energy.

• Eyring model: to understand thermally and

stress activated failure mechanisms.
– Assumes that the energy required for the reaction
to take place is affected by applied stress(V or I).

 a (T ) S   Q 
R sinh   exp  
 kT   kT 
a (T )  kT (T )
Q  Ea 0  a (T ) S B
 Humidity-Temperature acceleration
• Possible failure mechanism: presence of water
vapor in the chip.
– Permeates plastic packaging material in two steps
• Transports contaminants from the surface of package
through plastic and leaches impurities from packaging
material itself.
• Diffusion of contaminated water vapor through
passivation layer of chip. Slow process. Determines
reaction rate of failure mechanism.
• Causes electrochemical corrosion.
 Burn-in
• Manufactured device shows existence of early
failure.
• Photoresist or etching defects (open or shorts).
• Contamination on chip or in package
• Scratches.
• Weak chip or wire bonds
• Partially cracked chip or package
• Burn-in: operation of device for a period of time
during which most of the devices subjected to
early failure actually fails.
• Acceleration depends on mechanism contributing
to early failure.
 Failure mechanisms
• Electrostatic discharge damage:
• Voltages higher than breakdown voltage of gate oxide may
be placed on the device during handling.
• Major source: triboelectricity.
• Burn-in cannot reduce this. Actually can increase early
failure rate.
• Input and output terminals are designed with protection
network to provide path for discharge of current and
protect gate oxide.
• Alpha particle induced soft errors:
• Emitted by U and Th occurring in packaging materials.
• Soft errors: random failure not related to physically
defective device.
• Eg: Loss of information stored.
 Failure Rate
• Failure Rate
– A system such as a calculator that made of many
semiconductor devices is put in operation for the
purpose of calculation, would have a certain failure
rate ,
– which means it may fail after certain number of
operating hour. Thus, a calculator (system) has failure
rate with respect to operating time. The question is if
such failure is acceptable to end-user.
–
A certain failure rate of the system in a commercial aircraft is it acceptable to air
travelling passengers?
• If the unit of failure is defined to be 1 Failure Unit = 1
FIT = 1 Failure/10-9 Device-hour
If one now considers a system that has 225 integrated
circuits and the failure rate of integrated circuit is 100 FIT.
One can calculate the mean time to a failure
Thus,
Period of operation< 1
Failure/ No of transistor x  =
1Failure/225 x100 x 10-9 = 4.44x104 hrs, which
is equal to 5.13 years.
• The percentage of failure per month shall be
100x10-9 x225x720x100% = 1.62%.
• Based on the above discussed example, one would see that it is
time consuming before a failure is shown out. We cannot be waiting
for 5.13 years to see a failure is shown out to calculate the failure
rate of a system.
• One ought to have a developed method by sample testing to
predict the failure rate of the system. In this section, it discusses the
methods to quantitatively measure and predict device failure rate,
and to identify and eliminate the failure mechanism.

• If a device or system is operating at time t = 0. The probability that

the device will fail at or before time t is given by the function F(t).
This is a cumulative distribution function cdf with the following
properties.
•

The reliability function R(t) is a probability that the device will

survive to time t without failure. Thus, the reliability function
R(t) is related to fail function by equation below
 R(t) = 1- F(t)
• The derivative of fail function F(t) with respect
to time is known as the probability density
function pdf and is represented by f(t). Thus,
the pdf is related to the cdf by
F(t) =d/dt F(t)
or the cumulative function
• Similarly the reliability function

And

The term failure rate is referred to as instantaneous fail rate and not average

The fraction of devices that are good at time t and that fails by time t+Δt is given by
F(t+t) –F(t) = R(t) – R(t+  t)
The average failure rate during the time interval  is given by
Average failure rate =1/  (R(t) – R(t+ t)/R(t)
In the limit as  approaches zero, this becomes the instantaneous failure rate () (t), which is
given by

Integrating equation it becomes

Thus, the reliability function R(t) is given by

A common measure of reliability is the mean time to failure

(MTTF) of the device or system, which is defined as

MTTF is the device’s average age at failure for a population whose

reliability function is R(t) with probability density function f(t).
• During the early life of the device, the failure rate is high but it decreases as
time passed. The failure during this period is called infant mortality failure.

• The causes of the early failure are generally fabrication and assembly
related defects such as wire problem, micro-crack, over etch, photoresist
residue, contamination, electrostatic defect etc. The defects can be wiped
out by accelerated life test and followed by a final test to segregate them.
•
• The steady useful life period, the failure rate is normally low and the rate of
failure is also fairly constant. Device failure in this period is a result of a
large number of fabrication and assembly unrelated causes such as
mishandling, applying wrong stimulant etc.

• The wear out period is the old age period, whereby the device has reached
the end of its life.
• The steady useful life period, the failure rate is
normally low and the rate of failure is also fairly
constant.

• Device failure in this period is a result of a large

number of fabrication and assembly unrelated
causes such as mishandling, applying wrong
stimulant etc. The wear out period is the old age
period, whereby the device has reached the end of
its life
 Problems
1. A disk drive's MTBF number may be 1,200,000 hours
and the disk drive may be running 24 hours a day, seven
days a week. One year has 8,760 hours. Calculate the
percentage failure? ( Ans-0.73%)
• A disk drive's MTBF number may be 700,000 hours and
the disk drive may be running 2400 hours a year.
Calculate the percentage failure ? ( Ans-0.34%)
2. Define the following terms: Failure Rate; Cumulative
distribution function; Density function; Mean time
between failure. 3
3. Define the relationship between cumulative
distribution function (cdf) F(t) and the density function
f(t).