MOS Capacitor Deeep Trench Isolation for CMOS Image Sensors

N. Ahmed1,2, F. Roy1, G-N.Lu

1,3
2
,B
B. Mamdy
3
1,2
, J-P. Carrere1,1A. Tournier11, N. Viro
ollet11, C. Perrot1,
M. Rivoire , A. Seiggnard , D.Pellissier-Tanon , F. Leverd , B. Orlan ndo
1
STMicroelectroonics, 850, rue J. Monnet, BP. 16, 38921 Crolles, France
2
INL-UUMR5270, CNRS, Villeurbanne, F-69622, France
3
CEA-LETI, 17 rue des Martyrs, 38054 Grenoble, Cedex 9, France
Tel : (+333) 4-3892-2741, E-mail: [email protected]

Abstract structure. TCAD simulations have been performed on four

pixel configurations for comparisoon: (a) DTI with SWI and
This paper proposes the integration of MOS Capacitor Deep additional shallow sidewall imp plantation (SSWI) around
Trench Isolation (CDTI) as a solution to boosst image sensors’ photodiode (PD); (b) CDTI with SW WI and SSWI; (c) DTI with
pixels performances. We have investigatted CDTI and SWI only; (d) CDTI with neither SWI nor SSWI. It is noted
compared it to oxide-filled Deep Trench Isolation (DTI) that the additional SSWI serves to stop spreading of PD
configurations, on silicon samples, with a fabrrication based on depletion region to SW interface.
TCAD simulations. The experiment measureements evaluated
on CDTI without Sidewall Implantation (SW WI) exhibit very
STI Formatio
on
low dark current (~1aA at 60°C for a 1.4µ µm pixel), high
full-well capacity (~12000e-), and it shows quaantum efficiency
CDTI Patterning
improvement compared to DTI configuratioon. Pixels with
optimized CDTI gate oxide thickness havve demonstrated
CDTI Side-W
Wall
comparable angular response to oxide-filled DT TI counterparts. Implantatio
on
(Optional))
Introduction
CDTI Gate-Oxide
e liner
With the continuous scaling down of pixel size of CMOS
image sensors (CIS) [1], the crosstalk issue bbecomes critical. CDTI doped Poly-Silicon
One solution is to introduce Deep Trench Isolation (DTI) n
deposition
between pixels, which suppresses electrical crrosstalk resulting
from diffusion of photo-generated carriers andd reduces optical CDTI Poly-Silicon
n CMP
crosstalk thanks to the pixel Sidewall (SW)) acting as light
guide [2-5]. However, DTI integration in thhe pixel presents Further step
ps:
Surface MOS formmation
Si/SiO2 interface, which should be passivatedd by pinning the
silicon surface Fermi level (Ef) close to either valence band or n process flow
Fig.1: CDTI-integration
conduction band. To do so, Sidewall Implanntation (SWI) is
currently used [6]. However, it is difficult to obtain a desired
doping profile for the DTI due to its very laarge aspect ratio.
Moreover, SWI will also affect other pixel’s performances
such as Full-Well Capacity (FWC) and tthe size of the
collecting region of photo-generated carriers.
We propose here an alternative by integrating MOS Capacitor
Deep Trench Isolation (CDTI), which is aalso an efficient
solution for crosstalk problem. It allows activve SW interface
passivation by biasing the CDTI in accum mulation regime,
without the need of SWI. Accordingly, better performances (b)
can be achieved.

Innovative solution and its integration

The proposed CDTI consists in filling trencches with doped

poly-silicon. Its fabrication steps are inserted in front-end CIS
process, as shown in Fig. 1. It should be meentioned that no (a)
extra mask is needed for the CDTI integration compared to the Fig.2: Cross-section of fabricated pixel with
h CDTI, a)Using Scanning Electron
DTI one. Fig. 2 shows a fabricated CDT TI 1.4-µm pixel Microscope(SEM), b)Using Transmission Electron
E Microscopy(TEM)

978-1-4799-8001-7/14/$31.00 ©2014 IEEE 4.1.1 IEDM14-80

 Fig. 3 presents doping profile (in color change) of these four Pixels designs corresponding to these four configurations have
configurations. Fig. 4a draws simulated distributions of hole then been fabricated and characterized. Fig. 5 shows that
density near SW interface for these configurations. Thanks to CDTI allows a clear improvement in the statistical
MOS effect, CDTI (in accumulation) configurations provide a distributions of pixel dark current (Idark). In CDTI
much higher hole density at SW interface than DTI. In case of configurations, Idark is monitored by the CDTI gate bias voltage
CDTI without SWI, the hole population is concentrated at the (Fig. 5b). It is minimized to only 1aA at 60°C when MOS
interface, leaving a larger region for collection of CDTI is in strong accumulation mode. These CDTI
photo-generated carriers. Fig. 4b shows the flat-band voltage configurations, even without SW Implantations, have much
(VFB) at which holes start to be well accumulated at the lower Idark than DTI counterparts. This may be explained by
Interface. better active SW electrical passivation created by pinning the
Ef due to much higher interface hole density.
Cut X-X Cut X-X 1.4
PD @VCDTI=-1V
PD
SSWI 1.2 CDTI
SSWI DTI+SWI+SSWI
CDTI+SWI+SSWI DTI+SWI

Normalized pixel population

1.0
SWI DTI CDTI
CDTI
SWI DTI
Si-substrate Si-substrate 0.8
(a) (b)
Cut X-X
0.6
Cut X-X

PD PD
0.4

0.2
SWI DTI CDTI
Si-substrate Si-substrate 0.0
0 0.2 0.4 0.6 0.8
(c) (d)
Normalized dark current (a)
Fig.3: 3D-TCAD simulation, doping profiles are calibrated by secondary ion
mass spectroscopy (SIMS), a) DTI+SWI+SSWI, b) CDTI+SWI+SSWI, c) 100
DTI+SWI, d) CDTI
1.2
@VCDTI=-1V DTI+SWI
dark current (aA) @60°C
Normalized hole density

1 CDTI+SWI+SSWI DTI
CDTI
CDTI
0.8
Oxide 10 DTI+SWI+SSWI
Si-substrate at
0.6
interface
0.4 CDTI
DTI+SWI+SSWI CDTI+SWI+SSWI
0.2 DTI+SWI CDTI
DTI
(Idark =1aA)
0
1
1.25 1.26 1.27 1.28 1.29 1.3
Cut x-x (µm) (a) -1.5 -1.0 -0.5 0.0
VCDTI (V) (b)
Fig. 5: Statistical distributions of pixel dark current: a) @ VCDTI=-1V, b)
1.1 dark current VS.VCDTI @ 60°C
CDTI
Normalized hole density

CDTI+SWI+SSWI
0.9 CDTI
0.7
From Fig. 6, we can see that the DTI with only SWI
0.5 DTI+SWI+SSWI configuration has activation energy (Ea) of 0.68eV, indicating
0.3 dominant thermal generation mechanism of dark current due to
DTI
DTI+SWI a depleted interface.
0.1 This finding is consistent with Fig. 3c & 4a. It accounts for a
-0.1
Accumulation VFB Depletion much higher Idark level as shown in Fig. 5.The three other
- 1.5
- 0.5 0.0 - 1.0 configurations have an Ea of 1.1eV, which implies dominant
VCDTI (V) (b) diffusion mechanism of Idark, and good interface holes
Fig.4: 3D –TCAD simulation of hole density near deep trench Interface accumulation.
Si/Sio2@Z=-0.2µm: a) @VCDTI=-1V, b) In function of VCDTI

IEDM14-81 4.1.2
 80 70 60 T (°C) 50 40 30
6 14000
@VCDTI=-1V
LN [dark current(aA)]

5
DTI+SWI 12000
4
Ea=0.68ev
3
DTI 10000

Full Well Capacity(e-)

2
1 DTI+SWI+SSWI X2
0 Ea=1.1ev 8000
-1 CDTI
6000
-2 CDTI+SWI+SSWI CDTI
-3 Ea=1.1ev 4000
-4
32.8 33.8 34.8 35.8 36.8 37.8 2000
q/KT (ev)-1 (a)
0
1.2

DTI+SWI+SSW
CDTI+SWI+SS

CDTI

DTI+SWI
1.1
Activation Energy(ev)

WI
CDTI

I
1 CDTI+SWI+SSWI
DTI+SWI+SSWI
0.9

0.8 Fig.8: Full well capacity @VCDTI=-1V

DTI+SWI
0.7
Fig. 9 compares, in terms of quantum efficiency (QE), two
0.6
selective configurations: DTI with SWI and SSWI versus
-0.5 0 -1.5 -1 CDTI alone. QE for CDTI is 6% better for blue and 3% for
VCDTI (V) (b)
Fig. 6: Activation energy (Ea) measurements, with temperatures ranging from green, than the DTI with SWI and SSWI. This difference may
30 to 80°C: a) @VCDTI=-1V, b) Ea VS.VCDTI be explained by SWI effect on the collection efficiency of
photo-generated carriers.
The evolution of Ea versus VCDTI confirms that the transition
from depleted interface towards a hole accumulated SW : CDTI
occurs around VCDTI=VFB (Fig. 6b). - - - : DTI+SW+SSWI
+6%
Fig. 7 exhibits the transfer characteristic of the four +3%
Quantum Eefficiency

configurations. Both CDTI and DTI without SSWI have

doubled FWC compared to the two other configurations:
~12000e- vs ~6000e- (Fig. 8). This means that SSWI degrades
FWC of the PD by restricting its extension region.

CDTI
1
Normalized output swing

DTI+SWI w/o SSWI

0.8

0.6 CDTI+SWI+SSWI with SSWI

410 460 510 560 610 660
LAMBDA(nm)
0.4 DTI+SWI+SSWI

Fig. 9: QE curves comparison between with CDTI and with DTI+SWI+SSWI.

0.2 Clear gain without crosstalk problem is observed

0 Process optimization targeting optical crosstalk through

0.0 0.1 0.2 0.3 0.4 0.5 frustrated reflection has also been carried out. Fig. 10b shows
Exposure Time (s) angular response of the CDTI configuration with two oxide
Fig.7: Transfer characteristic @VCDTI=-1V thicknesses, in comparison with that of DTI+SWI+SSWI
configuration.

4.1.3 IEDM14-82
 The CDTI outperforms the DTI in all the aspects, with
significant improvements in Idark and FWC.
CDTI (This Work)
DTI+SWI+SSWI [2]
1/SNR10
1

Dynamic 0.5
FWC
range
0

QE_Max 1/Idark
Fig. 11: Overall normalized pixel performances
Fig. 12 presents a picture taken from a CDTI CIS, which
integrates, for the testing, different parametric variations,
including off-axis variations of optical components.
(a)
Radially-shifted micro-lenses
1.2
V01
DTI+SWI+SSWI 1.1 CDTIox=19nm
V02
V03
Angular Response

1
V04

0.9 …
…
0.8 …
…
0.7 …
CDTIox=10nm V12
0.6 Fig. 12: Example image from an R&D test chip with different
parametrical variations, including off-axis variations of optical
-25 -15 -5 5 15 25 components
Angle of source (degree)
(b) Conclusion
1.2 CDTI@Ox=10nm In this paper the successful integration of CDTI has been
CDTI@Ox=19nm reported, featuring accumulation-biased active SW interface
Normalized Acceptance Angle

1 DTI+SWI+SSWI passivation which allows much lower dark current with

0.8
improved full-well capacity and quantum efficiency, compared
to oxide-filled DTI. CDTI with optimized gate oxide thickness
@ 80% of AR

0.6 is as efficient as DTI to deal with crosstalk. This technology is

promising to boost the performance of different pixel types and
0.4 sizes, especially below 1µm pixel pitch.
0.2
References
0
[1] J.C. Ahn, et al., “Advanced Image Sensor Technology for Pixel Scaling
BLUE GREEN RED
(c) Down Toward 1.0µm,”IEDM, pp.275-278, 2008.
[2] A. Tournier et al., “Pixel-to-Pixel Isolation by Deep Trench Technology:
Fig. 10: a) Cross-section of fabricated CDTI with the two oxide Application to CMOS Image Sensor,” IISW, 2011.
thicknesses, b) Acceptance Angle curves for GREEN pixels, [3]Koen De Munck et al., “Backside Illuminated Hybrid FPA achieving Low
c) Normalized acceptance angle calculated at 80% of angular response Cross-Talk combined with High QE,” IISW, 2011.
[4] Y. Kitamura et al., “Suppression of Crosstalk by Using Backside Deep
Trench Isolation for 1.12µm Backside Illumination CMOS Image Sensor,”
As in Fig. 10b&10c, optimized CDTI with 19nm gate oxide
IEDM,pp.24.2.1-24.2.4, 2012.
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filling. It should be mentioned that results previously shown
3DBackside-Illuminated 1.12ìm Pixel with Front-Side Deep-Trench Isolation
on the CDTI configuration correspond to the optimized 19 nm
and Vertical Transfer Gate, ”ISSCC, pp.124-125, 2014.
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IEDM14-83 4.1.4