The von Neumann Computer ARCHITECTURE

1. The von Neumann Computer Model

 Von Neumann computer systems  The following block diagram shows major
contain three main building relationship between CPU components:
blocks:
o the central processing unit
(CPU),
o memory,
o and input/output devices
(I/O).
 These three components are
connected together using
the system bus.
 The most prominent items within
the CPU are the registers: they
can be manipulated directly by a
computer program.

2. Components of the Von Neumann Model

1. Memory: Storage of  The von Neumann Machine:

information (data/program)
2. Processing Unit:
Computation/Processing of
Information
3. Input: Means of getting
information into the
computer. e.g. keyboard,
mouse
4. Output: Means of getting
information out of the
computer. e.g. printer,
monitor
5. Control Unit: Makes sure
that all the other parts
perform their tasks correctly
and at the correct time.
 3. Communication Between Memory and Processing Unit

 Communication between memory and processing unit

consists of two registers:
o Memory Address Register (MAR).
o Memory Data Register (MDR).
 To read,
1. The address of the location is put in MAR.
2. The memory is enabled for a read.
3. The value is put in MDR by the memory.
To write,
0. The address of the location is put in MAR.
1. The data is put in MDR.
2. The Write Enable signal is asserted.
3. The value in MDR is written to the location
specified.

4. CPU data-path

 Hardware units like ALU's, registers, memory, etc., are linked together into a data-
path.
 The flow of bits around the data-path is controlled by the "gates" which allow the bits
to flow (on) or not flow (off) through the data-path.
 The binary instructions (1 = on; 0 = off) that control the flow are called micro-
instructions.

 Simplified x86 data path :

5. Memory Operations

 There are two key operations on memory:

1. fetch( address ) returns value without changing the value stored at that address.
2. store( address, value ) writes new value into the cell at the given address.
 This type of memory is random-access, meaning that CPU can access any value of the array at
any time (vs. sequential access, like on a tape).
 Such memories are called RAM (random-access memory.)
 Some memory is non-volatile, or read-only (ROM or read-only memory.)

 Memory Operations:
6. Understanding the MAR and the MDR

 MAR stands for memory address register:  Memory Circuitry:

o MAR is connected to the address
bus.
o MAR is "the only way" for the CPU
to communicate with address bus.
o Tri-state buffer between MAR and
the address bus prevents MAR from
continously dumping its output to
the address bus.
o MAR can hold either an instruction
address or a data address.
 MDR Stands for memory data register.
o MDR is connected to the data bus.
o Data can go in both directions: to
and from memory,
 therefore, MDR can load its
data from
 the data bus (for
reading data)
 one of the CPU
registers (for storing
data.)
o A 2-1 MUX circuit selects input
from one of the two.

7. ALU, the Processing Unit

 Processing unit is  The ALU:

hardware that
implements
Arithmetic and
Logical Operations.
 ALU stands
for Arithmetic and
Logic Unit, capable
of performing
 ADD,
SUBTRACT, AND, OR,
and NOT operations.

 The size of input quantities of ALU is often referred to as word length of the computer.
 Many processors today have word length of 32 and 64 bit.
 Processing unit also includes a set of registers for temporary storage of data and memory
addressing.
 8. ALU and the Word Length

 The size of quantities processed by ALU is the word length of the computer.
 The word length does not affect what a computer can compute.
 A computer with a smaller word length can do the same computation as one with a larger
word length...
o ...but it will take more time.
 For example, to add two 64 bit numbers,
 word length = 16 takes 4 adds.
 word length = 32 takes 2 adds.
 word length = 64 takes 1 add.

9. Control Unit

 Manages the Precessing

Unit.
 Implemented as FSM.
 FSM directs all activity.
 Clock-based step-by-step
precessing, cycle-by-cycle.
 FSM is controlled by the
1. Clock signal
2. Instruction Register
3. Reset signal

 Control unit includes

o Instruction Register IR
o Instruction
Pointier IP (aka
Program Counter PC)
 FSM outputs of the control
unit,
 - - - - ->
shown by dash lines,
have two purposes:
1. Control processing
that takes place inside the
ALU.
2. Authorize read/write
gate control of the CPU
data-path.
CPU, memory, Assembly ->
Protected memory.
10. Input/Output

 I/O controller provides the necessary interface to I/O devices.

 Takes care of low-level, device-dependent details.
 Provides necessary electrical signal interface.

11. Input/Output Ports

 Processor and I/O interface points for exchanging data are called I/O ports.
 Two ways of mapping I/O ports:
1. Memory-mapped I/O:
 I/O ports are mapped to the memory address space.
 Reading/writing I/O is similar to reading/writing memory.
 Can use memory read/write instructions.
 Motorola 68000 uses memory-mapped I/O.
2. Isolated I/O:
 Separate I/O address space.
 Intel 80x86 processors support isolated I/O.
 Requires special I/O instructions, like IN and OUT on x86.

12. Input/Output Address Space

 Pentium x86 provides 64 KB of I/O address space.

 Can be used for 8-, 16-, and 32-bit I/O ports.
 Combination cannot exceed the total I/O address space, can have either
o 64 K 8-bit ports
o 32 K 16-bit ports
o 16 K 32-bit ports
o A combination of these for a total of 64 KB.
 I/O instructions do not go through memory segmentation or paging.
 I/O address refers to the physical I/O address.
13. Console Input/Output in Protected Memory Mode

 Using console in Protected  Von Neumann Computer System Block

Memory Mode: Diagram:
o Keyboard input
o Console display output
o Ascii character encoding

14. Instruction Processing

 Central idea of von Neumann model is that both program and data stored in computer
memory:
o Program is a sequence of instructions
o Instruction is a binary encoding of operations and operands:
o For example, an arithmetic expression
 -a + b * c

could be computed by a program with three machine instructions

neg ax ; negate (multiply by -1)
imul bx, cx ; multiply and store result in bx
add ax, bx ; add and store result in ax

where NEG, IMUL, ADD are arithemtic instructions, AX, BX, and CX are
operands.

o Instructions are most basic units of processing.

o Instructions are executed under control of the control unit

15. Instruction Components

 Instruction in memory has two parts: opcode and operands.

 The opcode identifies the operation that instruction does
 The operands are subjects of the operation, such as data values, registers, or memory addresses.
 Due to variety of opcodes and operands, instructions may occupy different sizes of bytes in
memory.
 Instructions with no operands can have implied operands, those that are not explicitly shown.
  Instruction formats:

16. Why Learn Intel x86 ISA ?

 The x86 Intel CPU family is generally classified as a Von Neumann Architecture Machine.
 Most pervasive ISA in the marketplace.
 Opcodes have zero or more operands.
 Instructions and operands have strong support for data types.
 All x86 Assemblers are free, including Microsoft Macro Assembler, MASM.
 Fullscreen 32-bit debuggers WinDbg, OllyDbg, and MS Visual Studio.

17. Design of the x86 CPU Instruction Set

 Instruction set architecture (ISA) is an important design issue for CPU designers:
o caches, pipelining, superscalar implementation can be added to the design later, but
o it is very difficult to change the CPU instructions once in production and people
writing software...
 ...LOOP instruction on the x86 CPU sees very little use in modern high-
performance programs.
 Challenges:
o Expandability is a big concern (predicting future needs.)
o Legacy support is almost the opposite of expandability.
 Each instruction requires some number of transistors on the CPU's silicon die.

18. CPU Instruction Set

 A typical Von Neumann architecture encodes  Instruction decoder:

CPU instructions as numeric values in memory.
 Programming and engineering of the instruction
set is a major task in the CPU design.
 Each instruction needs a unique numeric opcode.

 Instruction formats:
19. History of IBM PC

 Design a simple instruction set to begin with and leave room for later expansion -
o main reason the x86 is so popular and long-lived.
 Intel started with a relatively simple CPU and figured out how to extend the instruction set
to accommodate new features.
 IBM decided that open documentation is a good thing.
 IBM published the IBM PC Technical Reference Manual, with everything the engineers
knew about the machine, which was another reason for the success of the IBM PC
platform.
 See also: 25 Years of the IBM PC and CNN article Meet the inventor of Ctrl-Alt-Delete

20. Early x86 Processor Family

 Intel introduced microprocessors in 1969: 4-bit microprocessor 4004.

 8-bit microprocessors are 8080 and 8085 models.
 16-bit processors:
o 8086 introduced in 1979.
o 20-bit address bus, 16-bit data bus.
 (8088 is a less expensive version.)
o Uses 8-bit data bus.
o Can address up to 4 segments of 64 KB.
o Referred to as the real mode addressing.
o Still fully compatible with modern x86 chips.
21. 8086 and 8088 CPU

 Year 1979 
 The 8088, 8086, and 80286 are 16-bit CPUs.
 Internal registers are 16 bits in size.
 The 8086 is faster than the 8088 because of its 16-bit data bus; the 8088 has
only an 8-bit data bus.
 The 16-bit data bus allows you to use EVEN and ALIGN on an 8086 processor
to word-align data and thus improve data-handling efficiency.
 Memory addresses on the 8086 and 8088 refer to actual physical addresses.
 The 8086 and 8088 have 20 address pins, and 1 megabyte of addressable
memory (which is the real mode segmented memory explained later) requires
addresses of 20 bits in size.
 See also: Brief History of Microprocessors

22. 80186 CPU

 A faster version of 8086.

 16-bit data bus and 20-bit address bus.
 Improved instruction set.
23. 80286 CPU

 Year 1982.
 Introduced protected mode addressing.
 Enhanced with memory protection capabilities with some instructions to control protected
mode.
 Runs faster.
 24-bit address bus.
 16 MB address space.
 Segmentation in protected mode is different from the real mode.
 Allows the operating system to run multiple processes at the same time.
 The 80286 was the minimum for running Windows 3.1 and higher.
 Backwards compatible.

24. 80386 CPU

 Year 1985.
 The 80386 and many of its successors are 32-bit CPUs.
 Internal registers are 32 bits in size.
 Unlike its predecessors, the 80386 processor can handle both 16-bit and 32-bit data.
 Supports entire instruction set of 80286.
 Adds several new instructions as well.
 Software written for the 80286 runs unchanged on the 80386, but the chip is faster.
 The 80386 implements many new hardware-level features, including
o paged memory.
o segmentation can be turned off (flat model).
o support for multiple virtual 8086 processes.
o addressing of up to 4 gigabytes of memory.
o specialized debugging registers.

25. 80386 CPU, Cont.

 32–bit operating systems such as Windows NT required 80386 or higher processor.

 More embedded systems nowdays use the 80386 CPU.
 Examples include:
o high speed data communications devices.
o graphics equipment.
o tra-high-speed data acquisition gear.
o Cockpit displays of some modern jetliners use 80386 as controllers.
 See also: Intel 386 Manuals

26. 80486 CPU

 Year 1989.
 The 80486 processor is an enhanced version of the 80386 with
 o instruction pipelining allows parallel execution capability to instruction decode and
execution units.
o executes many instructions 2-3 times faster.
o achieves scalar execution of 1 instruction per clock cycle.
 The chip incorporates
o math coprocessor for performing floating-point arithmetic
o 8 Kilobyte memory cache.

(The math coprocessor was disabled on a variation of the chip called the 80486SX.)

 New instructions.
 Fully compatible with 80386 software.
 Later versions introduced energy savings for laptops.
 See also: Intel 486 Manuals

27. Pentium (Intel 80586)

 Pentium was introduced in 1993, followed by

o Pentium Pro in 1995,
o Pentium II in 1997,
o Pentium III in 1999,
o Pentium IV 2001.
 Similar to 80486 but with 64-bit data bus.
 Wider internal datapaths: 128- and 256-bit wide.
 Added second execution pipeline.
 Superscalar performance allows two instructions per clock cycle.
 Doubled on-chip level-1 cache:
o one 8 KB for data
o another 8 KB for instructions.
 Added branch prediction.
  See also: Pentium
Manuals

28. Pentium Pro

 Introduced in 1995.
 Three-way superscalar performance, 3 instructions per clock cycle.
 36-bit address bus.
 64 GB address space.
 Introduced dynamic execution:
 o Out-of-order execution.
o Speculative execution.
 In addition to the level-1 cache, has 256 KB level-2 cache.

29. Pentium II

 Introduced in 1997.
 Added multimedia (MMX) instructions.
 Doubled on-chip level-1 cache:
o 16 KB for data
o 16 KB for instructions.
 Introduced comprehensive power management features:
o Sleep
o Deep sleep.
 In addition to the level-1 cache has 256 KB level-2 cache.

30. Itanium processor

 RISC design
o (All previous x86 designs were CISC.)
 64-bit processor
 Uses 64-bit address bus
 128-bit data bus
 Introduced several advanced features:
o Speculative execution
o Predication to eliminate branches
o Branch prediction