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Full Adder - VHDL Code - Testbench - EDA Playground

This document contains VHDL code for a full adder circuit. The code defines a full adder entity with inputs a, b, c and outputs sum and cy. The architecture section describes how sum is calculated as the XOR of a, b, and c, and how cy is calculated as the OR of the ANDs of the input combinations. A test bench is also provided which stimulates the full adder with all possible input combinations over time.

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Vicky Patil
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422 views

Full Adder - VHDL Code - Testbench - EDA Playground

This document contains VHDL code for a full adder circuit. The code defines a full adder entity with inputs a, b, c and outputs sum and cy. The architecture section describes how sum is calculated as the XOR of a, b, and c, and how cy is calculated as the OR of the ANDs of the input combinations. A test bench is also provided which stimulates the full adder with all possible input combinations over time.

Uploaded by

Vicky Patil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FULL ADDER

VHDL CODE
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Fulladder is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : in STD_LOGIC;

sum : out STD_LOGIC;

cy : out STD_LOGIC);

end Fulladder;

architecture Behavioral of Fulladder is

begin

sum<= a xor b xor c;

cy<= (a and b) or (b and c) or (c and a);

end Behavioral;

Test bench
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY Fulladder_tb IS

END Fulladder_tb;

ARCHITECTURE behavior OF Fulladder_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Fulladder

PORT(

a : IN std_logic;

b : IN std_logic;

c : IN std_logic;

sum : OUT std_logic;

cy : OUT std_logic

);

END COMPONENT;
--Inputs

signal a : std_logic := '0';

signal b : std_logic := '0';

signal c : std_logic := '0';

--Outputs

signal sum : std_logic;

signal cy : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Fulladder PORT MAP (

a => a,

b => b,

c => c,

sum => sum,

cy => cy

);

-- Stimulus process

stim_proc: process

begin

a <= '0';

b <= '0';

c <= '0';

wait for 10 ns;

a <= '0';

b <= '0';

c <= '1';

wait for 10 ns;

a <= '0';

b <= '1';

c <= '0';

wait for 10 ns;


a <= '0';

b <= '1';

c <= '1';

wait for 10 ns;

a <= '1';

b <= '0';

c <= '0';

wait for 10 ns;

a <= '1';

b <= '0';

c <= '1';

wait for 10 ns;

a <= '1';

b <= '1';

c <= '0';

wait for 10 ns;

a <= '1';

b <= '1';

c <= '1';

wait for 10 ns;

wait;

end process;

END;

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