0% found this document useful (0 votes)

490 views

Pic16c7x Micro Controller Data Sheet

PIC16C7X 8-Bit CMOS Microcontrollers with A / D Converter Devices included in this data sheet: PIC32C7X PIC32c7x PIC32-c7x. Wide operating voltage range: 2.5V to 6.0V High Sink / Source Current 25 / 25 mA Commercial, Industrial and Extended temperature ranges. Low-power consumption: 2 mA @ 5V, 4 MHz 15 uA typical @ 3V,

Uploaded by

guttajimmy

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

490 views

Pic16c7x Micro Controller Data Sheet

Uploaded by

guttajimmy

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 289

PIC16C7X

8-Bit CMOS Microcontrollers with A/D Converter

Devices included in this data sheet: • Wide operating voltage range: 2.5V to 6.0V
• PIC16C72 • PIC16C74A • High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
• PIC16C73 • PIC16C76
ranges
• PIC16C73A • PIC16C77
• Low-power consumption:
• PIC16C74 • < 2 mA @ 5V, 4 MHz
• 15 µA typical @ 3V, 32 kHz
PIC16C7X Microcontroller Core Features: • < 1 µA typical standby current
• High-performance RISC CPU
PIC16C7X Peripheral Features:
• Only 35 single word instructions to learn
• Timer0: 8-bit timer/counter with 8-bit prescaler
• All single cycle instructions except for program
branches which are two cycle • Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
• Operating speed: DC - 20 MHz clock input
crystal/clock
DC - 200 ns instruction cycle
• Timer2: 8-bit timer/counter with 8-bit period
• Up to 8K x 14 words of Program Memory,
register, prescaler and postscaler
up to 368 x 8 bytes of Data Memory (RAM)
• Capture, Compare, PWM module(s)
• Interrupt capability
• Capture is 16-bit, max. resolution is 12.5 ns,
• Eight level deep hardware stack
Compare is 16-bit, max. resolution is 200 ns,
• Direct, indirect, and relative addressing modes PWM max. resolution is 10-bit
• Power-on Reset (POR) • 8-bit multichannel analog-to-digital converter
• Power-up Timer (PWRT) and • Synchronous Serial Port (SSP) with
Oscillator Start-up Timer (OST) SPI and I2C
• Watchdog Timer (WDT) with its own on-chip RC • Universal Synchronous Asynchronous Receiver
oscillator for reliable operation Transmitter (USART/SCI)
• Programmable code-protection • Parallel Slave Port (PSP) 8-bits wide, with
• Power saving SLEEP mode external RD, WR and CS controls
• Selectable oscillator options • Brown-out detection circuitry for
• Low-power, high-speed CMOS EPROM Brown-out Reset (BOR)
technology
• Fully static design
PIC16C7X Features 72 73 73A 74 74A 76 77
Program Memory (EPROM) x 14 2K 4K 4K 4K 4K 8K 8K
Data Memory (Bytes) x 8 128 192 192 192 192 368 368
I/O Pins 22 22 22 33 33 22 33
Parallel Slave Port — — — Yes Yes — Yes
Capture/Compare/PWM Modules 1 2 2 2 2 2 2
Timer Modules 3 3 3 3 3 3 3
A/D Channels 5 5 5 8 8 5 8
Serial Communication SPI/I2C SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C,
USART USART USART USART USART USART
In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes — Yes Yes Yes
Interrupt Sources 8 11 11 12 12 11 12

 1997 Microchip Technology Inc. DS30390E-page 1

PIC16C7X
Pin Diagrams

SDIP, SOIC, Windowed Side Brazed Ceramic SSOP

MCLR/VPP •1 28 RB7 MCLR/VPP •1 28 RB7

RA0/AN0 2 27 RB6 RA0/AN0 2 27 RB6
RA1/AN1 3 26 RB5 RA1/AN1 3 26 RB5
RA2/AN2 4 25 RB4 RA2/AN2 4 25 RB4
RA3/AN3/VREF 5 24 RB3 RA3/AN3/VREF 5 24 RB3
RA4/T0CKI 6 23 RB2 RA4/T0CKI 6 23 RB2
RA5/SS/AN4 7 22 RB1 RA5/SS/AN4 7 22 RB1
VSS 8 21 RB0/INT VSS 8 21 RB0/INT
OSC1/CLKIN 9 20 VDD OSC1/CLKIN 9 20 VDD
OSC2/CLKOUT 10 19 VSS OSC2/CLKOUT 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7 RC0/T1OSO/T1CKI 11 18 RC7
RC1/T1OSI 12 17 RC6 RC1/T1OSI 12 17 RC6
RC2/CCP1 13 16 RC5/SDO RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA RC3/SCK/SCL 14 15 RC4/SDI/SDA

PIC16C72 PIC16C72

SDIP, SOIC, Windowed Side Brazed Ceramic PDIP, Windowed CERDIP

MCLR/VPP •1 28 RB7
MCLR/VPP 1 40 RB7
RA0/AN0 2 27 RB6 RA0/AN0 2 39 RB6
RA1/AN1 3 26 RB5 RA1/AN1 3 38 RB5
RA2/AN2 4 25 RB4 RA2/AN2 4 37 RB4
RA3/AN3/VREF 5 24 RB3 RA3/AN3/VREF 5 36 RB3
RA4/T0CKI 6 35 RB2
RA4/T0CKI 6 23 RB2
RA5/SS/AN4 7 34 RB1
RA5/SS/AN4 7 22 RB1 RE0/RD/AN5 8 33 RB0/INT
VSS 8 21 RB0/INT RE1/WR/AN6 9 32 VDD
OSC1/CLKIN 9 20 VDD RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
OSC2/CLKOUT 10 19 VSS
VSS 12 29 RD6/PSP6
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT OSC1/CLKIN 28 RD5/PSP5
13
RC1/T1OSI/CCP2 12 17 RC6/TX/CK OSC2/CLKOUT 14 27 RD4/PSP4
RC2/CCP1 13 16 RC5/SDO RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC3/SCK/SCL 14 15 RC4/SDI/SDA RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
PIC16C73 RD0/PSP0 19 22 RD3/PSP3

PIC16C73A RD1/PSP1 20 21 RD2/PSP2

PIC16C76 PIC16C74
PIC16C74A
PIC16C77

DS30390E-page 2  1997 Microchip Technology Inc.

PIC16C7X
Pin Diagrams (Cont.’d)

RC1/T1OSI/CCP2
MQFP

RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK

RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO

NC
44
43
42
41
40
39
38
37
36
35
34
RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKOUT
RD6/PSP6 4 30 OSC1/CLKIN
RD7/PSP7 5 29 VSS
VSS 6 28 VDD
VDD 7 PIC16C74 27 RE2/CS/AN7
RB0/INT 8 26 RE1/WR/AN6
RB1 9 25 RE0/RD/AN5
RB2 10 24 RA5/SS/AN4
RB3 11 23 RA4/T0CKI

12
13
14
15
16
17
18
19
20
21
22
RA3/AN3/VREF
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
NC
NC
RB4
RB5
RB6
RB7

RC1/T1OSI/CCP2
RA3/AN3/VREF

RC3/SCK/SCL
RC4/SDI/SDA
MCLR/VPP

PLCC
RA2/AN2
RA1/AN1
RA0/AN0

RC6/TX/CK

RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO

MQFP
RB7
RB6
RB5
RB4
NC

TQFP
NC
44
43
42
41
40
6
5
4
3
2
1

44
43
42
41
40
39
38
37
36
35
34

RA4/T0CKI 7 39 RB3
RC7/RX/DT 1 33 NC
RA5/SS/AN4 8 38 RB2
RE0/RD/AN5 9 37 RB1 RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RE1/WR/AN6 10 36 RB0/INT RD5/PSP5 3 31 OSC2/CLKOUT
RE2/CS/AN7 11 PIC16C74 35 VDD RD6/PSP6 4 30 OSC1/CLKIN
VDD 12 34 VSS RD7/PSP7 5 PIC16C74A 29 VSS
VSS 13 PIC16C74A 33 RD7/PSP7 VSS 6 28 VDD
OSC1/CLKIN 14 32 RD6/PSP6 VDD 7
PIC16C77 27 RE2/CS/AN7
OSC2/CLKOUT 15 PIC16C77 31 RD5/PSP5 RB0/INT
RB1
8
9
26
25
RE1/WR/AN6
RE0/RD/AN5
RC0/T1OSO/T1CKI 16 30 RD4/PSP4
RB2 10 24 RA5/SS/AN4
NC 17 29 RC7/RX/DT
RB3 11 23 RA4/T0CKI
12
13
14
15
16
17
18
19
20
21
22
18
19
20
21
22
23
24
25
26
27
28
RC1/T1OSI/CCP2

RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1

RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3

RC6/TX/CK
RC5/SDO

RA3/AN3/VREF
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
NC
NC
RB4
RB5
RB6
RB7

 1997 Microchip Technology Inc. DS30390E-page 3

PIC16C7X
Table of Contents
1.0 General Description ....................................................................................................................................................................... 5
2.0 PIC16C7X Device Varieties ........................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................... 9
4.0 Memory Organization................................................................................................................................................................... 19
5.0 I/O Ports....................................................................................................................................................................................... 43
6.0 Overview of Timer Modules ......................................................................................................................................................... 57
7.0 Timer0 Module ............................................................................................................................................................................. 59
8.0 Timer1 Module ............................................................................................................................................................................. 65
9.0 Timer2 Module ............................................................................................................................................................................. 69
10.0 Capture/Compare/PWM Module(s).............................................................................................................................................. 71
11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 77
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ...................................................................................... 99
13.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117
14.0 Special Features of the CPU ..................................................................................................................................................... 129
15.0 Instruction Set Summary............................................................................................................................................................ 147
16.0 Development Support ................................................................................................................................................................ 163
17.0 Electrical Characteristics for PIC16C72 ..................................................................................................................................... 167
18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183
19.0 Electrical Characteristics for PIC16C73A/74A ........................................................................................................................... 201
20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219
21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241
22.0 Packaging Information ............................................................................................................................................................... 251
Appendix A: ................................................................................................................................................................................... 263
Appendix B: Compatibility ............................................................................................................................................................. 263
Appendix C: What’s New............................................................................................................................................................... 264
Appendix D: What’s Changed ....................................................................................................................................................... 264
Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 265
Pin Compatibility ................................................................................................................................................................................ 271
Index .................................................................................................................................................................................................. 273
List of Examples................................................................................................................................................................................. 279
List of Figures..................................................................................................................................................................................... 280
List of Tables...................................................................................................................................................................................... 283
Reader Response .............................................................................................................................................................................. 286
PIC16C7X Product Identification System........................................................................................................................................... 287
For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As
an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and
PIC16C74A devices.
Applicable Devices
72 73 73A 74 74A 76 77

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.

DS30390E-page 4  1997 Microchip Technology Inc.

PIC16C7X
1.0 GENERAL DESCRIPTION 8-bit A/D is provided. The 8-bit resolution is ideally
suited for applications requiring low-cost analog inter-
The PIC16C7X is a family of low-cost, high-perfor- face, e.g. thermostat control, pressure sensing, etc.
mance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converters, in the The PIC16C7X family has special features to reduce
PIC16CXX mid-range family. external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
All PIC16/17 microcontrollers employ an advanced There are four oscillator options, of which the single pin
RISC architecture. The PIC16CXX microcontroller fam- RC oscillator provides a low-cost solution, the LP oscil-
ily has enhanced core features, eight-level deep stack, lator minimizes power consumption, XT is a standard
and multiple internal and external interrupt sources. crystal, and the HS is for High Speed crystals. The
The separate instruction and data buses of the Harvard SLEEP (power-down) feature provides a power saving
architecture allow a 14-bit wide instruction word with mode. The user can wake up the chip from SLEEP
the separate 8-bit wide data. The two stage instruction through several external and internal interrupts and
pipeline allows all instructions to execute in a single resets.
cycle, except for program branches which require two
cycles. A total of 35 instructions (reduced instruction A highly reliable Watchdog Timer with its own on-chip
set) are available. Additionally, a large register set gives RC oscillator provides protection against software lock-
some of the architectural innovations used to achieve a up.
very high performance. A UV erasable CERDIP packaged version is ideal for
PIC16CXX microcontrollers typically achieve a 2:1 code development while the cost-effective One-Time-
code compression and a 4:1 speed improvement over Programmable (OTP) version is suitable for production
other 8-bit microcontrollers in their class. in any volume.

The PIC16C72 has 128 bytes of RAM and 22 I/O pins. The PIC16C7X family fits perfectly in applications rang-
In addition several peripheral features are available ing from security and remote sensors to appliance con-
including: three timer/counters, one Capture/Compare/ trol and automotive. The EPROM technology makes
PWM module and one serial port. The Synchronous customization of application programs (transmitter
Serial Port can be configured as either a 3-wire Serial codes, motor speeds, receiver frequencies, etc.)
Peripheral Interface (SPI) or the two-wire Inter-Inte- extremely fast and convenient. The small footprint
grated Circuit (I 2C) bus. Also a 5-channel high-speed packages make this microcontroller series perfect for
8-bit A/D is provided. The 8-bit resolution is ideally all applications with space limitations. Low cost, low
suited for applications requiring low-cost analog inter- power, high performance, ease of use and I/O flexibility
face, e.g. thermostat control, pressure sensing, etc. make the PIC16C7X very versatile even in areas where
no microcontroller use has been considered before
The PIC16C73/73A devices have 192 bytes of RAM, (e.g. timer functions, serial communication, capture
while the PIC16C76 has 368 byes of RAM. Each device and compare, PWM functions and coprocessor appli-
has 22 I/O pins. In addition, several peripheral features cations).
are available including: three timer/counters, two Cap-
ture/Compare/PWM modules and two serial ports. The 1.1 Family and Upward Compatibility
Synchronous Serial Port can be configured as either a
3-wire Serial Peripheral Interface (SPI) or the two-wire Users familiar with the PIC16C5X microcontroller fam-
Inter-Integrated Circuit (I 2C) bus. The Universal Syn- ily will realize that this is an enhanced version of the
chronous Asynchronous Receiver Transmitter PIC16C5X architecture. Please refer to Appendix A for
(USART) is also known as the Serial Communications a detailed list of enhancements. Code written for the
Interface or SCI. Also a 5-channel high-speed 8-bit A/ PIC16C5X can be easily ported to the PIC16CXX fam-
D is provided.The 8-bit resolution is ideally suited for ily of devices (Appendix B).
applications requiring low-cost analog interface, e.g.
1.2 Development Support
thermostat control, pressure sensing, etc.
PIC16C7X devices are supported by the complete line
The PIC16C74/74A devices have 192 bytes of RAM,
of Microchip Development tools.
while the PIC16C77 has 368 bytes of RAM. Each
device has 33 I/O pins. In addition several peripheral Please refer to Section 16.0 for more details about
features are available including: three timer/counters, Microchip’s development tools.
two Capture/Compare/PWM modules and two serial
ports. The Synchronous Serial Port can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I2C) bus. The Uni-
versal Synchronous Asynchronous Receiver Transmit-
ter (USART) is also known as the Serial
Communications Interface or SCI. An 8-bit Parallel
Slave Port is provided. Also an 8-channel high-speed

 1997 Microchip Technology Inc. DS30390E-page 5

PIC16C7X
TABLE 1-1: PIC16C7XX FAMILY OF DEVCES
PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72(1)
Maximum Frequency 20 20 20 20 20 20
Clock
of Operation (MHz)
EPROM Program Memory 512 1K 1K 2K 2K —
(x14 words)
Memory ROM Program Memory — — — — — 2K
(14K words)
Data Memory (bytes) 36 36 68 128 128 128
Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR0,
TMR1, TMR1,
TMR2 TMR2
Capture/Compare/ — — — — 1 1
Peripherals PWM Module(s)

Serial Port(s) — — — — SPI/I2C SPI/I2C

(SPI/I2C, USART)
Parallel Slave Port — — — — — —
A/D Converter (8-bit) Channels 4 4 4 4 5 5
Interrupt Sources 4 4 4 4 8 8
I/O Pins 13 13 13 13 22 22
Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5

Features In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes
Brown-out Reset Yes — Yes Yes Yes Yes
Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP,
SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP
20-pin SSOP 20-pin SSOP 20-pin SSOP

PIC16C73A PIC16C74A PIC16C76 PIC16C77

Maximum Frequency of Oper- 20 20 20 20
Clock
ation (MHz)
EPROM Program Memory 4K 4K 8K 8K
Memory (x14 words)
Data Memory (bytes) 192 192 368 368
Timer Module(s) TMR0, TMR0, TMR0, TMR0,
TMR1, TMR1, TMR1, TMR1,
TMR2 TMR2 TMR2 TMR2
Capture/Compare/PWM Mod- 2 2 2 2
Peripherals ule(s)

Serial Port(s) (SPI/I2C, US- SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART
ART)
Parallel Slave Port — Yes — Yes
A/D Converter (8-bit) Channels 5 8 5 8
Interrupt Sources 11 12 11 12
I/O Pins 22 33 22 33
Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0

Features In-Circuit Serial Programming Yes Yes Yes Yes

Brown-out Reset Yes Yes Yes Yes
Packages 28-pin SDIP, 40-pin DIP; 28-pin SDIP, 40-pin DIP;
SOIC 44-pin PLCC, SOIC 44-pin PLCC,
MQFP, TQFP MQFP, TQFP

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil-
ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.

DS30390E-page 6  1997 Microchip Technology Inc.

PIC16C7X
2.0 PIC16C7X DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP)
Devices
A variety of frequency ranges and packaging options
are available. Depending on application and production Microchip offers a QTP Programming Service for fac-
requirements, the proper device option can be selected tory production orders. This service is made available
using the information in the PIC16C7X Product Identifi- for users who choose not to program a medium to high
cation System section at the end of this data sheet. quantity of units and whose code patterns have stabi-
When placing orders, please use that page of the data lized. The devices are identical to the OTP devices but
sheet to specify the correct part number. with all EPROM locations and configuration options
For the PIC16C7X family, there are two device “types” already programmed by the factory. Certain code and
as indicated in the device number: prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
1. C, as in PIC16C74. These devices have
Microchip Technology sales office for more details.
EPROM type memory and operate over the
standard voltage range. 2.4 Serialized Quick-Turnaround
2. LC, as in PIC16LC74. These devices have Production (SQTPSM) Devices
EPROM type memory and operate over an
extended voltage range. Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
2.1 UV Erasable Devices grammed with different serial numbers. The serial num-
bers may be random, pseudo-random, or sequential.
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot Serial programming allows each device to have a
programs. This version can be erased and unique number which can serve as an entry-code,
reprogrammed to any of the oscillator modes. password, or ID number.
Microchip's PICSTART Plus and PRO MATE II
programmers both support programming of the
PIC16C7X.

2.2 One-Time-Programmable (OTP)

Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.

 1997 Microchip Technology Inc. DS30390E-page 7

PIC16C7X
NOTES:

DS30390E-page 8  1997 Microchip Technology Inc.

PIC16C7X
3.0 ARCHITECTURAL OVERVIEW PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
The high performance of the PIC16CXX family can be It performs arithmetic and Boolean functions between
attributed to a number of architectural features com- the data in the working register and any register file.
monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which, The ALU is 8-bits wide and capable of addition, sub-
program and data are accessed from separate memo- traction, shift and logical operations. Unless otherwise
ries using separate buses. This improves bandwidth mentioned, arithmetic operations are two's comple-
over traditional von Neumann architecture in which pro- ment in nature. In two-operand instructions, typically
gram and data are fetched from the same memory one operand is the working register (W register). The
using the same bus. Separating program and data other operand is a file register or an immediate con-
buses further allows instructions to be sized differently stant. In single operand instructions, the operand is
than the 8-bit wide data word. Instruction opcodes are either the W register or a file register.
14-bits wide making it possible to have all single word The W register is an 8-bit working register used for ALU
instructions. A 14-bit wide program memory access operations. It is not an addressable register.
bus fetches a 14-bit instruction in a single cycle. A two-
Depending on the instruction executed, the ALU may
stage pipeline overlaps fetch and execution of instruc-
affect the values of the Carry (C), Digit Carry (DC), and
tions (Example 3-1). Consequently, all instructions (35)
Zero (Z) bits in the STATUS register. The C and DC bits
execute in a single cycle (200 ns @ 20 MHz) except for
operate as a borrow bit and a digit borrow out bit,
program branches.
respectively, in subtraction. See the SUBLW and SUBWF
The table below lists program memory (EPROM) and instructions for examples.
data memory (RAM) for each PIC16C7X device.

Program
Device Data Memory
Memory
PIC16C72 2K x 14 128 x 8
PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
PIC16C76 8K x 14 368 x 8
PIC16C77 8K x 14 386 x 8
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (sym-
metrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.

 1997 Microchip Technology Inc. DS30390E-page 9

PIC16C7X
FIGURE 3-1: PIC16C72 BLOCK DIAGRAM

13 Data Bus 8 PORTA

EPROM Program Counter
RA0/AN0
Program RA1/AN1
Memory RAM RA2/AN2
8 Level Stack RA3/AN3/VREF
2K x 14 File
(13-bit) Registers RA4/T0CKI
128 x 8 RA5/SS/AN4
Program 14
Bus RAM Addr(1) 9 PORTB
Addr MUX
Instruction reg
RB0/INT
Direct Addr 7 Indirect
8 Addr

FSR reg RB7:RB1

STATUS reg PORTC

8
RC0/T1OSO/T1CKI
RC1/T1OSI
3 RC2/CCP1
Power-up MUX
RC3/SCK/SCL
Timer RC4/SDI/SDA
Instruction Oscillator RC5/SDO
Decode & Start-up Timer ALU RC6
Control RC7
Power-on
Reset 8
Timing Watchdog
Generation Timer W reg
OSC1/CLKIN Brown-out
OSC2/CLKOUT Reset

MCLR VDD, VSS

Timer0 Timer1 Timer2

Synchronous
A/D Serial Port CCP1

Note 1: Higher order bits are from the STATUS register.

DS30390E-page 10  1997 Microchip Technology Inc.

PIC16C7X
FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM

Device Program Memory Data Memory (RAM)

PIC16C73 4K x 14 192 x 8
PIC16C73A 4K x 14 192 x 8
PIC16C76 8K x 14 368 x 8

13 Data Bus 8 PORTA

Program Counter
RA0/AN0
EPROM
RA1/AN1
Program RA2/AN2
Memory 8 Level Stack RAM RA3/AN3/VREF
(13-bit) File RA4/T0CKI
Registers RA5/SS/AN4
Program 14
Bus RAM Addr(1) 9 PORTB
Addr MUX
Instruction reg
RB0/INT
Direct Addr 7 Indirect
8 Addr

FSR reg RB7:RB1

STATUS reg
8 PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
3 RC2/CCP1
Power-up MUX
RC3/SCK/SCL
Timer RC4/SDI/SDA
Instruction Oscillator RC5/SDO
Decode & Start-up Timer ALU RC6/TX/CK
Control RC7/RX/DT
Power-on
Reset 8
Timing Watchdog
Generation Timer W reg
OSC1/CLKIN Brown-out
OSC2/CLKOUT Reset(2)

MCLR VDD, VSS

Timer0 Timer1 Timer2 A/D

Synchronous
CCP1 CCP2 USART
Serial Port

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C73.

 1997 Microchip Technology Inc. DS30390E-page 11

PIC16C7X
FIGURE 3-3: PIC16C74/74A/77 BLOCK DIAGRAM

Device Program Memory Data Memory (RAM)

PIC16C74 4K x 14 192 x 8
PIC16C74A 4K x 14 192 x 8
PIC16C77 8K x 14 368 x 8

13 Data Bus 8 PORTA

Program Counter
RA0/AN0
EPROM RA1/AN1
Program RA2/AN2
Memory 8 Level Stack RAM RA3/AN3/VREF
(13-bit) File RA4/T0CKI
Registers RA5/SS/AN4
Program 14
Bus RAM Addr (1) 9 PORTB
Addr MUX
Instruction reg
RB0/INT
Direct Addr 7 Indirect
8 Addr

FSR reg RB7:RB1

STATUS reg
8 PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
3 RC2/CCP1
Power-up MUX
RC3/SCK/SCL
Timer
RC4/SDI/SDA
Instruction Oscillator RC5/SDO
Decode & Start-up Timer RC6/TX/CK
ALU
Control RC7/RX/DT
Power-on
Reset 8 PORTD
Timing Watchdog
Generation Timer W reg
OSC1/CLKIN Brown-out
OSC2/CLKOUT RD7/PSP7:RD0/PSP0
Reset(2)

Parallel Slave Port PORTE

MCLR VDD, VSS
RE0/RD/AN5

RE1/WR/AN6
Timer0 Timer1 Timer2 A/D
RE2/CS/AN7

Synchronous
CCP1 CCP2 USART
Serial Port

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C74.

DS30390E-page 12  1997 Microchip Technology Inc.

PIC16C7X
TABLE 3-1: PIC16C72 PINOUT DESCRIPTION
DIP SSOP SOIC I/O/P Buffer
Pin Name Description
Pin# Pin# Pin# Type Type

OSC1/CLKIN 9 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4 7 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 22 I/O TTL
RB2 23 23 23 I/O TTL
RB3 24 24 24 I/O TTL
RB4 25 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI 12 12 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 17 17 I/O ST
RC7 18 18 18 I/O ST
VSS 8, 19 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

 1997 Microchip Technology Inc. DS30390E-page 13

PIC16C7X
TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION
DIP SOIC I/O/P Buffer
Pin Name Description
Pin# Pin# Type Type

OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP 1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2 4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

DS30390E-page 14  1997 Microchip Technology Inc.

PIC16C7X

TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION

DIP PLCC QFP I/O/P Buffer
Pin Name Description
Pin# Pin# Pin# Type Type

OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.

OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0
RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1
RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2
RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference
voltage
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6 39 43 16 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

 1997 Microchip Technology Inc. DS30390E-page 15

PIC16C7X
TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.’d)
DIP PLCC QFP I/O/P Buffer
Pin Name Description
Pin# Pin# Pin# Type Type

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0 19 21 38 I/O ST/TTL(3)
RD1/PSP1 20 22 39 I/O ST/TTL(3)
RD2/PSP2 21 23 40 I/O ST/TTL(3)
RD3/PSP3 22 24 41 I/O ST/TTL(3)
RD4/PSP4 27 30 2 I/O ST/TTL(3)
RD5/PSP5 28 31 3 I/O ST/TTL(3)
RD6/PSP6 29 32 4 I/O ST/TTL(3)
RD7/PSP7 30 33 5 I/O ST/TTL(3)
PORTE is a bi-directional I/O port.
RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave port,
or analog input5.
RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port,
or analog input6.
RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave
port, or analog input7.
VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,28, 12,13, — These pins are not internally connected. These pins should
40 33,34 be left unconnected.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

DS30390E-page 16  1997 Microchip Technology Inc.

PIC16C7X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by An “Instruction Cycle” consists of four Q cycles (Q1,
four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro- pipelined such that fetch takes one instruction cycle
gram counter (PC) is incremented every Q1, the while decode and execute takes another instruction
instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction
latched into the instruction register in Q4. The instruc- effectively executes in one cycle. If an instruction
tion is decoded and executed during the following Q1 causes the program counter to change (e.g. GOTO)
through Q4. The clocks and instruction execution flow then two cycles are required to complete the instruction
is shown in Figure 3-4. (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).

FIGURE 3-4: CLOCK/INSTRUCTION CYCLE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2

OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

 1997 Microchip Technology Inc. DS30390E-page 17

PIC16C7X
NOTES:

DS30390E-page 18  1997 Microchip Technology Inc.

PIC16C7X
4.0 MEMORY ORGANIZATION FIGURE 4-2: PIC16C73/73A/74/74A
Applicable Devices PROGRAM MEMORY MAP
72 73 73A 74 74A 76 77 AND STACK

4.1 Program Memory Organization PC<12:0>

The PIC16C7X family has a 13-bit program counter CALL, RETURN

RETFIE, RETLW 13
capable of addressing an 8K x 14 program memory
space. The amount of program memory available to
each device is listed below: Stack Level 1

Program
Device Address Range
Memory
Stack Level 8
PIC16C72 2K x 14 0000h-07FFh
PIC16C73 4K x 14 0000h-0FFFh
Reset Vector 0000h
PIC16C73A 4K x 14 0000h-0FFFh
PIC16C74 4K x 14 0000h-0FFFh
PIC16C74A 4K x 14 0000h-0FFFh
Interrupt Vector

User Memory
0004h
PIC16C76 8K x 14 0000h-1FFFh
0005h

Space
On-chip Program
PIC16C77 8K x 14 0000h-1FFFh Memory (Page 0)
For those devices with less than 8K program memory, 07FFh
accessing a location above the physically implemented 0800h
On-chip Program
address will cause a wraparound. Memory (Page 1)
The reset vector is at 0000h and the interrupt vector is
at 0004h. 0FFFh
1000h
FIGURE 4-1: PIC16C72 PROGRAM
MEMORY MAP AND STACK
1FFFh
PC<12:0>
CALL, RETURN
RETFIE, RETLW 13

Stack Level 1

Stack Level 8

Reset Vector 0000h

Interrupt Vector
User Memory

0004h
0005h
Space

On-chip Program
Memory

07FFh
0800h

1FFFh

 1997 Microchip Technology Inc. DS30390E-page 19

PIC16C7X
FIGURE 4-3: PIC16C76/77 PROGRAM 4.2 Data Memory Organization
MEMORY MAP AND STACK Applicable Devices
PC<12:0> 72 73 73A 74 74A 76 77
The data memory is partitioned into multiple banks
CALL, RETURN 13 which contain the General Purpose Registers and the
RETFIE, RETLW
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
Stack Level 1
RP1:RP0 (STATUS<6:5>)
Stack Level 2 = 00 → Bank0
= 01 → Bank1
= 10 → Bank2
Stack Level 8 = 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Reset Vector 0000h Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
Interrupt Vector 0004h registers from one bank may be mirrored in another
0005h bank for code reduction and quicker access.
On-Chip Page 0
User Memory

07FFh 4.2.1 GENERAL PURPOSE REGISTER FILE

Space

0800h
On-Chip Page 1 The register file can be accessed either directly, or indi-
0FFFh rectly through the File Select Register FSR
(Section 4.5).
1000h
On-Chip Page 2
17FFh
1800h
On-Chip Page 3
1FFFh

DS30390E-page 20  1997 Microchip Technology Inc.

PIC16C7X
FIGURE 4-4: PIC16C72 REGISTER FILE FIGURE 4-5: PIC16C73/73A/74/74A
MAP REGISTER FILE MAP

File File File File

Address Address Address Address
00h INDF(1) INDF(1) 80h
00h INDF(1) INDF(1) 80h
81h 01h TMR0 OPTION 81h
01h TMR0 OPTION
82h 02h PCL PCL 82h
02h PCL PCL
83h 03h STATUS STATUS 83h
03h STATUS STATUS
84h 04h FSR FSR 84h
04h FSR FSR
85h 05h PORTA TRISA 85h
05h PORTA TRISA
86h 06h PORTB TRISB 86h
06h PORTB TRISB
87h 07h PORTC TRISC 87h
07h PORTC TRISC
08h 88h 08h PORTD(2) TRISD(2) 88h
09h 89h 09h PORTE(2) TRISE(2) 89h
8Ah 0Ah PCLATH PCLATH 8Ah
0Ah PCLATH PCLATH
8Bh 0Bh INTCON INTCON 8Bh
0Bh INTCON INTCON
8Ch 0Ch PIR1 PIE1 8Ch
0Ch PIR1 PIE1
8Dh 0Dh PIR2 PIE2 8Dh
0Dh
8Eh 0Eh TMR1L PCON 8Eh
0Eh TMR1L PCON
8Fh 0Fh TMR1H 8Fh
0Fh TMR1H
90h 10h T1CON 90h
10h T1CON
91h 11h TMR2 91h
11h TMR2
92h 12h T2CON PR2 92h
12h T2CON PR2
93h 13h SSPBUF SSPADD 93h
13h SSPBUF SSPADD
94h 14h SSPCON SSPSTAT 94h
14h SSPCON SSPSTAT
95h 15h CCPR1L 95h
15h CCPR1L
96h 16h CCPR1H 96h
16h CCPR1H
97h 17h CCP1CON 97h
17h CCP1CON
98h 18h RCSTA TXSTA 98h
18h
99h 19h TXREG SPBRG 99h
19h
9Ah 1Ah RCREG 9Ah
1Ah
9Bh 1Bh CCPR2L 9Bh
1Bh
9Ch 1Ch CCPR2H 9Ch
1Ch
9Dh 1Dh CCP2CON 9Dh
1Dh
9Eh 1Eh ADRES 9Eh
1Eh ADRES
9Fh 1Fh ADCON0 ADCON1 9Fh
1Fh ADCON0 ADCON1
20h 20h A0h
A0h
General General
Purpose Purpose General General
Register Register Purpose Purpose
BFh
Register Register
C0h

7Fh FFh
Bank 0 Bank 1
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as
'0'.
Unimplemented data memory locations, read as
Note 1: Not a physical register.
'0'. 2: These registers are not physically imple-
Note 1: Not a physical register. mented on the PIC16C73/73A, read as '0'.

 1997 Microchip Technology Inc. DS30390E-page 21

PIC16C7X
FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP
File
Address

Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h
TMR0 01h OPTION 81h TMR0 101h OPTION 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h 107h 187h
PORTD (1) 08h TRISD (1) 88h 108h 188h
PORTE (1) 09h TRISE (1) 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
PIR2 0Dh PIE2 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh 8Fh 10Fh 18Fh
T1CON 10h 90h 110h 190h
TMR2 11h 91h 111h 191h
T2CON 12h PR2 92h 112h 192h
SSPBUF 13h SSPADD 93h 113h 193h
SSPCON 14h SSPSTAT 94h 114h 194h
CCPR1L 15h 95h 115h 195h
CCPR1H 16h 96h 116h 196h
CCP1CON 17h 97h General 117h General 197h
Purpose Purpose
RCSTA 18h TXSTA 98h Register 118h Register 198h
TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h
RCREG 1Ah 9Ah 11Ah 19Ah
CCPR2L 1Bh 9Bh 11Bh 19Bh
CCPR2H 1Ch 9Ch 11Ch 19Ch
CCP2CON 1Dh 9Dh 11Dh 19Dh
ADRES 1Eh 9Eh 11Eh 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h

General General General General

Purpose Purpose Purpose Purpose
Register Register Register Register
80 Bytes 80 Bytes 80 Bytes
96 Bytes EFh 16Fh 1EFh
F0h 170h accesses 1F0h
accesses accesses
70h-7Fh 70h-7Fh 70h - 7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as '0'.

* Not a physical register.
Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'.

Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require
relocation of data memory usage in the user application code if upgrading to the PIC16C76/77.

DS30390E-page 22  1997 Microchip Technology Inc.

PIC16C7X
4.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two
sets (core and peripheral). Those registers associated
The Special Function Registers are registers used by with the “core” functions are described in this section,
the CPU and Peripheral Modules for controlling the and those related to the operation of the peripheral fea-
desired operation of the device. These registers are tures are described in the section of that peripheral fea-
implemented as static RAM. ture.

TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY

Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets
BOR (3)

Bank 0

00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(1) (4) (4)
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h — Unimplemented — —

09h — Unimplemented — —

0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

0Dh — Unimplemented — —

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h TMR2 Timer2 module’s register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h — Unimplemented — —

19h — Unimplemented — —

1Ah — Unimplemented — —

1Bh — Unimplemented — —

1Ch — Unimplemented — —

1Dh — Unimplemented — —

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.

 1997 Microchip Technology Inc. DS30390E-page 23

PIC16C7X
TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets
BOR (3)

Bank 1

80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

83h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h — Unimplemented — —

89h — Unimplemented — —

8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000

8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

8Dh — Unimplemented — —

8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu

8Fh — Unimplemented — —

90h — Unimplemented — —

91h — Unimplemented — —

92h PR2 Timer2 Period Register 1111 1111 1111 1111

93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000

94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000

95h — Unimplemented — —

96h — Unimplemented — —

97h — Unimplemented — —

98h — Unimplemented — —

99h — Unimplemented — —

9Ah — Unimplemented — —
9Bh — Unimplemented — —

9Ch — Unimplemented — —

9Dh — Unimplemented — —

9Eh — Unimplemented — —

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

DS30390E-page 24  1997 Microchip Technology Inc.

PIC16C7X
TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets
BOR (2)

Bank 0

00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4) (7) (7)
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
(5)
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h TMR2 Timer2 module’s register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x

19h TXREG USART Transmit Data Register 0000 0000 0000 0000

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu

1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu

1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.

 1997 Microchip Technology Inc. DS30390E-page 25

PIC16C7X
TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets
BOR (2)

Bank 1

80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4) (7) (7)
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111
(5)
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111

8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

8Eh PCON — — — — — — POR BOR(6) ---- --qq ---- --uu

8Fh — Unimplemented — —

90h — Unimplemented — —

91h — Unimplemented — —

92h PR2 Timer2 Period Register 1111 1111 1111 1111

93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000

94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000

95h — Unimplemented — —

96h — Unimplemented — —

97h — Unimplemented — —

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

9Ah — Unimplemented — —
9Bh — Unimplemented — —

9Ch — Unimplemented — —

9Dh — Unimplemented — —

9Eh — Unimplemented — —

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

DS30390E-page 26  1997 Microchip Technology Inc.

PIC16C7X

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY

Value on: Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets
BOR (2)

Bank 0

00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu