EEE-251 Digital Logic Design Laboratory

Week 5 Experiments

Name: Ahmet Yusuf Yatkın

Dep.: Electrical and Electronics Engineering
Student Number: 18290239
[email protected]

Abstract—In this experiment, we inspect some Flip flop When the third clock pulse arrives this logic “1” value
circuits (D Type Flip-Flop, Master-Slave Flip Flop), and moves to the output of FFC ( QC ) and so on until the arrival
checked the outputs are match with theoretical background. of the fifth clock pulse which sets all the outputs QA to QD
Also, we’ll inspect 4-8-bit register circuits and 64 bit memory back again to logic level “0” because the input to FFA has
circuit. Our aim was demonstrating the how these circuits work
and what output will they give. Our results matched with
remained constant at logic level “0”. The effect of each clock
theoretical information. pulse is to shift the data contents of each stage one place to
the right, and this is shown in the following table until the
Keywords— D Type Flip-Flop, Master-Slave Flip-Flop, 4-bit complete data value of 0-0-0-1 is stored in the register. This
shift register, 8-bit shift register, 64 bit memory circuit. data value can now be read directly from the outputs of QA
to QD. Then the data has been converted from a serial data
I. INTRODUCTION input signal to a parallel data output. The truth table and
Flip-Flop circuits design to control some logical following waveforms show the propagation of the logic “1”
operations from its electrical inputs. Also, they are important through the register from left to right as follows:
for building bigger logical circuits. These circuits basically
process their inputs and give the output from those inputs what
it designed for. our experiment aims to demonstrate behavior
some of the Flip-Flop, register and Memory circuits.
mentioned in keywords. We gave inputs to these gates and
tested the output.
II. THEORETICAL BACKROUND
First, I began with 4-bit shift register, 4-bit shift register

Note that after the fourth clock pulse has ended the 4-bits
of data (0-0-0-1) are stored in the register and will remain
there provided clocking of the register has stopped. In
practice the input data to the register may consist of various
combinations of logic “1” and “0”.

Second, I continue with D Type Flip Flop Circuit. gate

experiment. We remember that a simple SR flip-flop requires
two inputs, one to “SET” the output and one to “RESET” the
circuit is given in figure above. Let’s assume that all the flip- output. By connecting an inverter (NOT gate) to the SR flip-
flops (FFA to FFD) have just been RESET (CLEAR input) flop we can “SET” and “RESET” the flip-flop using just one
and that all the outputs QA to QD are at logic level “0” i.e., input as now the two input signals are complements of each
no parallel data output. If a logic “1” is connected to the other. This complement avoids the ambiguity inherent in the
DATA input pin of FFA then on the first clock pulse the SR latch when both inputs are LOW, since that state is no
output of FFA and therefore the resulting QA will be set longer possible. Thus, this single input is called the “DATA”
HIGH to logic “1” with all the other outputs still remaining input. If this data input is held HIGH, the flip flop would be
LOW at logic “0”. Assume now that the DATA input pin of “SET” and when it is LOW the flip flop would change and
FFA has returned LOW again to logic “0” giving us one data become “RESET”. However, this would be rather pointless
pulse or 0-1-0. The second clock pulse will change the output since the output of the flip flop would always change on every
of FFA to logic “0” and the output of FFB and QB HIGH to pulse applied to this data input. To avoid this an additional
logic “1” as its input D has the logic “1” level on it from QA. input called the “CLOCK” or “ENABLE” input is used to
The logic “1” has now moved or been “shifted” one place isolate the data input from the flip flop’s latching circuitry
along the register to the right as it is now at QA. after the desired data has been stored. The effect is that D
input condition is only copied to the output Q when the clock
input is active. This then forms the basis of another sequential REFERENCES
device called a D Flip Flop. The “D flip flop” will store and [1] Lecture Videos of related week published by Ankara University
output whatever logic level is applied to its data terminal so [2] Experiment Videos of related week published by Ankara University
long as the clock input is HIGH. Once the clock input goes [3] https://www.electronics-tutorials.ws/wp-
LOW the “set” and “reset” inputs of the flip-flop are both content/uploads/2018/05/sequential-seq7.gif
held at logic level “1” so it will not change state and store [4] https://www.electronics-tutorials.ws/wp-
whatever data was present on its output before the clock content/uploads/2018/05/sequential-seq34.gif
transition occurred. In other words, the output is “latched” at [5] https://www.electronics-tutorials.ws/wp-
content/uploads/2018/05/sequential-seq15.gif
either logic “0” or logic “1”. Detailed results will be given in
[6] A 64-Bit Memory System Design Group 13 article 2016
results part.

Third, I inspect Master-Slave Flip-Flop.

We can see from above that on the leading edge of the

clock pulse the master flip-flop will be loading data from the
data D input; therefore, the master is “ON”. With the trailing
edge of the clock pulse the slave flip-flop is loading data, i.e.
the slave is “ON”. Then there will always be one flip-flop
“ON” and the other “OFF” but never both the master and
slave “ON” at the same time. Therefore, the output Q acquires
the value of D, only when one complete pulse, i.e., 0-1-0 is
applied to the clock input. Detailed results will be given in
results part.

Finally, I inspect 64-bit memory circuit. An SRAM

memory system consists of four parts: the address registers,
where addresses received from the CPU are stored while the
memory retrieves the requested data, a row decoder that takes
the address stored in the address register and selects the
appropriate row of the memory array, the memory array
itself, consisting of SRAM cells arranged into an array
fashion, and two data registers where the data to be read or
written into the memory is stored. a. On a 64-bit SRAM
layout, there is 1 column and 16 rows. A column can store 4
bits. i.e. 4 individual elements are present in each column.
The effective layout is 16x[1x4]. A modular design approach
is done, wherein each column and its circuits(read/write) are
done individually. Address registers are used to store and
deliver the address values to the circuit, and similarly data
registers are used to deliver the data to be written to the
circuit. A second set of data register is used to store the values
read from the SRAM. A 4-16 decoder is used as the row
decoder to select the row of operation.
III. CONCLUSION
To conclude, all of our experiments, theoretical
information and the simulation proved each other. All results
are same in these three ways. With these experiments, we’ve
learned all behaviors about 4-bit shift registers (with its types).
D Type Flip-Flop circuit, Master-Slave Flip-Flop circuit, and
the 64-bit Memory Circuit with checking too many different
combinations of each circuit.