12 Data Conversion Circuits — D/A and A/D Converters Digital-fo-analogue (D/A) and analogve-to-digital (\/D) converters constitute an essential ink when igtal devices interface with analogue devices, and vice versa. They are important building blocks of any digital system, including both communication and noncommunication systems, besides having ‘other applicaions. A'D/A converter is important not only because itis needed at the output of most gta systems, where it converts a digital signal into an analogue voltage o current so that it can be fed toa chart recorder, for instance, for measurement purposes oF a Servo motor in a control application: it is also important because it forms an indispensable part of the majority of A/D converter types. An AD converter to, tas numerous applications. When it comes to transmiting analogue data, i forms ‘an essential interface with a digital communication system where the analogue signal tobe transmited is digitized at the sending end with an A/D converter. It is invariably used in all digital read-out test and measuring equipment, Whether itis a digital multimeter ora digital storage oscilloscope or even a pH meter, an A/D converter is an important and essential component of all of them. In this chapter, we wil discuss the operational fundamentals the major performance specifications, along with their significance, and different types and applications of digital-o-analogue and analogue-to-digtal converters, in addition to appliation-elevant information of some of the popular devices. A large ‘numberof solved examples is also included to illustrate the concepts. 12.1 Digital-to-Analogue Converters [A DIA converter takes digital data a its input and converts them into analogue voltage or current that is proportional t the weighted sum of digital inputs In the following paragraphs itis briefly explained Digit Electronics: Pines, Devices and Arcations Ail Mai (© 2007 Jom Wiley & Sons, La ISBN: 978.0-70052148a4 Digital Electronics how differen bits in the digital input data contribute a different quantum to the overall output analogue voltage or curent, and also thatthe LSB has the least and the MSB the highest weight 12.1.1 Simple Resistive Divider Network for D/A Conversion ‘Simple resistive networks can be used to convert a digital input into an equivalent analogue output. Figure 12.1 shows one such resistive network that can convert three-bit digital input into an analogue ‘output. This network, however, can be extended further to enable it to perform digitl-to-analogue conversion of digital data with larger number of bis. In the network of Fig. 121, if R, is much larger than R, it can be proved withthe help of simple network theorems thatthe output analogue voltage is given by [WR + [V3 /(R/20] + [Va/CR/A)} Mae TRI RAIHRDT oo _ WR avs /R1 +4458) = WAT 2/R1 +107] a Mem 44¥y any a ich canbe funber expressed as ype PERU Wa a 21 ‘The generalized expression of Equation (12.4) can be extended further t0 an n-bit D/A converter to get the following expression: MV DEM +¥,x (Ky an In expression (12.5), if = Vy =... = Vy = V. them a logie "atthe LSB position would cont V/(2"—1) to the analogue output, and & logic *I* in the next adjacent higher bit position would Figure 12. Simple resistive network for DIA conversionata Conversion Circuits ~ DIA and A/D Converters 475 contribute 2V/(2" ~1) tothe output. The contributions of successive higher bit positions inthe case of a logic I" would be 4V/(2" — 1), 8V/(2" = 1), 16V/(2"~ 1) and so on. That is, the contribution of any given bit postion owing to the presence of a logic ‘I’ is twice the contribution of the adjacent lower bit position and half that of the adjacent higher bit position, When all input bit positions have a logic “1”, the analogue output is given by VOQ42424 42 Vs 3 =v (12.6) In the case ofall inputs being inthe logic 0" state, Vy =O. Therefore, the analogue output varies from (to V volts asthe digital input varies from an all s ton all 1s input 12.1.2 Binary Ladder Network for D/A Conversion ‘The simple resistive divider network of Fig, 12.1 has two serious drawbocks. One, each resistor in the network is of a different value. Since these networks use precision resistors, the added expense becomes unattractive. Two, the resistor used for the most significant bit (MSB) is required to handle ‘a much larger current than the LSB resistor. For example, ina 10-bit network, the current through the (SB resistor willbe about 500 times the current through the LSB resistor ‘To overcome these drawbacks, a second type of resistive network called the binary ladder (or RI2R ladder) is used in practice, The binary ladder, too, i a resistive network that produces an analogue ‘output equal tothe weighted sum of digital inputs, Figure 12.2 shows the binary ladder network for our-bit DVA converter. Asis clear from the figure, the ladder is made up of only two different values fof resistor. This overcomes one of the drawbacks of the resistive divider network. It can be proved ‘with the help of simple mathematics that the analogue output voltage Vin the case of binary ladder network of Fig. 12.2 is given by xP Va DEV x24 Vy 2! a In general, for an n-bit D/A converter using a binary ladder network Me (127) Vix 24 Vi xB x2 oo HV, KOE! 7 V, Va = [2"— V2". For ¥, Ms Figure 12.2 Binary ler network for DIA conversion476 Digital Electronics Binary ee eee Figure 123. Block ssematc representation of « DIA converte ‘The analogue output voltage inthis ease varies from 0 (for an all Os input) to (2° — 1)2"]V (For an all 1s input). ‘Also in the case of a resistive divider network, the LSB contsibution to the analogue output is [1/2"=1)]V. This is also the minimum possible incremental change in the analogue output voltage. ‘The sume in the case of binary’ ladder network would be (1/2")V, ‘A binary ladder network is the most widely used network for digital-to-analogue conversion, for ‘obvious reasons. Although actual D/A conversion takes place inthis network, a practical D/A converter device has additional circuitry such asa register for temporary storage of input digital data and level amplifiers co ensure that the digital signals presented to the resistive network are all ofthe same level Figure 12.3 shows a block schematic representation of a complete n-bit D/A converter, D/A converters of different sizes (cight-it, 12-bit, 16-bit, ete.) are available in the form of integrated circuits 12.2 D/A Converter Specifications ‘The major performance specifications of a DIA convener include resolution, accuracy, conversion speed, dynamic range, nonlinearity (NL) and differential nonlinearity (DNL) and monotonocity. 12.2.1 Resolution ‘The resolution of a D/A converter is the number of states (2°) into which the full-scale range is divided or resolved. Here, n isthe number of bits inthe input digital word. The higher the number ‘of bits the better isthe resolution, An eight-bit DYA converter has 255 resolvable levels. I is said toata Conversion Circuits ~ DIA and A/D Converters an hhave a percentage resolution of (1/255) x 100 =0.39 % or simply an eight-bit resolution. A 12-bit DIA converter would have a percentage resolution of (1/4095) x 100 0.0244 %. In genera, for an n-bit DIA converter, the percentage resolution is given by (/2" — 1) x 100. The resolution in millivolts for the two eases for a full-scale output of 5 V is approximately 20 mV (For an eightbit converter) and 1.2 mV (fora 12-bit converter). 12.2.2 Accuracy ‘The accuracy of a DIA converter isthe difference between the actual analogue output and the ideal expected output when a given digital input is applied. Sources of error include the gain error (or {ull-seale error), te offset error (or zero-scale err), nonlinearity errors and adrift of all these factors. ‘The gain error (Fig. 12.4(a)] i the difference between the actual and ideal output voltage, expressed 4s a percentage of full-scale output. Its also expressed in terms of LSB. As an example, an accuracy ‘of 0.1% implies thatthe analogue output voltage may be off by as much as +5 mV for a full-scl ‘output of 5 V uroughout the analogue output vollage range. The offset eror is the error at analogue zero [Fig 12.4(6) 12.2.3 Conversion Speed or Settling Time ‘The conversion speed of a D/A converter is expressed in terms of its setling time. The setting time Js the time period that has elapsed for the analogue output to reach its final value within a specified error band after a digital input code change has heen effected. General-purpose DA converters have settling time of several microseconds, while some of the high-speed DVA converters have a setting Analog output Digital input @ igure 124, (2) Gain eor and () ost ero478 Digital Electronics Analog output Digital input © Figure 12.4 (continued) time of a few nanoseconds. The setting time specification for D/A converter type numiber AD 9768 from Analog Devices USA, for instance, is Sms. 12.24 Dynamic Range ‘This is the ratio of the largest ouput to the smallest output, excluding zero, expressed in dB. For linear D/A converters itis 20 x log2*, which is approximately equal to 6n. For companding-type D/A ‘converters, discussed in Section 12.3, itis typically 66 oF 72 4B. 12.2.5 Nonlinearity and Differential Nonlinearity [Nonlinearity (NL) is the maximum deviation of analogue output voltage from a straight line drawn between the end points, expressed as a percentage of the fullseale range or in terms of LSBs. Difjerental nonlinearity (DNL is the worst-case deviation of any adjacent analogue outputs from the ‘deal one-LSB step size. 12.2.6 Monotonocity In an ideal D/A converter, the analogue output should increase by an identical step size for every ‘one-LSB increment inthe digital input word, When the input of such a converter is fe from the output of a counter, the converter output will be a perfect staircase waveform, as shown in Fig. 12.5. In such ceases, the converter is said to be exhibiting perfect monotonocity. A D/A converter is considered as ‘monotonic if its analogue output either increases or remains the same but does not deerease asthe digital inpot code advances in one-LSB steps. If the DNL error of the converter is less than or equal {o twice its worst-case nonlinearity errr, it guarantees monotonocityata Conversion Circuits ~ DIA and A/D Converters 479 om ay Converter ] Digital VP Counter Figure 128 Monotonecity in @ DIA conver, 12.3 Types of D/A Converter ‘The D/A converters discussed inthis section include the following: 1. Multiplying-type D/A converters. 2. Bipolar-output DIA converters. 3. Companding DIA converters. 12.3.1 Multiplying D/A Converters In a muliplying-ype DIA converter, the converter multiplies an analogue reference by the digital input. Figure 12.6 shows the circuit representation. Some D/A converters can multiply only positive digital words by & positive reference. This is known as single quadrant (QUAD-1) operation. Two- {quadrant operation (QUAD-I and QUAD-lI]) can be achieved in a D/A converter by configuring ‘the output for bipolar operation. This is accomplished by offsetting the output by a negative MSB (qual to the analogue output of 1/2 of the full-scale range) so thatthe MSB becomes the sign bi Digital Input DA Ret Convertor "avalon (Output Figure 12.6 Muitiplyingsype DIA converter480 Digital Electronics ‘Some D/A converters even provide four quadrant operation by allowing the use of both postive and negative reference. Multiplying D/A converters ae particularly useful when we are looking fr digitally ‘programmable attenuation of an analogue input signal. 12.3.2 Bipolar-Output D/A Converters In bipolar-ourput DIA converters the analogue output signal range includes both positive and negative Values. The transfer characteristics of an ideal two-quadrant bipolar-output DYA converter are shown, in Fig. 127. 12.3.3 Companding D/A Converters Companding-type DIA. converters are so constructed thatthe more si hhave a larger than binary relationship to the less significant the more significant bits, which in turn increases the analogue signal range. The effect of this is to ‘compress more data into more significant bits, 12.4 Modes of Operation DIA converters are usually operated in either of the following two modes of operation: 1. Current steering mode. 2. Voluge switching mode, 12.4.1 Current Steering Mode of Operation In the current steering mode of operation of a D/A converter, the analogue output is a current equal 10 ‘the product ofa reference voltage anda fractional binary value D of the input digital word. D is equal to the sum of fractional binary values of different bits in the digital word Also, fractional binary values of different bits in an n-bit digital word stating from the LSB are 22%, 242", 22/2",..., 2"-42" FS f Analog or a Figure 12.7. Ripolarouput BVA converter transfer charset.ata Conversion Circuits ~ DIA and A/D Converters 481 ty R 8 aR 6 N18 (analog Ground) ee Figure 1238 Curent steering mode of operation of DIA convener. 1 ome ‘The output curent is often converted into a corresponding voltage using an external opamp wired as a current-to-voltage converter. Figure 12.8 shows the circuit arrangement. The majority of DIA converters in IC form have an in-built opamp that can be used for curent-o-voltage conversion. For the circuit arrangement of Fig. 1238, if the feedback resistor Ry equals the ladder resistance R, the analogue output voltage atthe opamp output is -(D.V) ‘The arrangement ofthe four-bit D/A converter of Fig. 12.8 can be conveniently used to explain the ‘operation of a D/A converter inthe current steering mode. The R/2R ladder network divides the input current J due to a reference voltage Vqr applied atthe reference vollage input of the DIA converter into binary weighted curents, as shown. These currents are then stered to either the output designated Out-1 or Out-2 by the current stering switches. The postions ofthese current steering switches are controlled by the digital input wond. A logic ‘I” steers the corresponding current to Out-1, whereas logic 0” steers it to Out-2. For instance, a logic ‘I’ in the MSB position will ster the eurent 1/2 10 (Out-1. A logic ‘0 sters itt Our-2, whichis the ground terminal. In the fou-bit converter of Fig. 1.8, the analogue output current (or voltage) will be maximum for a digital input of 1111. The anslogue ‘output current in this ease will bo 1/2 +1/4 +118 + 1116 = (15/16)7. The analogue output voltage will be (-15/16}IR, = (—IS/IO)R. Also, = Vgg/R a the equivalent resistance of the ladder network across Vqy is also R. The analogue output voltage is then [(—15/16)(Vg)/R] xR = (—15/16)Vqp Here, 15/16 is nothing but the fractional binary value of digital input 1111. In general, the maximum analogue output voltage is given by —(1 2°") x Vj, where isthe numer of bts in the input digital ‘word. 12.4.2 Voltage Switching Mode of Operation In the voltage switching mode of operation of a RR ladder type DIA converter the reference voltage is applied to the Out-1 terminal and the output is taken from the reference voltage terminal. Out2 is joined to analogue ground, Figure 12.9 shows « four-bit D/A converter of the R/2R ladder type in482 Digital Electronics 4 ‘ i ~~ Figure 129) Voltage sitching mode of operation of DYA converter voltage switching mode of operation. The output voltage is the product of the fractional binary value of the digital input word and the reference voltage applied atthe Out-I terminal, ie. D.Vj. AS the positive reference voltage produces & postive analogue output voltage, the voltage switching mode of ‘operation is possible with a single supply. As the circuit produces analogue output voluage, it obviates the need for an opamp and the feedback resistor. However, the reference voltage applied to the Out-1 terminal inthis ease will see different input impedances for different digital inputs. For this reason, the source ofthe input ix buffered, 12.5 BCD-Input D/A Converter ‘A BCD-input D/A converter accepts the BCD equivalent of decimal digits atits input. two-digit BCD DIA converter for instance isan eight-bit D/A converter. Figure 12.10 shows the circuit representation of an eight-hit BCD-type D/A convener. Such a converter has 99 steps and accepts decimal digits (0 to 99 at its input. A 12-bit converter will have 999 steps. The weight ofthe different bits in the least significant digit (LSD) will be 1 (for Ap), 2 (for By). 4 (for Cy) and 8 (For Ds). The weights of the corresponding bits in the next higher digit will be 10 times the weights of corresponding bts in the lower adjacent digit. For the DYA converter shown in Fig. 12.10 the weight ofthe different bits in the most significant digit (MSD) will be 10 (or A,), 20 (or B,), 40 (for C,) and 80 (for D,). In general, an n-bit DYA converter of the BCD input type will have (10"”— 1) steps. The percentage resolution of such a converter is given by [1/(10"— 1)] x 100,ata Conversion Circuits ~ DIA and A/D Converters 483 Most {2;— Signieant | cy Digit} 5, | uso) |; ec oa | _. Least [2—} convenor | Anal signteart [cj] °°” ear Det | 5, aso [2% Figure 12.10 BCD-inpur D/A convener. Example 12.1 An eight-bit D/A converter has a step size of 20 mV. Determine the full-scale ouput and percentage resolution. Solution © (122) x V = 20 x 10, where V is the voltage corresponding t0 a loge ‘I ‘This gives V = 20 x 107% 28 = 5.10V. ‘© The full-scale ousput = [(2*~ 1) 2") x V = (Q' 1y28] x 5.12 = (255/286) x 5.12 = S.1V. 1 The percentage resolution = [1/2'—1)] x 100 = 100/255 = 0.392%. ‘© Tho percentage resolution ean also be determined from: (Step sizefull-scale output) x 100 = 20 x 10-%5.1) x 100 = 0392. Example 12.2 Refer to Fig. 12.11. This BCD DIA converter has a step size of 6.25 mV. Determine the full-scale ouput Solution 1A step sizeof 6.25 mV implies that Ay has a weight of 6.25 mV. ‘© The weights of B,C, and Dy would respectively be 12.5, 25 and 50 mV. © Now, the weight of A, will be 10 times the weight of Ay, Le. the weight of A, will be 62.5 mV. # The weights of B;, C; and D,will accordingly be 125, 250 and 500 mV respectively. ‘© On similar lines, the weights of Ay, By, C, and D, will respectively be 625 mY, 1.25 V, 2.5 V and 3v. For full-scale output, the input will be decimal 999, Each ofthe three four-bit groups willbe 1001 ‘Therefore, the full-scale analogue output = 625 + 50-+ 62.5 +500 + 625-+ 5000 mV =6.24375 V. ‘The full-scale analogue output can also be determined from the product of the step size and number of steps. That is, the full-scale output = 6.25 x 999 = 6.24375 .484 Digital Electronics A Converter 8 /Ao——+] LSB igure 12.11 BCD-input DYA converter (example 122) Example 12.3 A certain eight-bit D/A converter has a full-scale output of § mA and a full-scale error of 0.25 % of {fall scale, Determine the range of expected analogue ouput for « digital input of 10000010. Selon asc up tep size = Number of steps “3 19.6 uA ‘ Fora digital input of 10000010 (= 130.) the analogue output is given by 130 x 19. = 2.548 ma. 0.255 «107 mor = 2°25 25% 10" =£125 nA ‘© The expected analogue ourput will therefore be in the range 2.5385-2.5605 mA. Example 12.4 [An experimenter connects a four-bit ripple counter to a four-bit DIA converter to perform a staircase test using @ 1 AH clock as shown in Fig, 12.12. The output staircase waveform is shown in Fi. 12.13. The cause of the incorrect staircase signal is later determined to be a wrong connection between the Counter output and the DIA converter input. What is it? se waveform would be generated at the output of the D/A converter if the counter outputs Q, (LSB), Qj, 2: and Q, (MSB) were connected t© the corresponding inputsata Conversion Circuits ~ DIA and A/D Converters 485 (MSB) Q3}—+] ok, 4 OF] va. Counter g, Converter Jnalog O1P (USB) Qo} —+ Figure 12.12 Example 124. 15 14 13 12 1" 10 Analog Output (V) t 128.4 5 6 7 8 8 1011 1213 14 15 16 (ms) Figure 12.13 Suirease waveform (example 124, fof the D/A converter in the same order. If we carefully examine the given staircase waveform ‘and recall the sequence in which the counter will advance, it can be visualized that the given staircase waveform would result ifthe interconnections of the LSB and the next adjacent higher it of the counter output and the corresponding inputs of the DYA converter were interchanged, While in one complete eyele the counter counts as 0000, 0001, OD10, 0011, 0100, 0101, 0110, 111, 1000, 1001, 1010, 1011, 1100, 1101, 1110 and 1111, the D/A converter, owing 10 interchanged connections, gets inputs as 0000, 0010, 0001, 0011, 0100, 0110, O101, 0111, 1000, 1010, 1001, 1011, 1100, 1110, 1101 and 1111. The corresponding analogue outputs are 0, 2. 1, 3, 4, 6,5, 7, 8 10, 9, 11, 12, 14, 13 and 15 V, as shown in the staircase waveform of Fig. 12:13.486 Digital Electronics 12.6 Integrated Circuit D/A Converters ‘This section presents application relevant information on some of the commonly used D/A eonverter IC type numbers, as itis not possible to give a detailed description ofeach one of them. The type numbers included fortis purpose are DAC-0810800, DAC-80, DAC-0808, AD 7524 and DAC-1M08A/1S08A, 12.6.1 DAC-08 DAC-08 is an eight-bit monolithic D/A converter. is major performance specifications include seting time of 85 ns, a monotonic multiplying performance over a wide 20-to-1 reference current range, a direct interface to all popular logic Families, high voltage compliance complementary current ‘outputs, nonlinearities of 0.1 % over the entre operating temperature range and a wide power supply range of 245 V to +18 V. Figures 12.14(a) and (b) respectively show the basi circuit configurations for positive low impedance output operation and negative low impedance output operation. DAC-08, paces E5200 lea A @ © Figure 12.14 (2) Busi crit configuration of DAC0S for positive opt operation and (b) the basic eicit configuration of DAC-08 for negative output operation,ata Conversion Circuits ~ DIA and A/D Converters 487 applications include waveform generators, servomovor and pen drivers, audio encoders and digitally controlled attenuators, analogue meter drivers, programmable power supplies, high-speed modems, CRT display drivers, ete. 12.6.2 DAC-0808 DAC-0808 is an eight-bit D/A converter featuring a fullscale output current setting time of 150ns ‘while dissipating only 33 mW with +5 V supplies. Relative accuracies of beter than 0.19 % ensure cight-it monotonocity and linearity, while zero-level output curent of less than 4 mA provides eight- bit zero accuracy for Jny > 2-mA. Ithas a wide power supply voltage range of 4-45 V to +18 V. It can interface directly with popular TTL, DTL or CMOS logic families and is a direct replacement for the DIA converter MC 1S08/MC 1408, Figure 12.15 shows the application circuit of DAC-O808 wired 4s a voltage-output D/A converter, 12.6.3 DAC-80 DAC-80 is 12-bit D/A converter. Both current and voltage-output versions are available. Its salient features include low power dissipation (345 mW), full © 10 V swing with +12 V supplies, TTL and CMOS-compatible digital inpus, +1/2 LSB maximum nonlinearity over 0-70 °C, guaranteed ‘monotonocity over 0-70 °C and 4 ms setting time to 0.01 % of full-scale and monolithic design Figures 12.16 and 12.17 show the pin connection diagrams of current-outpot and voltage-output models of DAC0. Neg =5V 1344] 2 Vner (10.000) (88) Ago 12 18v Vez Figure 12.18 DAC-O808 wired asa voltge-ouput DIA conver.Digital Electronics sey ‘Bet [| 1k {2a} 6.9V Relerence Out te EL Raerenee |_f5) cain Aust vo [al Groot | ea ace ats (| fan] common wee Scaling Nework as CEH] raat} | fal ssana esse [ag Fr seat networ 20 (EF) Network a2 Saar v7 ZL “an | a Fo song or eel eee || eee ero Bite [a [75] Reterence input it 10 [79] [35] four itt [| [74] Veo ai 12 [7] 33] no (88) Figure 12.16 Pin connection diagram of DAC-80(curen-ouput version), ‘ort cof PE [a=] ev Reterence Out et2 Zt aterence | 73] Gain Adjust sits (3 Creu] [53) +Vec a4 [a rT [2] Common ars [5] 1288, F+-4———[p5] Suing Junction Br6 [BF etek Yet 20" Range et7 [ZL gant, (ha) 101 Range Bite [a] | Swiches [77] Bipolar Oftset ets [3 | [7] Rterence input sit 10 [Fa] Sf vou Bt Gi} [7a] Veo sit 12 [72] [ia] no ase) Figure 12.17 Pin conection diagram of DAC-80 (voltage-ouput version).ata Conversion Circuits ~ DIA and A/D Converters 489 12.6.4 AD 7524 AD 7524 isan eight-bit monolithic CMOS DAC designed for direct interface to most microprocessors such as 6800, 8085, 280, etc. It has an accuracy of 1/8 LSB, with a typical power dissipation of less than 10 mW. Monotonocity is guaranteed over full operation temperature range. It has setting time ‘of 250 ns (typical) for the output current to settle within 1/2 LSB for a supply voltage of +15 V. Its excellent muliplying characteristics (two or four quadrant) make AD 7524 un ideal choice for many mieroprocessor-contolled zain setting and signal control applications. It has a wide power supply range of +5 V to +15 V. Figure 12.18 shows the functional diagram which resembles the Functional diagram of any curent-output multiplying DYA converter 12.6.5, DAC-1408/DAC-1508 DAC- 1508/1408 isa general-purpose, high-speed multiplying-type eight-bit D/A converter. DAC-1508 is idemical 9 DAC-1408 except forthe operational temperature range, which is ~S5°C to +125 °C in the ease of DAC-1508, as against 0-70 °C for DAC-1408, Its pin and functionally compatible with DAC-0808, 8, 8 BB Cc) «s8) Figure 12.18 Functional diagram of AD 7524490 Digital Electronics 12.7 DIA Converter Applications In addition to being an integral purt of some of the architectures of popular varieties of A/D ‘converters, D/A converters ate extensively used in a variety of other application circuits, Some common applications inelude multipliers digitally controlled dividers, programmable integrators, low-frequency function generators and digitally controlled filters. 12.7.1 DIA Converter as a Multiplier ‘The basic DVA converter operated in the current steering mode with the output opamp wired as a ccurrentto-voltage converter works as a multiplier where the output voltage is the product of the analogue input applied at the Vj terminal and the digital word input. CMOS D/A converters ae ‘much better suited to multiplying applications as the multiplying capabilites of other types of DYA converter are restricted to a limited range of input voltage. One such application circuit where the ‘multiplying capability of the D/A. converter is used isthe digitally eontolled audio signal atenuator. Figure 12.19 shows the circuit diagram. The audio signal is applied to the Vqy input and the attenuation code is applied to the digital input. The analogue output is the attenuated version of the input ‘As tai attenuators, conventional D/A converters provide a limited range of attenuation which i 256:1 oF 48 dB for an cigh-bit converter and 4096:1 oF 72 dB fora 12-bit converter. Logarithmic D/A converters, which give a logarithmic relationship between the digital fraction and the output signal matching the response ofthe human ea ae particularly suitable for this application, These are coded to give attenuation in equal decimal steps. 12.7.2 D/A converter as a Divider If the feedback resistance is used a the input resistor and the D/A converter is connected asa feedback clement, the circuit acts asa divider or a programmable gain element. igure 12.20 shows the eieuit configuration. The output is given by V, = —(Vq/D). For smaller values of digital fraction D the ‘output increases, and the designer should ensure that the amplifier does not saturate wnder these conditions. Vw [oigtat input Figure 12.19 Digitally controled audio signa attenuatorata Conversion Circuits ~ DIA and A/D Converters 41 Digital Input Ve i Fre ours Dia Converter ours, Figure 12.20 Digitally conlled divider 12.7.3 Programmable Integrator ‘The programmable integrator forms the basis of a number of medium-frequency function generators. Figure 12.21 shows an inverting type of programmable integrator The output is expressed by [VC Roc RYLD f Vat (29) where Roa isthe input resistance ofthe DYA converter a the Vag ternal. Resistance R has heen used to get an appropriate value ofthe integrator ime constant for te fll-seale value of D."The integrator time constant given by [C(Roxe+ Ry] is largest when the input digital code is near ze and ‘our S “Dhl gals Converter our I le Figure 12.21 Inveing.type programmable integrator492 Digital Electronics smallest when D has the full-scale value. Figure 12.22 shows the noninverting type of programmable integrator. The output in this case is given by v DyeR) f Vos (210) 12.7.4 Low-Frequency Function Generator Figure 12.23 shows one possible circuit configuration of a DYA converter based low-frequency function ‘generator. There is no limit to the lowest frequency’ possible using this configuration. The upper limit Pra ‘ours | Vee wy ure Figure 12.22 Noninvesing programmable iterator Fra ours > DA |’ converter our LS 5 | Sign ROM oat} = Counter Figure 1223 Low-frequency funtion generatorata Conversion Circuits ~ DIA and A/D Converters 493 is determined by the setting time of the D/A convener, the required resolution and the permissible quantization noise ‘Since most of the functions are symmetric, iti usual to synthesize only half ofthe waveform and then invert it for the second half, This is tae for pulse, triangular, ramp and trapezoidal waveforms, For sinusoidal waveforms it is necessary only to synthesize one-quarter of the waveform. In the arrangement of Fig. 12.23, the frequeney is determined by the elock frequency and the waveform by the contents of the ROM 12.7.5 Digitally Controlled Filters rs having low noise and distortion with controllable gain, centre frequeney and Q-factor can be constructed using multiplying-type D/A converters. Three basi types of first-order low-pass filter are showin in Figs 12.24, 12.25 and 12.26. The low-pass eicuit of Fig. 12.24 has a Ryyc-dependent cut-off frequency given by RyRy +R) x (D/C Rose cay Figure 12.25 Low pass iter with euvoff roqueey independent of Rye494 Digital Electronics Figure 12.26 Low-pass fier with «programmable tine constant Also, the transfer function for this low-pass filter is given by Vou! Va (Raf Ry) {IL +50(R, +R). Roge-C/Ry DI} 22) ‘The cutoff frequency can be made independent of Ryqc by using the DVA converter asa programmable {gin element, as shown in Fig. 12.25. In this ease, the cutoff frequency w is given by = RD/R RC 213) and the transfer function is given by Vogl Von = (—Re/ Ry){1/ (1 + jo( Rs Re-C/R3-D)]} (2.14) IF itis required to have a proportional adjustment of the filter time constant rather than its cut-off frequency, the circuit of Fig. 12.25 is rearranged and the D/A converter is connected in the divider configuration as shown in Fig. 12.26, The time constant is given by Time constant = Ry-RyCD/Rs 215)ata Conversion Circuits ~ DIA and A/D Converters 495 and the transfer function is given by Vu/ Va = (Re/Ry)11/[1 + ie0(Re-Ry C.D/R))) (1216) | may be mentioned here that other types of digitally controled filter ate also possible using DA converters. One such possiblity, for instance, is by using state variable techniques, which can be used to design D/A converter based programmable filters to get low-pass, high-pass and band-pass functions Irom the same circuit 12.8 A/D Converters After digita-to-analogue converters, the discussion in the following paragraphs is on another vital data conversion integrated circuit component known as the analogue-to-digital (A/D) converter. An A/D converter isa very important building block and has numerous applications It forms an essential interface when it comes to analysing analogue data with a digital computer. Its an indispensable part of any digital communication system where the analogue signal to be tansmitted is digitized at the sending end with the help of an A/D converter, It is invariably used in all digital read-out test and ‘measuring equipment, Be ita digital voltmeter or a laser power meter, ot for that matter even a pH ‘meter, an A/D converter is the heart ofall of them. ‘An AD converter takes ati input an analogue voltage and after a certain amount of time produces «digital ouput code representing the analogue input, The A/D conversion process is generally more ‘complex than the D/A conversion process. There are various techniques developed for the purpose ‘of AID conversion, and these techniques hive different advantages and disadvantages with respect to ‘one another, which have been utilized in the fabrication of diferent categories of A/D converter ICs, A DIA converter circuit, as we will se inthe following paragraphs, forms a part of some of the types ‘of AID converte. ‘We begin with a brief interpretation ofthe terminology and the major specifications that are relevant to the understanding of A/D converters, The idea is to enable the designers to make a judicious choice ‘of AID converter suitable for their application. A brief comparative study of different types of A/D converter and the suitability of each one of these types for a given application requirement is also discussed. This is followed by application-relevant information on some of the more popular A/D convener IC type numbers. 12.9 A/D Converter Specifications ‘The major performance specifications ofan A/D converter include resolution, accuracy, gain and offset crrors, gain and offset drifts, the sampling frequency and aliasing phenomenon, quantization error, nonlinearity, differential nonlinearity, conversion time, aperture and acquisition times and code with Each one ofthese is briefly described in the following paragraphs. 12.9.1 Resolution The resolution of an A/D converter isthe quantum of the input analogue voltage change required to ‘increment its digital output from one code to the next higher code. An n-bit A/D converter can resolve fone part in 2"— 1. It may be expressed asa percentage of full scale or in bis. The resolution of an cight-bit A/D converter, for example, can be expressed as one part in 255 or as 0.4% of full scale or496 Digital Electronics simply as cight-itresolotion. If such a converter has a full-scale analogue input range of 10 Vit can resolve a 40 mV change in input. 12.9.2 Accuracy “The accuracy specification describes the maximum sum of all errors, both from analogue sources (mainly the comparator and the ladder resistors) and from the digital sourees (quantization ertor) of the A/D converter, These errors mainly include the gain err, the offset error and the quantization errr. The accuracy describes the actual analogue input and full-scale weighted equivalent ofthe output code corresponding tothe actual analogue input. The accuracy specification is rarely provided on the datasheets, and quite often several sources of errors are listed separately. 12.9.3 Gain and Offset Errors The gain error isthe difference between the actual full-scale transition voltage and the ideal full-scale transition voltage. Its expressed either as a percentage of the full-scale range (% of FSR) or in LSBs. ‘The offoet error is the error at analogue zero for an A/D converter operating in bipolar mode, It is ‘measured in % of FSR or in LSBs. 12.9.4 Gain and Offset Drifis ‘The gain drift is the change in the full-scale transition vollage measured over the entire operating temperature range. It is expressed in full scale per degree Celsius or ppm of full scale per degree Celsius or LSBs. The offer drift is the change with temperature in the analogue zero for an A/D ‘converter operating in bipolar mode. It is generally expressed in ppm of full scale per degree Celsius or LSBs. 12.9.5 Sampling Frequency and Aliasing Phenomenon If the rate at which the analogue signal to be digitized is sampled is at least twice the highest Frequency in the analogue signal, which is what is embodied inthe Shannon-Nyquist sampling theorem, then the analogue signal can be faithfully reproduced from its quantized values by using a suitable interpolation algorithm. The accuracy of the reproduced signal is, however, limited by the quantization ‘error (discussed in Section 12.9.6). Ifthe sampling rae is inadequate, i if tis less than the Nyquist rate, then the reproduced signal isnot a faithful reproduction ofthe original signal and these spurious signals, called aliases, are produced. The frequency of an aliased signal isthe difference between the signal frequency and the sampling frequency. For example, if sampled at 1,5 KHz rate, a 2 KHz sine ‘wave would be reconstructed as a 500 Hz sine wave. This problem is called aliasing and, in onder to avoid it, the analogue input signal i low-pas filered to remove all frequency components above half ‘the sampling rate. This filter, called an anti-aliasing filter, i used in all practical A/D converters. 12.9.6 Quantization Error ‘The quantization error is inherent to the digitizing process. For a given analogue input voltage range it can be reduced by increasing the number of digitized levels. An A/D converter having an n-bitata Conversion Circuits ~ DIA and A/D Converters 47 ‘output can only identify 2* output codes while there are an infinite number of analogue input values adjacent to the LSB of the A/D converter that are assigned the same output code. For instance, if we fare digitizing an analogue signal with peak value of 7 V using three bits, then all analogue voltages ‘equal (0 or greater than 5.5 V and less than or equal to 6.5 V will be represented by the same output code, i.e. 110 (if the output coding is in straight binary form). The error is 40.5 V or +1/2 LSB, as «4 one-LSB change in the output corresponds to an analogue change of 1 V in this case. The 1/2 LSB limit o resolution is known as the fundamental quantization error. Expressed as a percentage, the quantization error in an eight-bit converter is one part in 255 or Ob %. 12.9.7 Nonlinearity ‘The nonlinearity specification [also referred to as the integral nonlinearity (INL) by some ‘manufacturers of an A/D converter describes is departure from a linear transfer curve, The nonlinearity error does not include gain, offset and quantization errors, Its expressed asa percentage of full scale or in LSBs. 12.98 Differential Nonlinearity Tis indicates the worstcase difference between the actual analogue voltage change and the ideal ‘one-LSB voltage change. The DNL specification is as important as the INL specification, as an A/D converter having a good INL specification may have a poor-quality transfer curve if the DNL specification is poor. DNL is also expressed as a percentage of full scale or in LSBs. DNL in fact explins the smoothness of the transfer characteristics and is thus of great importance to the user. Figure 12.27 shows the transfer curve for a three-bit A/D converter with a 7 V full-scale range, V4-LSB INL and one-LSB DNL. Figure 12.28 shows the same for a 7 V fullscale range, one-LSB INL and 1/4-LSB DNL. Although the former has a much better INL. specification, the later, with 4 better DNL specification, has a much better and smoother curve and may thus be prefered, Too high a value of DNL may even grossly degrade the converter resolution. In a four-bit converter zg oO Zon q 7 1U88 ONL ‘Analog input (v) Figure 12.27 Transfer characteristics ofa thee-bit AID converter (INL = one LSB, DNL = ISB).498 Digital Electronics Digtal Output oO 12a 4567 ‘Analog Input (V) Figure 12.28 Transfer characteristics ofa thre-bit A/D converter (INL = one LSB, DNL = 144 LSB), with a $2 LSB DNL, the 16-step transfer curve may be reduced to a six-step curve. The DNL specification should in no case be ignored, unless the INL specification is tight enough to guarantee the desirable DNL, 12.9.9 Conversion Time ‘This is the time that clapses from the time instant of the start of the conversion signal until the conversion complete signal occurs. It ranges from a few nanoseconds for flash-type A/D converters to «few microseconds for successive approximation type A/D converters and may be as large as tens of ‘milliseconds for dua-slope integrating A/D converters, 129.10 Aperture and Acquisition Times ‘When a rapidly changing signal is digitized, the input signal amplitude will have changed even before the conversion is complete, with the result that the output of the A/D converter does not represent the Signal amplitude atthe star. A sample-and-hold circuit with a buffer amplifier is used at the input of the A/D converter to overcome this problem, The aperture and acquisition times are the parameters of the sample-and-hold cicuit. The signal to be digitized is sampled with an electronic switch that can bbe rapidly tumed ON and OFF. The sampled amplitude is then stored on the hold capacitor. The A/D converter digitizes the stored voltage, and, after the conversion is complete, a new sample is taken and held for the next conversion. The acquisition time is the time required forthe electtonic switeh to close and the hold capacitor to charge, while the aperture time isthe time needed for the switch ‘completely to open after the occurence of the hold signal, Ideally, both times should be zero, The ‘maximum sampling frequency is thus determined by the aperture and acquisition times in addition to the conversion time,ata Conversion Circuits ~ DIA and A/D Converters 499 12.9.1 Code Width ‘The code width isthe quantum of input voltage change that occurs between the output code transitions expressed in LSBs of full scale. Cole wid uncertainty is dhe dynamic variation or jitter in the code ‘width owing to noise. 12.10 A/D Converter Terminology Some of the more commonly used terms while interpreting the specifications and salient features of ‘AID converters are briefly described inthe following paragraphs. 12.10.1 Unipolar Mode Operation In the unipolar mode of operation, the analogue input to the A/D converter varies from 0 to full-scale voltage of one polarity only. 12.102 Bipolar Mode Operation ‘An AID converter configured to convert both positive and negative analogue input voltages is said to bbe operating in bipolar mode. 12.10.3 Coding Coding defines the nature of the A/D converter output data format. Commonly used formats include straight binary, offset binary complementary binary, 2's complement, low byte and high byte 12.104 Low Byte and High Byte In A/D converters with a resolution greater than eight bits, some products are offered in high-byte or Jow-byte format to simplify their interface with eight-bit microprocessor systems. The low-byte output contains the least significant bit and some of al of the lower eight bits ofthe A/D converter outpt In the high byte, the output contains the MSB and some or all of the upper eight bits. 12.105 Right-Justified Data, Left-Justified Data Data bit sets shorter than eight bits are placed in byte-oriented data output format, starting withthe ‘ight side of the data output transfer register. This could apply tothe upper ot lower byte, For example, 4 12-bit ADC will hve four extra bits which could be right justified. Data hit sets shorter than eight bits are placed in left justified data, starting with the left side of the data output transfer register. This could apply to the lower or upper byte. For example, a 12-bit ADC will have four extra bits which could be left juste.500 Digital Electronics 12.10.6 Command Register, Status Register ‘The command register is an intemal register of the ADC that can be programmed by the user (0 select various modes of operation such as unipolar or bipolar mode selection, range selection, data ‘output format selection, ete. The status register indicates the current status of the analogue-to- ‘conversion with a “busy” of “conversion complet” signal 12.10.7 Control Lines Digital inpuvoutput pins that acivatefmonitor and control ADC operation are called control lines. ‘Some examples are chip select, write, start convert, conversion complete, etc. Example 12.5 Determine the resolution of a 12-bit A/D converter having a full-scale analogue input voltage of $V. Solution ‘© A 12-bit A/D converter resolves the analogue input voluge into (2"*— 1) levels * The resolution = 5/(2!* ~ 1) = 5000, (4096 ~ 1) = (5000/4005) = 1.22mV. Example 12.6 ‘The data sheet ofa certain eight-bit A/D converter lists the following specifications: resolution eight bits: full-scale error 0.02 % of full scale; fal-scale analogue input +5 V. Determine (a) the quantization error (in vots) and (b) the total possible error (in vols). Solution (@) The eightbit A/D converter has 2°—1 = 255 steps, Therefore, the quantization error = 5/255 50000255 = 19.607 mV. (b) The fll scale eror = 0.02%o ffullscale = 0.02 x $000/100= 1 mV. Therefor, the total possible error = 19.607 + 1 = 20.607mV. 12.11 Types of A/D Converter Analogue-to-digital converters ae often classified according to the conversion processor the conversion technique used to digitize the signal. Bused on various conversion methodologies, common types ‘of A/D converter include Mash or simultaneous or direc-conversion A/D converters, hall-flash A/D converters, counter-type A/D converters, tracking A/D converters, successive approximation type A/D converters, single-slope, dual-slope and multstope A/D converters and sigma-delta A/D converters, Each of the above-mentioned types of A/D converter is described inthe following paragraphs. 12.111 Simultaneous or Flash A/D Converters ‘The simultaneous method of A/D conversion is based on using @ number of comparators. The number ‘of comparators needed for n-bit A/D conversion is 2"—I. One such system capable of converting anata Conversion Circuits ~ DIA and A/D Converters S01 come. > avis | al “4 R 3 3 | 3 é ve |, oe 3 3 al +2 cone > ol ay Figure 12.29 Two-bitsimultncous AID converter analogue input signal into a two-bit digital output is shown in Fig, 12.29. The analogue signal to be igitized serves as one of the inputs to each of the comparators. The second input for each of the comparators isa reference input, different for each comparator. The reference voltages to be used for ‘comparators ae in general V2", 2V/2", 3V/2", 4V/2" and so on. Here, V is the maximum amplitude ofthe analogue signal that the A/D converter can digitize, and nis the number of bits in the digitized ‘ouput. In the present case of a two-bit A/D converter, the reference voltages forthe tree comparators will be V4, V2 and 3V/4. If we wanted a three-bit output, the reference voltages would have been VIS, V4, 3/8, V2, SV/8, 3V/4 and TVI8. Referting to Fig, 12.29, the output status of various comparators depends upon the input analogue signal V,. For instance, when the input V, ies between Vi and V2, the C, output is HIGH whereas the C, and C, outpus are both LOW. The results are summarized in Table 12.1, The three comparator outputs can then be fed to a coding network (comprising logic gates, etc, to provide two bits that are the digital equivalent ofthe input analogue voltage. The bits at the output of the coding network can then be entered into a flip-flop register for storage. Figure 12.30 shows the arrangement ofa three-bit simultaneous-ype A/D converter. ‘The construction of a simultaneous A/D converter is quite straightforward and relatively easy to understand. However, as the number of bits in the desired digital signal increases, the number of ‘Table 12.1 Sinuitancous or Fash A/D converters, Input analogue 6 G G Pp voltage) ovo v/a Low Low Low. ° ° Vid wv HIGH Low Low ° 1 V2 w3vjs HIGH HIGH Low 1 ° I 1 sv/deV HIGH HIGH HIGH502 “V Digital Electronics nic Encoding Logie [en ouputata Conversion Circuits ~ DIA and A/D Converters 503 comparators required to perform A/D conversion increases very rapidly, and it may not be feasible to tse this approach once the number of bits exceeds six or so. The greatest advantage ofthis technique Ties init capability to execute extremely fast analogue-to-digtal conversion, 12.11.2 Half-Flash A/D Converter ‘The half flash A/D converter, also known as the pipeline A/D converter, i a variant of the Nash-type ‘converter that largely overcomes the primary disadvantage of the high-resolution fullflash converter, namely the prohibitively large number of comparators requited, without significantly degrading its high-speed conversion performance. Compared with a full-fash converter of certain resolution, while the number of comparators and associated resistors is drastically reduced ina half-lash converter, the conversion time increases approximately by a factor of 2. For an a-bit fash converter the number of comparators required is 2"[(2" —1) for encoding of amplitude and one comparator for polarity] while the same for an equivalent half-lash converter would be 2 x 2" In the case of an eight-bit converter, the number is 32 (for halflash) against 256 (for full ash). How itis achieved is explained in the following paragraphs considering the example of an eight-bithalf-llash converter, ‘A halflash converter uses two fullflash converters, with each fullflash converter having a resolution equal to half dhe number of bits of the half-ash converter. That is, an eight-bithalf-fash converter uses two fourbit flash converters, In addition, it uses a four-it D/A converter and an cight-it latch, Figure 12.31 shows the basie architecture of such a converter. The timing and control circuitry is omited for the sake of simplicity. The circuit functions as follows. ‘The mos significant four-bit A/D converter converts the input analogue signal into a coresponding our-bit digital code, which is stored inthe most significant four bits of the output latch This four-bit Agta code, however, represents the low-resolution sample of the input. Simultaneously, iis converted back into an equivalent analogue signal with a four-bit DIA converter. The approximate value of the ‘analogue signal so produced is then subtracted from the sampled value andthe difference is converted Vree) Veer) ‘Analogue Vin Figure 12.31, Fighe-bit half-Mash A/D converter504 Digital Electronics ‘nto digital code using a least significant four-bit A/D converter. The least significant A/D converter is referenced to one-sixteenth (= 1/2) of the reference voltage used by the most significant A/D converter. The new four-bit digital output is fored in the least significant four bits of the output latch. ‘The lateh now contains the eigh-bit digital equivalent of the analogue input. The digitized output is the same as would be produced hy an eight-bitfull-lash converter. The only difference is that the conversion process takes a litle longer. It may also be mentioned bere that the eight-bit half-ash converter ean be used either as a four-bitfullTash converter or as an eigh-bit half-fash converter. ‘Some half-ash converters use single full-lash converter and reuse it for both conversions, This is achieved by using additional sample-and-hold circuitry. 12.113 Counter-Type A/D Converter i possible to construct higher-resolution A/D converters witha single comparator by using a variable reference voltage, One such A/D converter i the countertype A/D converter represented by the block schematic of Fig. 12.32. The circuit functions as follows. To begin with, the counter is rest to all 0s. When a convert signal appears on the start line, the input gate is enubled and the clock pulses are applied to the clock input of the counter, The counter advances through its normal binary count sequence. The counter output feeds a D/A converter and the staircase waveform generated atthe output of the BVA converer forms one ofthe inputs of the comparator. The other input tothe comparator is the analogue input signal. Whenever the DIA converter output exceeds the analogue input voltage, the ‘comparator changes state, The gate is disabled and the counter stop. The counter output at tha instant fof time is then the required digital output corresponding to the analogue input signal ‘The counter-ype A/D converter provides a very good method for digitizing to a high resolution. ‘This method is much simpler than the simultaneous method for higher-resoution A/D converters. The drawback with this converter is that the required conversion time is longer. Since the counter always ‘begins from the all 0s position and counts through its normal binary sequence, it may require as ‘many as 2° counts before conversion is complete. The average conversion time can be taken to be 2"/2=2"! counts. One clock cycle gives one count. As an illustration, if we have a four-bit converter and a 1 MHz clock, the average conversion time would be 8 ms. It would be as large as 0.5 ms for a 10-bit converter of this ype at a 1 MHz clock rte. In fact, the conversion time doubles foreach bit Cock cate Counter Digit Output ‘raioque Convertor Inputs Figure 12.32 Countersype MD conser.ata Conversion Circuits ~ DIA and A/D Converters 505 ‘added to the convener. Thus, the resolution can be improved only atthe cost of a longer conversion time, This makes the countertype A/D converter unsuitable for digitizing rapidly changing analogue signals. 12.114 Tracking-Type A/D Converter Inthe counter-type A/D converter deseribed above, the counter is reset to zero atthe start of each ‘new conversion, The DIA converter output staircase waveform always begins al zero and increases in ‘steps until it reaches a point where the analogue output of the D/A converter exceeds the analogue input to be digitized. As a result, the counter-type A/D converter ofthe type discussed above is slow. The tracking-1ype A/D converter, also called the delta-encoded A/D converter is a modified form of ‘counterype converter that to some extent overcomes the shortcoming of the late. In the modified arrangement, the counter, which is primarily an UP counter, is replaced with an UPIDOWN counter. It counts in upward sequence whenever the DYA converter output analogue voltage is less than the analogue input voltage to be digitized, and it counts in the downvvard sequence whenever the D/A ‘converter output analogue voltage is greater than the analogue input voltage. In this type of converter, ‘whenever a new conversion i t begin, the counter is not reset to zero; in fact it begins counting either up or down from its lst value, depending upon the comparator output. The D/A converter output staircase waveform contains both positive-going and negative-going staircase signals that track the input analogue signal 12.115 Successive Approximation Type A/D Converter ‘The development of A/D converters has progressed in a quest to reduce the conversion time. The secessive approximation type A/D converter aims at approximating the analogue signal to be digitized by trying only one bit ata time. The process of A/D conversion by this technique can be illustrated with the help of an example. Let us take a four-bit successive approximation type A/D converter. Initially, the counter is rset to all 0s. The conversion process begins with the MSB being set by the start pulse. That is, the flip-flop representing the MSB is set. The counter output is converted into an equivalent analogue signal and then compared with the analogue signal to he digitized. A decision is thea taken as to whether the MSB is to be left in (ve. the fip-flop representing the MSB is to remain set) or whether itis tobe taken out (Le. the flip-lop is to be reset) when the frst clock pulse sets the second MSB, Once the second MSB is se, again a comparison is made and a decision taken as to ‘whether or not the second MSB is to remain set wen the subsequent clock pulse sets the third MSB. ‘The process continues until we go down to the LSB. Note that, every time we make a comparison, \we tend fo narrow down the difference between the analogue signal tobe digitized and the analogue signal representing the counter count, Refer to the operational diagram of Fig, 12.33 It is clear from the diagram that, t0 reach any count from 0000 to 1111, the converter requires four clock eyeles. In ‘general, the number of clock cyeles required foreach conversion will be m for an n-bit A/D converter ofthis type. igure 12.34 shows a block schematic representation of a successive approximation type A/D converter. Since only one flip-flop (inthe counter) is operated upon atone time, arin counter, which is nothing but a circulating register (a serial shift register with the outputs QandO of the lst plop connected tthe J and inputs respectively ofthe fit flip-flop) is used to do the job. Referring 0 Fig £2.33, the dark lines show the sequence in which the counter aries atthe desired count, assuming that 1001 is the desired coun. This typeof A/D converter is much faser than the countertype AD converter previously discussed, In an mbit converter, the countrtype A/D converter on average would506 Digital Electronics am a ani < ae ZS st101 Ring i Conta! TT Logie ‘and Clock Digital Output ow converter Figure 12.64 Block schematic representation of «suoessve-pproximation AD convener. require 2°~! clock eyeles for each conversion, whereas a suocessive approximation type converter requires only n clock cycles, That is, an eight-it A/D converter ofthis type operating on a 1 MHz clock has conversion time of 8 ws. 12.1.6 Single-, Dual- and Multislope A/D Converters Figure 12.35 shows a block schematic representation of a single-slope A/D converter. In this type fof converter, one of the inputs to the comparator is a ramp of fixed slope, while the other input is the analogue input t be digitized. The counter and the ramp generator ar intially reset to 0s. Theata Conversion Circuits ~ DIA and A/D Converters 507 Me CIN Timing Binary & o Conte! ‘BCD Contot Reset amp Generator Latches Digital Output Figure 12.38 Block schematic representation of a siagleslope AID convert. ‘counter stats counting withthe frst clock cycle input. The ramp is also synchronized to start with the first clock input. The counter stops when the ramp amplitude equals the analogue input. In this case, the counter count is directly proportional to the analogue signal. It is & low-cost reasonably high-accuracy converter but it suffers from the disadvantage of loss of accuracy owing to changes in the characteristics ofthe ramp generator. Ths shortcoming is overcome ina dual-slope integrating-type A/D convener. Figure 12.36 shows a block schematic arrangement of a dua-slope integrating A/D converter. The converter works as follows. Initially, switch $ is connected to the analogue input voltage Vq to be digitized. The output of the integrator is mathematically given by wee EURO | Vad -VVROU 21) ‘The moment x, tends to go below zero, clock pulses each the clock input terminal ofthe counter which is initially cleared to all 0s, The counter begins counting from 0000... At the (2th clock pulse, ‘the counter is again cleared, the “I” to “0” transition of the MSB of the counter sets Mip-lop that control the state of switch $ which now connects the integrator input toa reference voltage of polarity ‘opposite to that ofthe analogue input. The integrator output moves in the positive direction; the counter has again started counting after being reset (at, say, ‘=7}). The moment te integrator output fends to exceed zet0 the counter stops asthe clock pulses no longer reach the cock input ofthe counter. The counter output at this stage (say, at (= 7.) is proportional to the analogue input. Mathematically, it can be proved that n= (V/V). 2*, where is the count recorded inthe counter at 1=T. Figure 12.37 illustrates the concept further with the help of relevant waveforms. This type of A/D converte is very popular in digital voltmeters owing to its good conversion accuracy and low cost. Also the accuracy is independent of both the integrator capacitance andthe clock frequency, as they affect the negative and positive slope inthe same manner. Yet another advantage of the dual-slope integrator A/D converter is that the fixed analogue input integration period results in rejection of noise frequencies present508 Digital Electronics ee Ly Input id Binary Counter OK ck Qy1 One Ona Qa Figure 12.36 Block schematic epeseatation ofa dual-slope AID converte, He, 4 eg), Ye ? May), Me ys a (Hs) pee) 1 1 1 1 a at Figure 12.37 Relevant waveforms in «das-slope A/D converter in the anatogue input and having time periods that are equal to or submultiples of the integration time, The proper choice of integration time can therefore achieve excellent rejection of S060 He line ripple ‘There are also multislope converter architectures tha ae aimed at further enhancing the performance of integrating A/D converters, For example, the iiple-slope architecture is used to increase theata Conversion Circuits ~ DIA and A/D Converters 509 conversion speed at the cost of added complexity. Increase in conversion speed is accomplished by carying out integration from reference voltage at two distinct rates, a high-speed rate and a low-speed rate. The counter i also divided into two sections, one for MSB bits and the other for LLSB bits. A properly designed triple-slope converter achieves increased conversion speed without compromising the inerent linearity, differential linearity and stability characteristics ofthe dual-slope ‘Bias currents, offset voltages and gain erors associated with operational amplifiers used as integrators and comparators do introduce some erors. These can be eancelled by using ational charge/discharge cycles and then using the results to corret the initial measurement. One such A/D converter is the quad-slope converter which uses two charge/discharge cyeles as compared with one charge/discharge cycle in the case of the dua-slope converter. Quad-slope A/D converters have a much higher accuracy than their dual-slope counterpart, 12.117 Sigma-Delta A/D Converter ‘The sigma-delta A/D converter employs a diferent concept from what has been discussed sofa fr the case of various types of A/D converter. While the A/D converters covered so far rely on sampling of the analogue signal atthe Nyquist frequency and encode the absolute value of the sample, in the case of a sigma-delta converter as explained inthe following paragraphs, the analogue signal is oversampled by a large factor (Le. the sampling frequency is much larger than the Nyquist value), and als itis ‘not the absolute value of the sample but the difference between the analogue values of two successive samples tha is encoded by the converte. In the case of the A/D converters discussed prior to tis and sampled at the Nyquist rate f.. the [RMS value ofthe quantization noise is uniformly distributed over the Nyquist band of DC to f,/2, as shown in Fig. 12.38(a). The signal-to-noise ratio for a full-scale sine wave input inthis case is given by SIN =(6.02n + 1.76) dB, m being the numberof bits, The only way to inerease the signal-to-noise ratio is by increasing the number of bits. On the other hand, a sigma-delta converter attempts to enhance the signal-to-noise mito by oversampling the analogue signal, which has the effect of spreading the noise spectrum over a much larger bandwidth and then filtering out the desired band. If dhe analogue signal ‘were sampled at arate of Kf, the quantization noise would be spread over DC to Ki, a8 shown in Fig. 12.38(6). Kis a constant referred to as the oversampling ratio. The enhanced S/N ratio means higher resolution, which is achieved by other types of A/D converter by way of increasing the number of bits. ‘may be mentioned here that, if we simply use oversampling to improve the resolution, it would be required to oversample by a factor of 2* to achieve an N-bit increase in resolution. The sigma-delta converter does not require to be oversampled by such a large factor because it not only limits the signal pass band but also shapes the quantization noise in such a way that most of it falls outside this pass band, as shown in Fig. 12.38(@), The following paragraphs explain the operational principle of the sigma-delta A/D converter. “The heart ofthe sigma-delta converter isthe delta modulator. Figure 12.39 shows a Block schematic representation of a delta modulator, which is basically a one-bit quantizer of the lash type (single comparator). The output of the delta modulator isa bitstream of 1s and 0s, with the number of 1s relative 10 the number of Os over a given number of clock cycles indicating the amplitude of the ‘analogue signal over that time interval. An all Is sequence over a given interval corresponds t0 the ‘maximum positive amplitude, and an all Os sequence indicates the maximum negative amplitude, An ‘equal numberof Is and Os indicates a zero amplitude, Other values between the positive and negative ‘maxima are indicated by a proportional number of 1s relative to the number of Os. This is further illustrated in Fig. 12.40.sm Digital Electronics ‘Quantization Analogue Noise iit we @ Kis | Dygtal titer Analogue] xD Digtal Femnayed Noiea Nv Converter Fier = ez Kise © T Removes Analogue _| sigma-Deta Digital Noise IN) “Meculator Fier Te Kis cy) Figure 12.38 (3) Quantization noise spectrum with simping atthe Nyquist rate, (b) the quantization noise strum with oversepling and () the quantization aise spectrum with oversampling in a sigmacdls convener, ‘Coming back tothe delta modulator (Fig. 12.39) the input othe one-bit quantizer, which is basically «4 comparator, is from the output of an integrator. The integrator in turn is fed from the difference ‘between the analogue input signal and the analogue equivalent of the quantized output produced by «4 one-bit D/A converter. A one-bit DYA converter is nothing but a two-way swith that feeds either -+Vg¢0F ~V 10 the summing point, depending upon the bit status at its input. The negative Feedback loop ensures that the average value of the D/A converter output nearly equals the analogue input so as to produce a near-zer0 input tothe integrator. ‘An inerease in analogue signal amplitude produces a larger number of Is atthe quantizer output and ‘consequently ahigher average value ofthe analogue signal atthe D/A converte output. This means that the number of Is inthe quantizer output bitstream over a given time interval represents the analogue ‘Signal amplitude, The single-bit data stream can then be encoded ino the desited output format. One ‘Simple way t do tis could be to use a counter to count the numberof 1s in the data stream over fixedata Conversion Circuits ~ DIA and A/D Converters su Kis (Choc) Vo < ‘To Digital ter Trtogrator ‘and Decimator Veer “BA Data stream Veer 2 Figure 12.39 Block schematic epresenaion ofa delta modulator. Max f——— Max |For ‘Quantized output from ‘Sigma-Delta Modulator Figure 12.40, Generation of one-bit data seeam. intervals of time, in which ease the counter output would represent the digital equivalent ofthe analogue signal over those time intervals. roctical sigma-delta A/D converters use a digital decimation filter at the output ofthe deta modulator to process te one-bt data stream to produce an output inthe desired format ‘Sigma-delta A/D converters are widely used for contemporary voice-band, audio and high-resolution precision industrial measurement applications. Their highly digital architecture is ideally suited for such applications as it allows easy addition of digital functionality without significantly increasing the cost, AD 1871 from Analog Devices is one such high-performance A/D converter of sigma-delta architecture intended for digital audio applications.312 Digital Electronics Example 12.7 Determine the conversion time of a 12-bit A/D converter of the counter type shown earlier in Fig 12.32 for an input clock frequency of | MH. Solution * The countertype A/D converter shown i Fig. 12.32 has a variable conversion time this maimum ‘when the input analogue voltage is just below the fll-seale analogue input voltae. + An average conversion time equa t half the maximum conversion ime is usally defined inthe cane of such converter ‘The maximum conversion time equal the ime taken by 22 — 1 The cock time peiod = IM 10°)= I as. Therefore, the maximum conversion time™= 4098 x The average conversion time (1095/2) =2.047 ms 4095 cycles of clock input. 1095 ps =4.095 ms, Example 12.8 The D/A converter of a counter-type A/D converter (refer to Fig, 12.32) produces a staircase output having a step size of 10 mV. The A/D converter has a 10-bit resolution and is specified to have a ‘quantization error of +1/2 LSB. Determine the digital output for an analogue input of 4012 V. Assume ‘thatthe comparator has a comparison threshold of 1 mV. Solution {© The comparator has 4 comparison threshold of 1 mY. ‘© With reference to Fig. 12.32, this implies that, forthe comparator to change stat, the voltage atthe relevant input should be 1 mV more than the voltage atthe other input. ‘© Now, one ofthe inputs to the comparator isthe analogue input voltage case). ‘© The other input to the comparator is a vollage that is equal tothe sum of the DVA converter output voltage and a fixed voltage corresponding to 1/2 LSB. ‘© This is the ease when the quantization error of the A/D converter is specified to be + V/2 LSB. ‘In the case of a quantization error of one LSB, the D/A converter directly feeds the other input of the comparator. ‘Inthe present case, one LSB corresponds to 10 mV. ‘© Therefore, /2 LSB corresponds to 5 mV. ‘© For an analogue input of 4.012 V, the voltage at the other input needs fo be 4.013 V (owing to the ‘comparator threshold of 1 mV). ‘© This implies thatthe D/A converter output needs to be 4.08 V. ‘© Therefore, the number of steps = 4.008/(10 x 10-°) =400.8 = 401 ‘© The digital output isthe binary equivalent of (401) 9,which equals 0110010001 (012 V in the present Example 12.9 ‘A 10-bit A/D converter ofthe successive approximation type has a resolution (or quantization error) (of 10 mV. Determine the digital output for an analogue input of 4.365 V.ata Conversion Circuits ~ DIA and A/D Converters 513 Solution In the case ofa successive approximation type A/D converter, the final analogue output of its D/A. converter portion always setles ata value below the analogue input voltage to be digitized within the resolution of the converter. 4 The analogue input voltage ‘© The resolution = 10 mV. {The number of steps =4.365/(10 x 10-9) = 436.5. * Step number 436 will produce a D/A converter output of 436 x 10 = 4360mV = 4.36V, and step number 437 will produce a DyAcomverter of 4.37 V. ‘© The AID converter will sete at step 436. ‘© The digital output wll be the binary equivalent of(436), which is 0110110100. 365 V. Note. When this converter actually performs the conversion, in the tenth clock cycle, the LSB will be sotto “I” iitally. This would produce « BYA converter output of 4.37 V which exceeds the analogue input voltage of 4.365 V. The comparator changes state, which in turn resets the LSB to 0", bringing the DIA converte output to 4.36 V. This is how a converter of this type setles where a DIA eonverter ‘output settles ata value that is one step below the value that makes it exceed the analogue input to be ined, Example 12.10 Compare the average conversion time ofan ei successive approximation type A/D converter if both are working at a 10 MI u-bitcounter-ype A/D converter with that ofan eight-bit Tock frequency. Solution © The clock time period = 0.1 ps. © The average conversion {(2%=1)/2}x0.1 = 12.75ps. ‘© The conversion time in the case of a successive approximation type A/D converter is given by 8x01 =08 ps. the case of a countertype A/D converter is given by 12.12 Integrated Circuit A/D Converters ‘This section presents applicaton-relevant information of some of the popular A/D converter IC type ‘numbers, a itis not possible to give a detailed description of each one of them. The type numbers included for this purpose are ADC 0800, ADC 0808, ADC 80, ADC 84, ICL TIO6/ICL. 7107 and AD 7820, 12.121 ADC-0800 ADC-0800 is a successive approximation type eightbit A/D converter. The intemal architecture of ‘ADC-0800 is shown in Fig. 1241. The digital output isin complementary form and is also tstate to permit bussing on common data lines. ts salient features include ratiometric conversion, no missing ‘odes, tristate outputs and a conversion time of 50 ps (typical), 1-LSB linearity anda cock frequeney range of 50-800 kHz,su Digital Electronics Network ‘Vge(PMOS “op Boy) 7 ' I { P-Resistor { NBody 1 | aso: 5 i fen Selection { 256A ad | | 9008 | network conto i Analog ——~4 : ' Switehes I I 1 | 900 ' — ! 4 et 1 | aso: a atch I J ' ' I I I | ' I I — I | Comparator | 4 5 e a{s|2| 1 7hshahs Rnetwork Vin MSO pment “2 Botom Analog omplementary input ital tout Figure 1241 Internal architecture of AD 0800. Figures 12.42(a) and (b) show application circuits using AD-O800, Figure 12:42(a) shows typical cireuit connections for a +5 V input voluge range and TTL-compatible output levels. whereas Fig, 12.42(0) shows the connections for a 0-10 V input range and 0-10 V output levels. 12.12.2 ADC-0808 ADC 0808 is an eight-bit CMOS successive approximation type A/D converter. The device has fan eight-channel multiplexer and a microprocessor-compatible control logic. Salient features of the device include eighc-bit resolution, no missing codes, a conversion time of 100 4s (typical),