Difference between Interrupt and Exception

Interrupt is one of the classes of Exception.

There are 4 classes of Exception- interrupt, trap, fault and abort.
Though, interrupt belongs to exception still there are many differences between them.
Def: In any computer, during its normal execution of a program, there could be events that can
cause the CPU to temporarily halt. Events like this are called interrupts.
Interrupts can be caused by either software or hardware faults. Hardware interrupts are called
Interrupts, while software interrupts are called Exceptions. Once an interrupt is raised, the
control is transferred to a special sub-routine called Interrupt Service Routine (ISR), that can
handle the conditions that are raised by the interrupt.
What is Trap, Fault and Abort ?
1. Trap –
It is typically a type of synchronous interrupt caused by an exceptional condition
(e.g., breakpoint, division by zero, invalid memory access).
2. Fault –
Fault exception is used in a client application to catch contractually-specified
SOAP faults. By the simple exception message, you can’t identify the reason of
the exception, that’s why a Fault Exception is useful.
A SOAP fault is an error in a SOAP (Simple Object Access Protocol)
communication resulting from incorrect message format, header-processing
problems, or incompatibility between applications. ... A message that includes
a fault element is known as a fault message.
3. Abort –
It is a type of exception occurs when an instruction fetch causes an error.

What is Interrupt?

The term Interrupt is usually reserved for hardware interrupts. They are program control
interruptions caused by external hardware events. Here, external means external to the CPU.
Hardware interrupts usually come from many different sources such as timer chip, peripheral
devices (keyboards, mouse, etc.), I/O ports (serial, parallel, etc.), disk drives, CMOS clock,
expansion cards (sound card, video card, etc). That means hardware interrupts almost never
occur due to some event related to the executing program.
Example –
An event like a key press on the keyboard by the user, or an internal hardware timer timing out
can raise this kind of interrupt and can inform the CPU that a certain device needs some
attention. In a situation like that the CPU will stop whatever it was doing (i.e. pauses the current
program), provides the service required by the device and will get back to the normal program.
When hardware interrupts occur and the CPU starts the ISR, other hardware interrupts are
disabled (e.g. in 80×86 machines). If you need other hardware interrupts to occur while the ISR
is running, you need to do that explicitly by clearing the interrupt flag (with sti instruction). In
80×86 machines, clearing the interrupt flag will only affect hardware interrupts.
Difference between Interrupt and Exception:

INTERRUPT EXCEPTION

These are Hardware interrupts. These are Software Interrupts.

Occurrences of hardware interrupts

usually disable other hardware

interrupts. This is not a true case in terms of Exception.

These are synchronous internal requests for

These are asynchronous external service based upon abnormal events (think of

requests for service (like keyboard illegal instructions, illegal address, overflow

or printer needs service). etc).

Being synchronous, exceptions occur when

Being asynchronous, interrupts can there is abnormal event in your program like,

occur at any place in the program. divide by zero or illegal memory location.

These are normal events and

shouldn’t interfere with the normal These are abnormal events and often result in

running of a computer. the termination of a program

Interrupt Cycle:

 An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-execute

cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a
computer retrieves a program instruction from its memory, determines what actions
the instruction requires, and carries out those actions. This cycle is repeated
continuously by the central processing unit (CPU), from bootupto when the computer
is shut down.

Block diagram of Interrupt Cycle

 After the execute cycle is completed, a test is made to determine if an interrupt was
enabled (e.g. so that another process can access the CPU)
 If not, instruction cycle returns to the fetch cycle
 If so, the interrupt cycle might performs the following tasks: (simplified...)
 move the current value of PC into MBR
 move the PC-save-address into MAR
 move the interrupt-routine-address into PC
 move the contents of the address in MBR into indicated memory cell
 continue the instruction cycle within the interrupt routine
 after the interrupt routine finishes, the PC-save-address is used to reset the value of
PC and program execution can continue
Content:

 Introduction
 Interrupts
 Purpose of interrupts
 Types of interrupts
 Interrupt Service Routine
 Interrupt vector table
 8086 Interrupts
 Interrupt priority
 8086 INTERRUPT PINS AND TIMING
Introduction
Interrupt is one of the most important features in the microcontroller/processor applications.
In this chapter we will explore the concept of interrupts and interrupt programming. Consider
a microprocessor system receiving data and change in status from I/O port or device. There
are two methods available to obtain input: Polling & Interrupts.

In INTERRUPT method, whenever any device needs service from microprocessor, the device
notifies to processor by sending signal (called interrupt). Upon receiving an interrupt signal,
the microprocessor holds whatever it is doing and serves the corresponding device.The
program associated with the interrupt is called the interrupt service routine(ISR) or interrupt
handler.

In POLLING method, the microprocessor continuously monitors the status of a given device;
when the status condition is met, it performs the service. After that, it moves on to the next
device until each one is serviced. Although polling can monitor the status of several devices
and serve each of them if certain conditions are met.

Interrupt
An INTERRUPT is a condition that causes the microprocessor to temporarily work on a
different task and then return to its previous task. Interrupt is an event or signal that request to
attention of CPU.

Whenever an interrupt occurs the processor completes the execution of the current instruction
and starts the execution of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a
program that tells the processor what to do when the interrupt occurs. After the execution of
ISR, control returns back to the main routine where it was interrupted.

Whenever an interrupt is occurred, it will be acknowledged by the processor at the end of the
current memory cycle. The processor then services the interrupt by branching to a special
service routine written to handle that particular interrupt. Upon servicing the device, the
processor is then instructed to continue with what is was doing previously by use of the
"return from interrupt" instruction.
The status of the program being executed must be saved first. The processors registers will be
saved on the stack, or at very least, the program counter will be saved. Preserving those
registers which are not saved will be the responsibility of the interrupt service routine. Once
the program counter has been saved, the processor will branch to the address of the service
routine.

Figure: Interrupt processing flow

Purpose of Interrupts
As we studied, the Microprocessor can serve several devices. There are two ways to offer
service: Interrupts and Polling.

 The advantage of interrupts is that the microprocessor can serve many devices
(not all at the same time, of course); each device can get the attention of the
microprocessor based on the priority assigned to it.
 The polling method cannot assign priority because it checks all devices in a
round-robin fashion.
 More importantly, in the interrupt method the microprocessor can also ignore
(mask) a device request for service.
 This is not possible with the polling method.
 The most important reason that the interrupt method is preferable is that the
polling method wastes much of the microprocessor’s time by polling devices that
do not need service.
 So interrupts are used to avoid tying down the microprocessor.
To understand the difference better, consider this example. The polling method is very much
similar to a salesperson. The salesman goes door-to-door requesting to buy his product. Like
processor keeps monitoring the flags or signals one by one for all devices. Interrupt is very
similar to a shopkeeper. Whosever needs a service or product goes to him and approaches
him. Like, when the flags or signals are received, they notify the processor that they need its
service.

Interrupts are useful when interfacing I/O devices with low data-transfer rates, like a
keyboard or a mouse, in which case polling the device wastes valuable processing time

Above time line shows typing on a keyboard, a printer removing data from memory, and a
program executing. The keyboard interrupt service procedure, called by the keyboard
interrupt, and the printer interrupt service procedure each take little time to execute

Types of Interrupts
In general there are two types of Interrupts:

 Internal (or) Software Interrupts are triggered by a software instruction and

operate similarly to a jump or branch instruction.
 External (or) Hardware Interrupts are caused by an external hardware module.

SOFTWARE INTERRUPTS–
INT nn is invoked software (sequence ofcode)

Examples:
DOS INT 21H, BIOS INT 10H.

INT 00 (divide error)

INT 01 (single step)

INT 03 (breakpoint)

INT 04 (signed number overflow)

HARDWARE INTERRUPTS
Hardware interrupts are generated by hardware devices when something unusual happens;
this could be a key-press or a mouse move or any other action.

Maskable Interrupts:
The processor can inhibit certain types of interrupts by use of a special interrupt mask bit.
This mask bit is part of theflags/condition code register, or a special interrupt register. In the
8086 microprocessor if this bit is clear, and aninterrupt request occurs on the Interrupt
Request input, it is ignored.

Non-Maskable Interrupts:
There are some interrupts which cannot be masked out or ignored by the processor. These are
associated with highpriority tasks which cannot be ignored (like memory parity or bus faults).
In general, most processors support the Non-Maskable Interrupt (NMI). This interrupt has
absolute priority, and when it occurs, the processor will finish thecurrent memory cycle, then
branch to a special routine written to handle the interrupt request.

Interrupt Service Routine

For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler.
When an interrupt is invoked, the microprocessor runs the interrupt service routine. For every
interrupt, there is a fixed location in memory that holds the address of its ISR. The group of
memory locations set aside to hold the addresses of ISRs is called the interrupt vector table.

When an interrupt is occurred, the microprocessor stops execution of current instruction. It

transfers the content of program counter into stack. It also stores the current status of the
interrupts internally but not on stack. After this, it jumps to the memory location specified by
Interrupt Vector Table (IVT). After that the code written on that memory area will execute.

Interrupt Vector Table

The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing
thestarting addresses of Interrupt Service Procedures(ISP).Since 4-bytes are required for
storing starting addresses of ISPs, the table can hold 256 Interrupt procedures.

The starting address of an ISP is often called theInterrupt Vector or Interrupt Pointer.
Therefore the table is referred as Interrupt Vector Table. In this table, IP value is put in as low
word of thevector & CS is put in high vector.
8086 Interrupts
We are aware of the fact that the interrupt can be either hardware or software. If the interrupts
are generated by the inbuilt devices, like timers or by the interfaced devices, they are called
as hardware interrupts. If the interrupts are generated by the software code, they are called as
software interrupts.

In other words an 8086 interrupt can come from any one of three sources.

1. An external signal applied to the non-maskable interrupt (NMI) input pin or to

the interrupt input pin (HARDWARE INTERRUPT).
2. Execution of the interrupt instruction (SOFTWARE INTERRUPT)
3. Some error condition produced in the 8086 by the execution of an instruction.
Example:
If you attempt to divide an operand by zero, the 8086 will automatically interrupt the
currently executing program. At the end of each instruction cycle, the 8086 checks to see if
any interrupts have been requested. If an interrupt has been requested, the 8086 responds to
the interrupt by stepping through the following series of major actions:

 It decrements the stack pointer by 2 and pushes the flag register on the stack.
 It disables the 8086 INTR interrupt input by clearing the interrupt flag in the flag
register.
 It resets the trap flag in the flag register.
  It decrements the stack pointer by 2 and pushes the current code segment register
contents on the stack.
 It decrements the stack pointer again by 2 and pushes the current instruction
pointer contents on the stack.
Divide-By-Zero Interrupt-Type 0:
The 8086 will automatically do a type 0 interrupt if the result of a DIV operation or an IDIV
operation is too large to fit in the destination register. For a type 0 interrupt, the 8086 pushes
the flag register on the stack, resets IF and TF and pushes the return addresses on the stack.

Single Step Interrupt-Type 1:

The use of single step execution feature is found in some of the monitor & debugger
programs. When we tell a system to single step, it will execute one instruction and stop. We
can then examine the contents of registers and memory locations.

In other words, when in single step mode a system will stop after it executes each instruction
and wait for further direction from user. The 8086 trap flag and type 1 interrupt response
make it quite easy to implement a single step feature direction.

Non-maskable Interrupt-Type 2:
The 8086 will automatically do a type 2 interrupt response when it receives a low to high
transition on its NMI pin. When it does a type 2 interrupt, the 8086 will push the flags on the
stack, reset TF and IF, and push the CS value and the IP value for the next instruction on the
stack. It will then get the CS value for the start of the type 2 interrupt service procedure from
address 0000AH and the IP value for the start of the procedure from address 00008H.

Breakpoint Interrupt-Type 3:
The type 3 interrupt is produced by execution of the INT3 instruction. The main use of the
type 3 interrupt is to implement a breakpoint function in a system. Whenever we insert a
breakpoint, the system executes the instructions up to the breakpoint and then goes to the
breakpoint procedure.

Overflow Interrupt-Type4:
The 8086 overflow flag will be set if the signed result of an arithmetic operation on two
signed numbers is too large to be represented in the destination register or memory location.

Example: If we add the 8 bit signed number 01101100 and the 8 bit signed number
010111101, the result will be 10111101. This would be the correct result if we were adding
unsigned binary numbers, but it is not the correct signed result.

Software Interrupts-Type O through 255:

The 8086 INT instruction can be used to trigger the 8086 to do any one of the 256 possible
interrupt types. The desired interrupt type is specified as part of the instruction.

The instruction INT32, for example will cause the 8086 to do a type 32 interrupt response.
The 8086 will push the flag register on the stack, reset TF and IF, and push the CS and IP
values of the next instruction on the stack.

INTR Interrupts-Types 0 through 255:

The 8086 INTR input allows some external signal to interrupt execution of a program. Unlike
the NMI input, however, INTR can be masked so that it cannot cause an interrupt. If the
interrupt flag is cleared, then the INTR input is disabled. IF can be cleared at any time with
CLEAR instruction.

Figure: 8086 Interrupt Instructions.

Interrupt Priority
If two or more interrupts occur at the same time then the highest priority interrupt will be
serviced first, and then the next highest priority interrupt will be serviced.

Example: If suppose that the INTR input is enabled, the 8086 receives an INTR signal
during the execution of a divide instruction, and the divide operation produces a divide by
zero interrupt. Since the internal interrupts-such as divide error, INT, and INTO have higher
priority than INTR the 8086 will do a divide error interrupt response first.

The interrupt that has a lower address, has a higher priority.

For example, the address of external interrupt 0 is 2, while the address of external interrupt 2
is 6; thus, external interrupt 0 has a higher priority, and if both of these interrupts are
activated at the same time, extern al interrupt 0 is served first.

8086 Interrupt Pins and Timing

 INTR: Interrupt Request. Activated by a peripheral device to interrupt the

processor.
o Level triggered. Activated with a logic 1.
 INTA: Interrupt Acknowledge. Activated by the processor to inform the
interrupting device the interrupt request (INTR) is accepted.
o Level triggered. Activated with a logic 0.
 NMI: Non-Maskable Interrupt. Used for major system faults such as parity errors
and power failures.
o Edge triggered. Activated with a positive edge (0 to 1) transition.
o Must remain at logic 1, until it is accepted by the processor.
o Before the 0 to 1 transition, NMI must be at logic 0 for at least 2
clock cycles.
o No need for interrupt acknowledgement.