1352 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO.

3, MARCH 2021

Source/Drain Extension Doping Engineering for

Variability Suppression and Performance
Enhancement in 3-nm Node FinFETs
Peng Lu , Benjamin Colombeau, Member, IEEE, Steven Hung, Weicong Li , Member, IEEE,
Xicheng Duan, Yifei Li, El Mehdi Bazizi, Sanjay Natarajan, and Jason C. S. Woo, Fellow, IEEE

Abstract — In this article, variability suppression and Various research has focused on process and statistical
performance enhancement through source/drain exten- variability in ultrascaled transistors. Statistical variations, such
sion (SDE) module engineering is demonstrated in 3-nm as metal gate granularity (MGG), have been reported as
node fin field-effect transistors (FinFETs). The process
variabilities induced by different modules are systemat- significant variability sources [7]. With advanced process
ically quantified in 3-nm node FinFETs using fully cali- technologies [7], their impact can be largely reduced. In ultra-
brated technology computer-aided design (TCAD) tools. scaled FinFETs, performances have become increasingly sen-
With experimentally characterized geometry parameters sitive to detailed geometry parameters [8], [9]. Therefore,
and their variation ranges, the fin and the SDE module realistic module parameters instead of idealized geometries
are identified as the main variability sources. The unique
device performances induced by the realistic fin and SDE are required for variability analysis. In addition, rather than
modules are interpreted. Previously developed for perfor- semiclassical models [10], quantum mechanical models are
mance enhancement in 7- and 10-nm node FinFETs, 3-D SDE needed.
doping profile engineering can effectively reduce fin and The source/drain extension (SDE) module engineering has
SDE module-induced variabilities by 4.0 × (2.7 ×) and 1.8 × been shown to be a critical factor for performance enhance-
(2.1 ×) in 3-nm node n-(p-)FinFETs, respectively. In addition,
the precise control of the vertical SDE profile enables a ment in 7- and 10-nm nodes [11], [12]. The fin recess etch
new dimension for design optimization. An optimization process is also identified as a significant variation source [11].
methodology for the 3-D SDE doping profile is demon- Therefore, its impact needs to be quantified in the 3-nm node.
strated, achieving a 7% (10%) ON-state current enhancement In addition, advanced source/drain (S/D) formation technology
in 3-nm node n-(p-)FinFETs. has been developed to precisely control the fin top recess
Index Terms — 3-nm node, fin field-effect transistor length (LR) and the vertical profile in the fin height (Hfin )
(FinFET), optimization methods, source/drain extension
direction, enabling new dimensions of freedom for design
(SDE), technology computer-aided design (TCAD) simula-
tion, variability. optimizations. To the best of the authors’ knowledge, no
optimization methodology has been proposed for the 3-D SDE
I. I NTRODUCTION doping profile.

F IN field-effect transistor (FinFET) has been the

mainstream technology on the very large scale integra-
tion (VLSI) platform for logic applications since the 22-nm
In this article, a systematic technology computer-aided
design (TCAD) analysis is performed to quantify different
modules’ contributions in variability in 3-nm node FinFETs.
node [1]. Although alternative technologies such as nanosheet The 3-D SDE doping profile engineering can be utilized to
FETs [2] and vertical nanowire FETs [3] have been proposed effectively suppress process-induced variability with minimal
as candidates for sub-10-nm nodes, FinFET is predicted to modification in the FinFET process flow. A 3-D SDE doping
be used in the future 3-nm node [4]. In aggressively scaled profile optimization method is proposed to achieve 7% (10%)
FinFETs, the process-induced variation, which is already a key on-state current (ION ) improvement in n-(p-)FinFETs.
limit in 10- and 14-nm node FinFETs [5], [6], is becoming
even more severe. Consequently, it is critical to suppress
device performances’ sensitivities to the geometry variations II. S IMULATION S ETUP AND C ALIBRATION
in future FinFETs. In this article, the simulated 3-nm node FinFET struc-
Manuscript received September 6, 2020; revised October 22, 2020, ture is shown in Fig. 1. The nominal physical parameters
November 24, 2020, and December 26, 2020; accepted January 8, and the realistic variations ranges (Table I) are character-
2021. Date of publication February 2, 2021; date of current version ized from AMAT’s advanced module process (Fig. 2), which
February 24, 2021. The review of this article was arranged by Editor
L. Ge. (Corresponding author: Peng Lu.) are developed for the future 3-nm node technology [13].
Peng Lu, Weicong Li, Xicheng Duan, Yifei Li, and The subfin is relatively heavily doped (1018 cm−3 ) through
Jason C. S. Woo are with the Department of Electrical and Computer in situ epitaxy. Advanced fin trimming technology [Fig. 2(a)]
Engineering, University of California, Los Angeles, CA 90095 USA
(e-mail: [email protected]). can be employed to realize well-controlled fin width
Benjamin Colombeau, Steven Hung, El Mehdi Bazizi, and Sanjay (Wfin , defined as the silicon thickness, TSi , at the fin top)
Natarajan are with the Applied Materials, Sunnyvale, CA 94085 USA. and taper angle (θ ). A low-temperature shallow trench iso-
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2021.3052432. lation (STI) formation [14] can be utilized to suppress the
Digital Object Identifier 10.1109/TED.2021.3052432 subfin dopant diffusion, forming a steep junction [Fig. 1(b)].
0018-9383 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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LU et al.: SDE DOPING ENGINEERING FOR VARIABILITY SUPPRESSION 1353

Fig. 1. Schematic of simulated 3-nm node FinFETs. (a) 3-D structure,

(b) fin geometry and the gate-stack, (c) and (d) schematic of the vertically Fig. 3. SDE junction doping profile setup. (a) Schematics of the 2-D
uniform and nonuniform SDE doping profile, respectively (not to scale). doping (not to scale), (b) LG direction doping profile near the S/D junction,
An abrupt junction between the sub-fin and the active fin is assumed. (c) S/D junction profiles simulated in this article, and (d) SIMS data of
doping diffusion gradient.
TABLE I
G EOMETRY PARAMETERS AND T HEIR VARIATION R ANGES profile extracted from process result (Fig. 2(b), referred to
as the V-shape profile); and the optimized profiles proposed
in the article. Secondary ion mass spectrometry (SIMS) data
[Fig. 3(d)] show a steep junction dopant gradient (∼2 nm/dec)
in n-FETs. Since the SDE doping is formed by dopant diffu-
sion, it is reasonable to assume that the diffusion is isotropic,
and the lateral diffusion gradient is similar to the vertical
value. The SDE doping in p-FET can be designed to be similar
to that in n-FETs for performance matching [15]. Therefore,
p-FETs’ B gradient is assumed to be 2 nm/dec. The S/D
contact resistivity (ρC ) is assumed to be 1 × 10−9 ·cm2 [16].
Sentaurus TCAD tools are used for variability studies.
A self-consistent 2-D Schrodinger equation and Poisson’s
equation solver [17] is used to capture the carrier quantum
confinement. Using the k·p approach [18] to calculate the
thin film’s impact on the band structure, the model can
accurately reproduce nanosheets’ capacitances with TSi from
4 to 9 nm [19]. The deformation potential model [20] is used
to capture the impact of the uniaxial stress (extracted from
process simulations) in s-SiGe p-FinFETs. A drift-diffusion
model with modified saturation velocity, capable of emulating
the quasi-ballistic carrier velocity profile for L G > 10 nm [21],
is utilized for carrier transport. Thin-film mobility models
calibrated to ultrathin body transistors [22], [23] are also
included. A calibrated band-to-band tunneling model [24] is
used to simulate the tunneling leakage. Combined with prop-
erly modeled fin and SDE, the simulations agree with various
technology nodes’ experimental data (Fig. 4) [15], [23], [25],
adding credibility to the analysis.
Fig. 2. Advanced module process results for characterization. (a) Fin
geometry achieved by AMAT, and (b) 3-D SDE junction profile [11].
III. Q UANTIFICATION OF P ROCESS -I NDUCED
A double-layered gate-stack is simulated. The heavily doped VARIABILITY AND P HYSICAL I NTERPRETATION
S/D regions are formed by an in situ epitaxy [11]. The SDE The FinFET variabilities induced by the examined sources
doping is induced by the S/D dopant diffusion and has an are summarized in Fig. 5. The fin geometry’s variability is
error function shape (Fig. 3). Three S/D junction profiles induced by the Wfin and θ ’s covariation. The ION and IOFF
[Fig. 3(c)] are simulated and compared: the vertically uniform are calculated by the equation: (maximal – minimal)/nominal
profile in conventional FinFETs; the vertically nonuniform value. Since ultrascaled transistors are extensively sensitive

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1354 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO. 3, MARCH 2021

Fig. 4. Simulation results match the experimental data. (a) Intel’s Fig. 6. Device performance in an n-FinFET with a vertically uniform
10/14-nm n-FinFET, and (b) Intel’s 14-nm and GlobalFoundries (GF’s) SDE profile (LR = 0 nm). (a) Current density evolution (VDS = 0.7 V),
silicon on insulator (SOI) p-FinFET [15], [23], [25]. and (b) OFF-state barrier profile in the middle of the Wfin .

Fig. 7. Fin module-induced variability in an n-FinFET with a vertically

uniform SDE profile, LR = 0 nm. (a) IOFF –ION distribution, (b) and (c)
IOFF and ION as a function of Tleakage and Taverage , respectively.

the drain fringing field is approximately uniform along the

Fig. 5. IOFF and ION variation induced by various sources in n- and
p-FinFET with vertically uniform SDE profile (geometry variation ranges
Hfin direction. Since tapered fins [Fig. 2(a)] are formed to
in Table I). enhance the robustness, the subfin TSi is ∼2.5 nm larger than
the Wfin , leading to a relatively weak local gate control, and
to detailed physical parameters, this article studies FinFETs a lower barrier height compared to the fin top [Fig. 6(b)],
with realistic fin geometries instead of idealized fins (θ = 0◦ ). forming a localized leakage path. The OFF-state current is
TCAD analysis demonstrates the unique current distribution’s exponentially modulated by the change in the barrier height
evolution (Fig. 6) and sensitivities to geometry parameters in and the quantum confinement’s ground-state energy (E 0 ).
realistic FinFETs. With sufficient published process results, In the relatively heavily doped subfin, the barrier is pulled
variabilities induced by different modules in Intel’s 14-nm up by the build-in potential [Fig. 6(b)], and the punchthrough
node FinFETs can be accurately isolated. Therefore, it is leakage is suppressed [Fig. 6(a)].
used as a reference to demonstrate the evolution of process- The fin geometry’s variation has a substantial impact on
induced variabilities (Fig. 5). Although the variation ranges the virtual cathode and the IOFF (Fig. 5). The leakage path
of geometry parameters have been reduced through advanced barrier height is extensively sensitive to the local TSi (Tleakage ).
process techniques, the variations in percentage increase as Since the leakage path is close to the subfin, Tleakage ≈
the nominal values are scaled down. Therefore, the 3-nm node Wfin + 2 × Hfin × tan(θ ). An increase in Wfin or θ can lead
is extensively sensitive to process-induced variations. The fin to a larger Tleakage , degrading the local electrostatic control,
module is the dominating contributor for IOFF . Both the fin reducing the virtual cathode barrier height, and increasing the
and the SDE (LR) are major sources for ION . Thanks to IOFF (Fig. 7). This is analogous to the IOFF ’s dependence on
the tight poly pitch (L G ) variation control, the L G is not a TSi in double-gate (DG) FETs [25], except the leakage path is
significant contributor to ION /IOFF . To identify the physical localized in the fin instead of extending across the entire width
mechanisms, n-FinFETs with various geometry parameters are in DG FETs. Quantitatively, the virtual cathode barrier height
studied in detail, and the differences between n- and p-FETs is approximately linearly related to the Tleakage . Increasing the
are discussed. Tleakage from 7 to 8 nm can lead to a 22 meV reduction in the
OFF -state barrier height and has a dominating impact on IOFF ’s
A. IOFF Variation increase. Meanwhile, the E 0 is also reduced by 7 meV, further
The subthreshold current is controlled by the diffusion increasing the IOFF . As a result, the IOFF is approximately
across the virtual cathode (the location where minimum energy exponentially related to the Tleakage [Fig. 7(b)]. Since a large
barrier occurs) and is governed by the gate electrostatic control Hfin is desired to improve the ION , the θ -induced Tleakage
competing with the drain fringing field. The former is sensitive is increasingly critical. The θ and Wfin covariation can lead to
to the gate-stack and the silicon thickness (TSi ), while the latter ±3 nm Tleakage , and consequently cause ∼630 ×IOFF .
is strongly affected by the SDE dopant encroachment [11]. The gate module has a significant impact on electrostatic
In an n-FinFET with a vertically uniform SDE (Fig. 3), control, and consequently affects constant current threshold

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LU et al.: SDE DOPING ENGINEERING FOR VARIABILITY SUPPRESSION 1355

Fig. 10. DG FETs’ performance as a function of TSi . (a) Transfer

Fig. 8. Gate-stack-induced performance variation in 3-nm node characteristics and (b) extracted JON and ΔVTH values. The DG FETs
n-FinFET. (a) Transfer characteristics, and (b) Cdielectric and CG versus have the nominal geometry parameters (except TSi ) and doping profile
gate dielectric EOT. listed in Table I.

counter-balancing the CSi increase’s effect. More importantly,

the TSi scaling causes an ∼14.5 mV/nm linear reduction in the
threshold voltage (VTH , defined as the linearly extrapolated
threshold voltage, Fig. 10). Since a FinFET with a tapered
fin is analogous to DG FETs with different TSi in parallel,
ION is sensitive to the average TSi (Taverage ), and Taverage ≈
Wfin + Hfin × tan(θ ). Although the Taverage can affect
the mobility and CSi , the transconductance’s (gm ) change is
relatively small (<5%). As a result, ION ≈ VTH × gm .
Fig. 9. ±1 nm ΔLR-induced performance variation in n-FinFETs with Since the VTH is linearly related to the TSi , the ION shows a
vertically uniform SDE doping profiles.
linear relation to the Taverage [Fig. 7(c)].
voltage (VTS , defined as the VGS at IDS = 10 μA/μm and The gate module has a substantial impact on previous
VDS = 0.7 V), subthreshold slope (SS), and IOFF . How- generations of transistors’ ION . However, this is not observed
ever, the equivalent oxide thickness (EOT) is well controlled in the 3-nm node. In the nominal fin [Fig. 1(c)], the CSi is
(±0.05 nm) by advanced gate-stack formation techniques, and extracted to be 6.68 μF/cm2 (5.2 Å EOT) and is comparable
the IOFF caused by the EOT is relatively small (∼50%, to COX (6 Å EOT). An EOT from 6.5 to 5.5 Å leads to only
Fig. 8). a 9% increase in C G [Fig. 8(a)]. In addition, the high electric-
The subthreshold performances are increasingly sensitive to field mobility degradation counterbalances the increase in
the SDE module as devices are scaled down. In 3-nm node carrier density, and the 3-nm node has a small ION caused
n-FinFETs with vertically uniform SDE profiles, when the LR by EOT.
increases from −1 nm (effectively caused by a thick spacer) The SDE doping profile has a substantial impact on the
to 1 nm (over-etch in the fin recess), the dopant encroachment R S/D and gate overdrive, both contributing to ION . In 3-nm
results in a stronger coupling between the virtual cathode and node FinFETs, the contact resistance is calculated to be
the drain fringing field (analogous to drain induced barrier ∼170 /fin per side, and the R S/D is dominated by the RSDE
lowering (DIBL) in planar FETs), degrading the SS and IOFF (Fig. 9). Increasing the LR from −1 to 1 nm can increase
(Fig. 9). The ±1 nm LR leads to ∼31 mV VTS . It is the dopant in the SDE [Fig. 1(c)] and reduce RSDE by ∼40%.
comparable to VTS induced by MGG, which is reported to Combined with the increased VGT , an ∼30% higher ION is
be a significant variability source [7]. observed.

C. Comparison Between n- and p-FinFET

B. ION Variation
In s-Si0.75 Ge0.25 channel p-FET, the relatively small
Unlike the localized IOFF , ION flows almost uniformly
bandgap leads to a ∼3 nA/μm tunneling leakage, which
through the fin (Fig. 6). ION is determined by the total car-
is less sensitive to the fin geometry. Therefore, the fin-
riers and average carrier velocity across the fin. Therefore,
induced IOFF is smaller than that in n-FET. The load-
it depends on the gate modulation, carriers’ drift transport,
ing effect in the SiGe selective area epitaxy can also
source/drain parasitic resistance (R S/D ), and gate-overdrive.
−1 −1 −1 cause a ±5% Ge composition variation, and a ±0.27 giga-
Gate modulation can be determined by C G = (COX + CSi ) ,
pascal (GPa) change in the channel stress. The resulting
where COX and CSi are the dielectric and quantum capacitance,
changes in mobility and quasi-ballistic velocity lead to a
respectively.
9% ION .
In a FinFET with a realistic tapered fin, ION flows through
the entire fin. The local ON-state current density ( JON ) is sim-
IV. 3-D SDE D OPING P ROFILE E NGINEERING FOR
ilar to that in a DG FET [26] with the same TSi . Although the
VARIABILITY S UPPRESSION AND P ERFORMANCE
top gate increases the local JON , the impact is relatively small
E NHANCEMENT
(<3% of ION ) compared to that induced by the fin geometry.
For TSi between 4 and 10 nm, reducing the TSi by 1 nm A. Variability suppression
leads to a 2%–3% increase in CSi [19]. However, the higher The localized leakage path in 3-nm node FinFETs indicates
gate electric field results in a ∼5% lower mobility [22], that the subthreshold performance’s variation, especially the

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1356 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 68, NO. 3, MARCH 2021

Fig. 11. Device performance in an n-FinFET with a V-shape SDE and

LR = 2 nm. (a) OFF-state barrier profile in the middle of the Wfin , and
(b) OFF-state and ON-state current density distribution.

Fig. 13. 3-D SDE doping profile optimization’s methodology and results.
(a) Schematics of the SDE doping profile modulation (not to scale),
(b) OFF-state and ON-state current distribution in an n-FinFET with the
optimized SDE profile, (c) RSDE -SS tradeoff in FinFETs with V-shape and
optimized SDE profile, and (d) ±1 nm LR-induced performance variation.

Fig. 12. Fin geometry (Wfin and θ covariation)-induced variability in 3-nm

node n- and p-FinFETs with various SDE profiles.

VTS (a significant contributor for both ION and IOFF ), can

be effectively reduced by improving the electrostatic control
around the leakage path. This can be achieved by the 3-D
SDE doping profile engineering. VTS is strongly affected
by Tleakage = Wfin + 2 × H × tan(θ ), where H is the
distance to the fin top. Compared to a vertically uniform SDE,
the V-shape profile [Fig. 2(b)] features reduced fin bottom
doping encroachment. Consequently, the coupling between the
drain fringing field and the fin bottom barrier is suppressed,
resulting in a higher local barrier (Fig. 11). The virtual cathode
is shifted toward the fin top, reducing H from 47 to 13 nm.
The ±1.5◦ θ -induced Tleakage is reduced from 2.5 to 0.7 nm,
suppressing the VTS . The top gate electric field also reduces
the virtual cathode’s sensitivity to the Tleakage , further suppress-
ing the fin geometry’s impact. The relatively small TSi and the
top gate improve the electrostatic control around the leakage Fig. 14. Device performances in n-/p-FinFETs with vertically uniform,
path. As a result, the virtual cathode and drain fringing field V-shape, and the optimized SDE doping profiles, respectively.
coupling is suppressed, reducing the SDE module-induced
variability. Compared to the vertically uniform SDE, the
V-shape SDE suppresses the fin module-induced ION in ION is observed (Fig. 14) in the 3-nm node. Therefore,
and IOFF by 1.6 × (1.3 ×) and 4.0 × (2.7 ×) in SDE design optimization is required to improve ION with
n-(p-)FET, respectively (Fig. 12). In addition, the ±1 nm a fixed IOFF = 10 nA/μm [high performance (HP) device
LR-induced ION variation is reduced by 1.8× (2.1×) in in International Technology Roadmap for Semiconductors
n-(p-)FET [Fig. 13(d)]. (ITRS)]. In the SDE doping profile engineering, the tradeoff
between electrostatic control and the RSDE has been identified
B. Optimization Methodology for Performance as the key to maximize ION /IOFF . In the V-shape SDE profile,
Enhancement the dopant encroachment near the subfin is over-suppressed,
Although the V-shape SDE profile can enhance the perfor- resulting in a relatively large RSDE and reduced ION (Fig. 14).
mance in the 7- and 10-nm node FinFETs [11], no increase Applied Materials’ SelectraTM lateral etch process [11] can be

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LU et al.: SDE DOPING ENGINEERING FOR VARIABILITY SUPPRESSION 1357

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