CMOS Analog Circuits

L15: Operational Amplifier-1

(14.10.2013)

B. Mazhari
B
Dept. of EE, IIT Kanpur
1G-Number
B. Mazhari, IITK
 VDD VDD

Vbias2 (W/L)6
M3 M4
M6
VO
vO
(W/L)7
Vi1 M1 M2 Vi2
vS Vbias1 M7
ISS
VSS
VBias M5

VSS

A differential amplifier does not The issue is how to we connect

have sufficient g
gain for many y these two stages together
applications. Its swing is also poor.
Thus an additional stage can be
beneficial. A CS stage with active
load is ideal.
2G-Number
B. Mazhari, IITK
 3.3V

M3 M4 3.3V
10/1 10/1

1.9V 2/1
2.21V V
O
M6 10
10A
A
10/1 10/1 ??? vO
M1 M2 2/1
-2.26V
2 26V
ISS=20A
-2.41V
M7
10/1
M5
-3 3V
-3.3V
-3.3V
3.3V

M3 M4
10/1 10/1
M6

2.21V

10A
10/1 10/1
M1 M2
M7
ISS=20A
20 A
-2.41V VBias
10/1
M5
3G-Number
B. Mazhari, IITK -3.3V
 3.3V

M3 M4
10/1 10/1
M6

2.21V 10/1
10A
10/1 10/1
M1 M2
M7
ISS=20A
-2.41V 5/1
10/1
M5 VBias

-3.3V

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B. Mazhari, IITK
Two-Stage Opamp: Biasing
VDD

M3 M4
(W/L)3 (W/L)4
M6

(W/L)6

(W/L)1 (W/L)2 kxISS

M1 M2
ISS M7

VBias (W/L)7
M5 (W/L)5

VSS

(W L)1  (W L) 2 (W L)3  (W L) 4

(W L)7  k  (W L)5 (W L)6  2k  (W L) 4

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B. Mazhari, IITK
Example

3.3V
3.3V

M3 M4
M3 M4
5/1
10/1 10/1 10/1 10/1 10/1
M6
M6

2 21V
2.21V
2.21V
A
10A
10/1 10/1
10/1 10/1
M1 M2
M1 M2
ISS=20A M7
ISS=20A M7
-2.41V
-2.41V 10/1
M5
10/1
5/1 M5 2.5/1
-3.3V
-3.3V

(W L)7  k  (W L)5

(W L)6  2k  (W L) 4

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B. Mazhari, IITK
Inverting and Non-inverting terminals

VDD

M3 M4
(W/L)3 (W/L)4
M6

(W/L)6

(W/L)1 (W/L)2 kxISS

v+ VO
vo V- V+
v- M1 M2
ISS M7

VBias (W/L)7
M5 (W/L)5

VSS

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B. Mazhari, IITK
Small Signal Analysis VDD

M3 M4
(W/L)3 (W/L)4
M6
VO1
((W/L))6

(W/L)1 (W/L)2 kxISS

V- V+ VO
M1 M2
ISS M7

VBias (W/L)7
M5 (W/L)5

VSS

vo vo1 vo
Adm     g m1  ro 2 ro 4  g m 6  ro 6 ro 7
vid vid vo1
vo vo1 vo g m1 g m 3
Acm      g m 6  ro 6 ro 7
vic vic vo1 1  2 g m1ro 5

CMRR  2 g m1  g m3  (ro 2 ro 4 )  ro 5
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B. Mazhari, IITK
 VDD

M3 M4
(W/L)3 ((W/L))4
M6
VO1
(W/L)6

(W/L)1 ((W/L))2 kxISS

V- V+
VO
M1 M2
ISS M7 ICMR   VDD  VSG 3  Vsat1  VGS 1
VBias (W/L)7
M5 (W/L)5

VSS ICMR   VSS  Vsat 5  VGS 1

Input common mode range
is same as that of
differential amplifier derived
earlier. Output swing is
close to supply rails within 4kT g kF KP
entotal  2 (1  m3 )  AF (1  P )
saturation voltage of PMOS 3g m1 g m1 f  Cox  W1  L KPN
and NMOS Transistors.
Input referred noise is also
determined p primarily
y byy the
input differential amplifier
stage
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B. Mazhari, IITK
Frequency Response

VDD

M3 M4
(W/L)3 (W/L)4
M6
1 VO1
(W/L)6

(W/L)1 (W/L)2 kxISS

V- V+
2
C2  Cgd 6  Cdb 6  Cgd 7  Cdb 7
VO
M1 M2
ISS M7
R2  r06 ro 7
VBias (W/L)7
M5 (W/L)5

VSS

C1  Cgd 2  Cdb 2  Cgd 4  Cdb 4  Cgs 6  Cgd 6 (1  AV 2 )

R1  ro 2 ro 4
3dB frequency will be determined by Node-1
10
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B. Mazhari, IITK
Example
3.3V

M3 M4
10/1 10/1
M6

1 10/1
C1  306.4 fF ; C2  10.3 fF
10A
V- 10/1 10/1
M2
V+
2 Ro1  Ro 2  1.3M 
M1
ISS=20A M7

-2.41V
10/1
5/1 f3dB  390kHz
M5
-3.3V

f3dB  290kHz

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B. Mazhari, IITK
Opamps are mostly used under negative feedback mode

R2

R1
VO
VS VO
VS

3.3V

M3 M4
10/1 10/1
M6

10/1

V- 10A
V+
10/1 10/1 VO
M1 M2
ISS=20A M7

-2.41V M7
10/1
M5
-3.3V

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B. Mazhari, IITK
 VO

VS

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B. Mazhari, IITK
 Amplifier is unstable
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 PM=-21o
Phase margin is negative
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 16
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B. Mazhari, IITK
How do we shift the dominant pole towards lower frequency?
3.3V

M3 M4
10/1 10/1
M6
C1  Cggd 2  Cdb 2  Cgd
g 4  Cdb 4 
1 10/1

10A Cgs 6  Cgd 6 (1  AV 2 )

V- 10/1 10/1 V+
M2
2
M1
ISS=20A M7
Ro1  ro 4 ro 2
-2.41V 5/1
10/1
M5
-3.3V 1
dominant pole: p1 ~
Ro1C1
Although an increase in RO through decrease in ISS can reduce p1, that would
increase the gain as well .

A better strategy is to increase C1 by adding an external capacitor

Since capacitors take up lot of area, we would like to use a small value of
capacitor. Use Miller’s effect to advantage 17 G-Number
B. Mazhari, IITK
 3.3V 3.3V

M3 M4 M3 M4
10/1 10/1 10/1 10/1
M6 M6

10/1 10/1
CC
10A 10A
V- 10/1 10/1 V+ V- 10/1 10/1 V+
0.2pF
M1 M2 M1 M2
ISS=20A M7 ISS=20A M7

-2.41V 5/1 -2.41V 5/1

10/1 10/1
M5 M5
-3.3V -3.3V

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B. Mazhari, IITK
 19
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B. Mazhari, IITK
In the previous example, improvement in phase margin was not obtained
because of presence of right half plane zero.

3.3V

M3 M4
10/1 10/1
M6

10/1
RZ 11k
CC 10A
V- 10/1 10/1 V+
0.2pF
M1 M2
ISS=20A
20A M7

-2.41V 5/1
10/1
M5
-3.3V

Inclusion of RZ cancels the right-half

right half plane zero and allows improved phase
margin
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B. Mazhari, IITK
Cc = 0.2pF

UGF=98MHz

PM=60o
-180

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B. Mazhari, IITK
 3.3V

M3 M4
10/1 10/1
M6

10/1
R 11k
CC 10A
V- 10/1 10/1 V+
0 2pF
0.2pF
M1 M2
ISS=20A M7

-2.41V 5/1
10/1
M5
-3.3V

By increasing or decreasing Compensation capacitor Cc, phase margin can be

increased or decreased.
decreased An increased phase margin comes at the expense
of reduced unity gain frequency though.

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B. Mazhari, IITK
 3.3V

M3 M4
10/1 10/1
M6
36o
10/1
R 11k
CC 10 A
10A
V- 10/1 10/1 V+
0.1pF
M1 M2
ISS=20A M7

-2.41V 5/1
10/1
M5
-3.3V

VO

VS

B. Mazhari, IITK There is overshoot and settling time 23

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 3.3V

M3 M4
10/1 10/1
M6

10/1
18o
R 11k
CC 
10A
V- 10/1 10/1 V+
0.05pF
M1 M2
ISS=20A M7

-2.41V 5/1
10/1
M5
-3.3V

VO

VS

Higher UGF but lesser phase margin leading to more overshoot and larger
settling time. 24 G-Number
B. Mazhari, IITK
2-pole system: Analysis
K
H (s)  s

1

1
1  4Q 2
s 1 s2 o
1  2 2Q 2Q
o Q o
o o
o o p1    1  4Q 2
p1    1  4Q 2 2Q 2Q
2Q 2Q

j j

Q<0.5
Q Q=0.5
Q

x x  x
x 

j

x Q>0.5
As Q increases further, the two
 poles move closer to vertical axis.
x
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B. Mazhari, IITK
 Q=0 1
Q=0.1 Q=0.5
Q 0.5

Q=2 Q=10

As Q increases, both overshoot and settling time increase

26
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B. Mazhari, IITK
2-pole amplifier

A(0) K
A( )  H (s) 
s s s 1 s2
(1  )  (1  ) 1  2
p1 p2 o Q o

p1  p2
o  p1  p2 ; Q 
p1  p2

Many amplifiers in open loop configuration have real poles in left half plane and
thus their Q < 0.5
0 5 and they have no overshoot or settling problem.
problem

p1  3.1  104 Hz ; p2  3.1  106 Hz

o  3.1
3 1  105 ; Q  0.1
01

27
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B. Mazhari, IITK
The same amplifier under closed loop with negative feedback can have Q >0.5
and thus overshoot and settling problems.

vo A
v Af  
vi  A vO vi 1  A
+
-
A( )
vfb
Af ( ) 

1  A( )  ( )

Loop Gain : T ( )  A( )  ( )

Amplifier becomes unstable if at some frequency the loop gain becomes -1.
Since β β≤1 for p
passive resistive feedback network,, the worst case condition for
stability occurs for β=1.

β 1 iis also
β= l called
ll d U
Unity
i gain
i ffeedback
db k
v
vi  A vO
+
- From the point of stability, the worst
case condition is unity gain feedback.
28
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2-pole amplifier under unity gain feedback
A(0) A( ) A(0)
A( )  ACL ( )  
(1 
s s
)  (1  ) 1  A( ) (1  s )  (1  s )  A(0)
p1 p2 p1 p2

A(0)
K
1  A(0) H (s) 
ACL ( )  s 1 s2
s 1 1 s2 1  2
1 (  ) o Q o
A(0) p1 p2 p1 p2 A(0)

p1  p2  A(0)
o  p1  p2  A(0) ; Q 
p1  p2

p1  3.1
3 1  104 H
Hz ; p2  33.11  106 H
Hz; A(0)  103

o  107 ; Q  3.1
Often we discuss stability in amplifiers in terms of phase margins 29
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B. Mazhari, IITK
2-pole amplifier: phase margin

AOL (0)
AOL ( )  ; p2  p1
j j
(1  )  (1  )
p1 p2

p1

G i
Gain p2
UGF

phase

PM
-180

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Unity gain Frequency (UGF)

AOL (0)
AOL ( ) 
j j
(1  )  (1  )
p1 p2
AOL ((0)) p1

j
j  (1  )
p2

AOL (0) p1
At UGF, gain = 1  AOL ( )  1
UGF 2
UGF  1  ( )
p2
UGF  AOL (0)  p1
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Phase Margin (PM)

AOL (0)
AOL ( ) 
j j
(1  )  (1  )
p1 p2
AOL (0) p1

j
j  (1  )
p2

UGF  AOL ((0))  p1

 UGF
1
Phase at UGF: A ol    tan ( )
2 p2

 UGF
Phase Margin: A ol    PM   tan ( 1
)
2 p2

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2-pole amplifier
 UGF 1
PM   tan ( )
2 p2
UGF  AOL (0)  p1  AOL (0)
1
  tan ( )
2 p2 p1

PM P2/p1
45o AOL (0)
60o 1.7AOL (0)
75o 3.7AOL (0)

When we make amplifiers,

amplifiers often the two poles are close together and we do not
get enough phase margin. Different techniques of compensation are used to
push the poles apart. P1 is reduced resulting in decrease in UGF.

33
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B. Mazhari, IITK
As discussed earlier, phase margin and Q are related together

Q % overshoot PM

0 527
0.527 0 008
0.008 75o

0.622 1.4 70o

0.817 8.7 65o

0.925 13.3 55o

34
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B. Mazhari, IITK
In the operational amplifier shown below, the two poles are not sufficiently far apart and
there is an additional zero in RHP (right half plane) due to which phase margin is
negative.
g A compensation
p capacitor
p is used to p
push p
poles apart.
p
3.3V

M3 M4
10/1 10/1 C1  Cgd 2  Cdb 2  Cgd 4  Cdb 4  Cgs 6
vo1 M6

Ro1  ro 2 ro 4
10/1
CC
10A
V- 10/1 10/1 V+
M1 M2 C2  Cgd 6  Cdb 6  Cgd 7  Cdb 7
ISS=20A
20A M7

-2.41V 5/1
M5
10/1
R2  r06 ro 7
-3.3V

CC

Cgd6
+ + +
gm1vin
vin C1 vo1 C2 vo
Ro1 Ro2
gm6vo1
- - -
35
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B. Mazhari, IITK
 CC

Cgd6
+ + +
gm1vin
vin C1 vo1 C2 vo
Ro1 Ro2
gm6vo1
- - -

s
AOL (0)  (1  ) 1 gm 6 gm6
AOL ( s )  z p  ; p  ; z 
R01 (CC  Cgd 6 )  (1  AV 2o ) CC  Cgd 6
1 2
s s C2
((1  )  ((1  )
p1 p2

AV 2 (0)  g m 6 Ro 2 ; AOL (0)  g m1Ro1 g m 6 Ro 2 UGF  AOL (0)  p1

g m1
UGF 
2 CC

 UGF UGF
Phase Margin: A ol    PM   tan 1 ( )  tan 1 ( )
2 p2 z
Does Miller’s theorem give proper results here ! 36
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B. Mazhari, IITK
 3.3V
CC
M3 M4
10/1 10/1
M6 Cgd6
10/1 + + +
CC gm1vin
10A vin C1 vo1 C2 vo
V- 10/1 10/1 V+ Ro1 Ro2
M2 gm6vo1
M1 - - -
ISS=20A M7

2 41V
-2.41V 5/1
10/1
M5
-3.3V

g m1  136  A / V ; Ro1  1.3M  ; g m 6  86  A / V ; Ro 2  1.3M  ; C2  10.3 fF

 UGF UGF
PM   tan 1 ( )  tan 1 ( )
2 p2 z

CC P1 P2 Z UGF tan-1 tan-1 PM

(pF) (kHz) (GHz) (MHz) (MHz)
(UGF/P2) (UGF/z)
0 469 13
1.3 5720 9065 81 6
81.6 57 7
57.7 -49
49o
0.1 11 1.3 134 212 9 57.7 23o
05
0.5 22
2.2 13
1.3 27 43 1 86
1.86 57 7
57.7 30o
2 0.56 1.3 6.8 11 0.47 57.7 32o

Even though p1 moves to lower frequency, PM does not improve much because of RHP
zero.
B. Mazhari, IITK
37 G-Number
 CC RZ

Cgd6
+ + +
gm1vin
vin C1 vo1 C2 vo
Ro1 Ro2
gm6vo1
- - -

1 gm6 1
p1  ; p2  ;z
Ro1CC  (1  AV 2 o ) C2 CC  (
1
 RZ )
gm6
Derivation in appendix

Poles remain the same but position of zero can be adjusted and even
eliminated.
1
Choose RZ 
gm6
 UGF
PM   tan 1 ( )
2 p2
38
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B. Mazhari, IITK