Experiment # 1

Introduction to Digital Logic Design

EQUIPMENT TO BE USED IN THE LAB

Before performing Lab activities in the Lab, it is necessary that student should have a
thorough understanding of the equipment that is to be used in the lab.

The details of such equipment are mentioned as under:

1. Bread Board
Breadboard (or protoBoard) is a construction base for prototyping of electronics. A Building
or prototyping circuit on a breadboard is also known as 'bread boarding’. In Breadboards we
have two sets of connected lines known as rows and columns as shown below:

Once inserted in a row, a component will be electrically connected to anything else placed in
that row. The same holds true for columns. But rows and columns are not connected with
each other unless connected externally.

Handling Precautions:
i. Always keep your work neat.
ii. Keep your component leads short.
iii. Avoid both overcrowding and excessive spacing.
iv. Never force components into the breadboard socket contacts.
v. Never bend a component lead at the body of the component.
vi. Leave at least ¼" of lead length available to plug into the breadboard socket itself.

1|Page
 2. Logic Probe
A logic probe is a hand-held pen-like test probe used for analyzing and troubleshooting the
logical states (Boolean 0 or 1) of a digital circuit. While most are powered by the circuit
under test, some devices use batteries. They can be used on either TTL (transistor-transistor
logic) or CMOS (complementary metal-oxide semiconductor) integrated circuit devices.
Following figure shows a logic probe:

Figure: 0.1
There are usually three differently-colored LEDs on the probe's body:

 Red and green LEDs indicate high and low states respectively.
 An amber LED indicates a pulse (as used in a NOID Light to test for pulses to fuel
injectors on an electronically controlled fuel injection vehicle)

Handling Precautions:
i. Be careful when working close to any kind of high voltage or current.
ii. If high voltage or current is exposed in your circuit, cover that portion up so you don’t
actually touch it with your fingers or the logic probe.
iii. To use the logic probe you really have to know what points in the circuit to test. This
means you need to have a schematic or other wiring diagram, so you know what goes
to where.

3. Power Supply
Power supplies are amongst the most popular pieces of electronic test equipment. There are a
variety of different types of power supplies used in Electronics Labs. The Power Supplies
we’re going to use are called multiple output power supplies. Multiple output power supplies
have more than one DC output, often two or three. These are useful and cost-effective for
systems that require multiple voltages. An often-used power supply for circuit development is
a triple output supply. One output supplies 0 to 5 volts, intended for digital logic. The other
two supply (typically) 0 to 25 or 0 to 30 volts, which can be used with bipolar analog
circuitry. Sometimes a tracking adjustment is supplied for the two 25 volt supplies so that the
+ and - 25 volt supplies can be adjusted together by turning one knob.

2|Page
 Figure: 0.2

Handling Precautions:
i. Electrical Power, floor and wall outlets are at 220 Volts AC. If you come in contact
with 220 Volts AC it could be fatal; take appropriate safety precautions.
ii. Double-check your wiring and circuit connections. It is a good idea to use a point-to-
point wiring diagram to review when making these checks.
iii. Avoid shorting the Power Supply as it may lead to serious Electric and Life hazards.
iv. Switch off the circuit while modifying the circuit.
v. Double check the circuit before switching on the supply

4. Logic Gate ICs:

In electronics, a logic gate is an idealized or physical device implementing a Boolean
function; that is, it performs a logical operation on one or more logical inputs, and produces a
single logical output. Logic gates are primarily implemented using diodes or transistors
acting as electronic switches, but can also be constructed using electromagnetic relays (relay
logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements.
For small-scale logic, designers now use prefabricated logic gates from families of devices
such as the TTL 7400 series by Texas Instruments, the CMOS 4000 series by RCA, and their
more recent descendants. Increasingly, these fixed-function logic gates are being replaced by
programmable logic devices, which allow designers to pack a large number of mixed logic
gates into a single integrated circuit.

Figure: 0.3

3|Page
 Figure: 0.4
Handling Precautions:

i. Prevent Over-Voltage and Over-Current Conditions

ii. Unconnected input pins with very high impedance levels can adversely affect stability
of operation. Such pins should be connected through an appropriate resistance to a
power supply pin or ground pin.
iii. IC pins are numbered anti-clockwise around the IC starting in the bottom left-hand
corner, near the notch or dot. This is shown below:

Figure: 0.5

5. Digital and Analog Training System (ETS-7000A):

It combines all essential function of analog experiment and digital experiment. It is

equipped with removable breadboard, DC power supply, function generator, two digits of
7-segment LED display, eight bits LED display, two pulse switches, 2.25 inch 8 ohm
0.25w speaker
It has a unique design universal connector, which reserves fixed holder on the panel in
order to be connected with various connectors for the convenience of developing interface
circuitry.

4|Page
 Figure: 0.6
Features:

1) Power Switch
2) Variable Positive and Negative Power Supply
3) Potentiometers
4) Universal Counter
5) Frequency Variable
6) Waveform amplitude variable
7) Frequency Range
8) Waveform Selector
9) 8-bit data switches
10) Removable Breadboard
11) Two pulse Switches
12) Adaptor
13) Digital Display
14) 8-bit LED display
15) Universal Connector fixed holders

Specifications:

1) DC Power Supply:
 Fixed DC output: +5V ± 10%, 1Amp.
 Fixed DC output: -5V ± 10%, 300 m Amp.
 Variable DC output: 0V to +15V ± 10%, 500 m Amp.
 Variable DC output: 0V to -15V ± 10%, 500 m Amp.

5|Page
2) Potentiometers:

 Variable resistor VR1= 1 KΩ

 Variable resistor VR2= 100 KΩ

3) Function Generators:
 Frequency Ranges:
o 0.1 Hz to 2 Hz
o 1 Hz to 20 Hz
o 10 Hz to 200 Hz
o 100 Hz to 2 KHz
o 1KHz to 20KHz
o 10 KHz to 200 KHz

 Amplitude Ranges:
o Sine wave output: 0-5 Vpp ±10% variable
o Triangle wave output: 0-5 Vpp ±10% variable
o Square wave output: 0-15 Vpp ±10% variable
o TTL mode output: 5 Vp ± 10%

4) Universal Counter:
a) Frequency Range: 1Hz – 99.999999 MHz ; 10Hz – 100.00 MHz
b) Period Range TH & TL : 0.01 μS. - 999999.99 μS. ; 1 μS.- 99999999 μS.
c) Input Signal: TTL or CMOS level or any level (VMIN ≥ + 2.3Vp ± 10%)
d) Display: 8-digit 7-Segment LED display
e) Counter switch external / Internal

5) Eight bit data switches:

Eight toggle switches and corresponding output point. When switch is set at
“DOWN” the output is low level; on the contrary, it is to be high level while setting at
“UP”.

6) Two pulse switches (with 2 sets of output: Ā,A, B́,B):

Two push buttons contain switches de-bouncer for eliminating the bounce
caused by switch from “OPEN” to “CLOSE” or from “CLOSE” to “OPEN” position.

7) Speaker:
2.25 inch diameter, 8 Ω/ 0.25 Watt, to be used for load.

8) Four channel adaptor:

The point tips of both of the two banana sockets and two BNC jacks are
changeable. It is suitable for ETS-7000Ato be connected with peripherals.

9) 8-bits LED display:

Eight red LEDs with separate input. The LED will light up when input is at
“Hi Level”, and it will be turned off when there is no input or at “ low Level”.

10) Universal connector fixed holder:

There is universal connector fixed holder on the panel in order to be connected

6|Page
 with various universal connector.

11) Two digits of 7-segment LED display:

 Output display:

o Segment identification

o Numerical designs and resultant displays

 Function Table:

Here ‘1’ is for logic ‘HIGH’ and ‘0’ is for logic ‘LOW’

7|Page
 1 = HIGH = H and 0 = LOW = L

Handling Precautions:

i. Electrical Power, floor and wall outlets are at 220 Volts AC. If you come in contact
with 220 Volts AC it could be fatal; take appropriate safety precautions.
ii. Double-check your wiring and circuit connections. It is a good idea to use a point-to-
point wiring diagram to review when making these checks.
iii. Avoid shorting the Power Supply as it may lead to serious Electric and Life hazards.
iv. Switch off the circuit while modifying the circuit.
v. Double check the circuit before switching on the supply
vi. Gently use data switches, pulse switches, function generator’s knobs, power supply
knobs, potentiometer knobs and other movable parts because they are sensitive.

SAFETY PRECAUTIONS

Following proper safety practices are must when working with electronic equipment. Not
only is there the danger of electrical shock, but the components can explode if not connected
properly. Many of today’s electronic components are easily damaged by improper handling.
The test equipment used in the electronic service industry is expensive and easily damaged if
proper operating procedures are not followed.

1. While implementing circuits on hardware, test points should be introduced and Logic
should be checked after every step/connection to avoid errors in the circuit.

2. Never make any changes to circuits without first isolating the circuit by switching off
and/or removing connections to supplies.

3. Equipment/Circuits must not be left unattended.

4. Equipment found to be faulty should be reported immediately to Instructor or Lab

Staff.

5. It should be noted that unconnected TTL gate terminals are by default on High logic
Level which may affect the output logic of the circuit.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the working of laboratory equipment, instruments and how to utilize them
in digital logic design experiments.

LO2: To understand the handling precautions and how to take safety measures while
performing laboratory experiments.

8|Page
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 02
9|Page
OBJECTIVE:
To understand the operation of various 2-Input and 3-Input logic gates and verify their
truth table

BACKGROUND THEORY:

In general, logic circuits have one or more inputs and only one output. The circuits
respond to various input combinations, and a truth table shows this relationship between
circuits input combinations and its output. The truth table for a particular circuit explains how
the circuit behaves under normal conditions. Familiarization with a logic circuit’s truth table
is essential to the technologist or technician before he or she can design with or troubleshoot
the circuit.

2-Input Logic Gates:

In this experiment, logic circuits with 2-inputs are:

Gate Symbol Truth Table Boolean IC Schematic

Expression
7408

A B Y
L L L
AND L H L
H L L
H H H

7432

10 | P a g e
 A B Y
L L L
OR L H H
H L H
H H H

7404

A Y
L H
NOT
H L

11 | P a g e
 7400

A B Y
L L H
NAND L H H
H L H
H H L

7402

A B Y
L L H
NOR L H L
H L L
H H L

12 | P a g e
 74LS86

A B Y
L L L
XOR L H H
H L H
H H L

74266

A B Y
L L H
XNOR L H L
H L L
H H H

13 | P a g e
3-Input Logic Gates:
In this experiment, logic circuits with 3-inputs are:

Gate Symbol Truth Table Boolean IC Schematic

Expression
7410

A B C Y
L L L H
L L H H
L H L H
NAND L H H H
H L L H
H L H H
H H L H
H H H L

7427

A B C Y
L L L H
L L H L
L H L L
L H H L
NOR H L L L
H L H L
H H L L
H H H L

HARDWARE REQUIRED:
 Power supply with cables
 Breadboard
 Logic gate ICs: 1) 7432, 2) 7408, 3) 7400, 4) 7402, 5) 7404, 6) 7410, 7) 7427
 LEDs
 Logic Probe (optional)

14 | P a g e
PROCEDURE:

1. Start with 7432 and carefully place it on to the breadboard as shown below:

2. After placing the IC, make Vcc and GND connections taking care not to reverse the
polarity.
3. Apply logic signals to inputs of the gate and observe the output using an LED
connected at the output. (Or by using Logic Probe if available).
4. Note the values in the tables provided and compare the findings with respective
predefined Logic Tables.
5. Now repeat the steps 2-4 with all the ICs provided

OBSERVATIONS:

7408 (AND)
7432 (OR)
Input Input B Output Y
Input Input B Output Y
A
A
L L L
L L L
L H L
L H H
H L L
H L H
H H H
H H H
7400 (NAND)
7402 (NOR)
Input Input B Output Y
Input Input B Output Y
A
A
L L H
L L H
L H H
L H L
H L H
H L L
H H L
H H L

15 | P a g e
 7404 (NOT)
Input Output Y
A
L H
H L

7410 (NAND) 7427 (NOR)

Input Input Input C Output Input Input B Input Output Y
A B Y A C
L L L H L L L H
L L H H L L H L
L H L H L H L L
L H H H L H H L
H L L H H L L L
H L H H H L H L
H H L H H H L L
H H H L H H H L

7486 (XOR) 74266 (XNOR)

Input Input B Output Y Input Input B Output Y
A A
L L L L L H
L H H L H L
H L H H L L
H H L H H H

16 | P a g e
Home Activity:
Using Multisim, implement the given logic circuits by using appropriate ICs and
determine the truth table of each circuitry.
Put your name and roll number on design suite and attach the screen shot of your
design suite at the end of experiment#2.

a)

b)

17 | P a g e
 REVIEW QUESTIONS:

Q.1) If you have asked to implement Y = AB + C, mention all the required IC number.

FOR AB 7408IC IS REQUIRED AND FOR AB+C 7432IC IS REQUIRED

Q.2) Complete the following timing wave forms.

Q.3) What have you learnt from this experiment?

I have learnt different ics usage,their different outputs, how they work differently from

each other.and after combinig different ics and comparing them with the variation of
high and low voltage.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the working of Logic gate’s ICs and how to utilize them in circuits.

LO2: To experimentally verify the behavior of Logic gates against their established truth
Tables.

18 | P a g e
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

19 | P a g e
 Experiment # 03
Introduction to Multisim
National Instruments Circuit Design Suite is a suite of EDA (Electronics Design
Automation) tools that assists you in carrying out the major steps in the circuit design flow.
Multisim is the schematic capture and simulation program designed for schematic entry,
simulation, and feeding to downstage steps, such as PCB layout. It also includes mixed
analog/digital simulation capability, and microcontroller co-simulation. This manual
describes some of the basic features of Multisim.

Note: for a description of the features available in your edition. Refer to the Multisim Help
for complete information about your Multisim edition accordingly.

User Interface
This section introduces you to Multisim’s user interface.
.

20 | P a g e
 1. Menu Bar 2. Design Toolbox 3. Component Toolbar
4. Standard Toolbar 5. View Toolbar 6. Simulation Toolbar
7. Main Toolbar 8. In Use List 9. Instruments Toolbar
10. Scroll Left/Right 11. Circuit Window 12. Spreadsheet View
13. Active Tab

Toolbars
Multisim includes the following toolbars:

• Standard Toolbar: Contains buttons for commonly-performed Windows functions.

• Main Toolbar: Contains buttons for commonly-performed Multisim functions.

• Simulation Toolbar: Contains buttons used during simulation.

• View Toolbar: Contains buttons used to manipulate the appearance of the workspace.

• Components Toolbar: Contains buttons used to place components onto the workspace.

• Virtual Toolbar: Contains buttons used to place virtual components on the workspace.

• Graphic Annotation Toolbar: Contains buttons used to draw graphic elements such as
lines and circles on the workspace. You can also place comments and pictures from here.

• Instruments Toolbar: Contains buttons used to place instruments on the workspace.

Setting Schematic Capture Preferences

You can customize virtually any aspect of Multisim preferences, including the colors
used in your circuit, page size, zoom level, auto-backup interval, symbol set (ANSI or DIN)
and printer setup. Your customization settings are saved individually with each circuit file
you use so you could, for example, have one color scheme for one circuit and another for a
different circuit.

Customization is done through the:

• Global Preferences dialog box—Use to set up global preferences. These preferences can
vary from computer to computer.

• Sheet Properties dialog box—Use to set up the preferences for the active sheet. These
preferences are saved with the circuit files so that if the circuit is opened on another
computer, it will use the same settings.

Complete the following steps to start placing components:

1. Open MyGettingStarted as described above.

2. Select Place»Component to display the Select a Component dialog box, navigate to the
7-segment LED display as shown below and click OK. The component appears as a
“ghost” on the cursor.

21 | P a g e
 Tip: Once you have selected the desired Group and Family, start typing the
component’s name in the browser’s Component field. As you type, the string appears
in the Searching field at the bottom of the browser. In the example below, type
seven_seg_decimal_com_a_blue. Matches are displayed as you type.

3. Move the cursor to the bottom-right of the workspace and left-click to place the
component. Note that the Reference Designator for this component is “U1”.

4. Place the remaining components in the Digital Counter area as shown below.

22 | P a g e
 Note: When placing resistors, inductors, or capacitors (RLC components), the Select a
Component dialog box has slightly different fields than for other components. When placing
these components, you can choose any combination of: the component’s value (for example,
the resistance value); type (for example, carbon film); tolerance; footprint and manufacturer.
If you are placing a component that will be ultimately exported to PCB layout, and become
part of a Bill of Materials, you must be careful that the combination of values that you select
in the Select a Component dialog box are available in a real-world, purchasable component.

Tip When placing RLC components, type the value of the device that you want to
Place in the field at the top of the Component list. The value does not need to appear
in the list to be placed on the schematic.

Tip While placing the 200 Ω resistor, rotate it to a vertical orientation by pressing
<Ctrl-R> on your keyboard.

Tip Reference Designators (for example, U1, U2) are assigned in the order the
Components are placed. If you place components in a different order than in the
original design, the numbering will differ. This will not affect the operation of the
design in any way.

5. Place the components in the Counter Control section. After placement, right-click on each
of the SPDT switches and select Flip Horizontal.

23 | P a g e
 Tip The SPDT switches are in the Basic group, Switch family.

Tip When a component is on the workspace and you want to place the same
Component again, highlight it and select Edit»Copy, then Edit»Paste. You can also
select it from the In Use List and click to place it on the workspace.

Digital Logic Fundamentals

Typically when students are learning digital logic fundamentals they are limited to
theoretical understanding. Multisim allow student to put this theory into practice through
schematic simulation and deployment to hardware. Multisim enables you to program your
Digilent teaching boards directly from the Multisim environment, making the connection
between theoretical concepts and hardware implementation more understandable.

This tutorial demonstrates the process a student can go through to learn Boolean logic
and illustrates how through using Multisim, students can apply this theory to hardware to see
the physical response.

1. Digital Logic Theory

When learning digital logic students will start with the three fundamental building
blocks: AND, OR and NOT gates.
 
AND
Boolean Expression: AB

24 | P a g e
 OR
Boolean Expression: A+B

 
NOT
Boolean Expression: Á

Multisim allows students to interactively learn the action of these fundamental logic gates
that make up the building blocks of all digital systems.

  2. Simulation of Digital Logic

In this tutorial we will learn the action of AND gates through simulation. Multisim
provides interactive components and virtual instruments to help students understanding.

1. Open a new blank schematic in Multisim.

2. Place down a two input AND gate from the component database. Right click and
select Place Component. Choose the following parameters:

  Database: Master Database
Group: Misc Digital
    Family: TIL
   Component: AND2

3. Place the component on the schematic.

25 | P a g e
4. In order to evaluate the behavior of the component we will use a virtual switch and
LED. Place the following components on the schematic.

26 | P a g e
5. Arrange the components on the schematic as below:

6. Wire the components together to create the digital logic circuit

7. Once we have completed our schematic we can evaluate the operation of the AND
gate. The two switches and the LED are interactive components. Click Run on the
tool bar shown below.

8. During execution toggle the switches and view the effect on the LED. The AND gate

27 | P a g e
 should respond according to the truth table below. When both switches are closed
(high) the LED turns on. This allows the student to experiment with the switches to
understand the AND gate operation.

 
9. Multisim also includes interactive instruments which we can connect to our schematic
as we would benchtop instruments. In understanding digital logic the Logic
Converter is a powerful tool. The Logic converter allows us to obtain a truth table
and Boolean expression for our circuit. Place a Logic Converter onto the schematic.

 
10. Connect the Logic Converter to the schematic as shown below. The Logic Converter
allows multiple inputs with and a single output.

28 | P a g e
 
 
11. Double click the Logic Converter to open its user interface.

12. Click on the top conversion button as shown below. This is will analyze the schematic
and create a truth table for the response.

13. Click on the next conversion button. This analyses the truth table and generates the
Boolean expression. For an AND gate the Boolean expression should be AB. The
logic converter also allows students to input truth tables and Boolean expressions and
generate logic diagrams.

29 | P a g e
 
14. This process can be modified to allow students to gain a comprehensive knowledge of
different logic gates.

 Home Activity:

Repeat all the tasks of Lab#02 by implementing on Multisim. Put your name
and roll number on design suite and attach the screen shot of your design suite
at the end of experiment#3

30 | P a g e
31 | P a g e
REVIEW QUESTIONS:

Q.1) List at least two advantages of design suite.

FIRSTLY, NO BRADBOARD, IC OR WIRES IS REQUIRED

WE CAN PERFORM TASK EASILY AND QUICKLY WITHOUT PURCHASING

ANY COMPONENT. IT IS VERY BENEFITIAL FOR THE STUDENTS.

Q.2) What have you learnt from this experiment?

I have learnt the multisim usage connect different ics, gates and how they work

differently in different circuits and they show different outputs form each other.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Design schematic and visualize it’s behavior.

LO2: Analyze the response of designed circuit.

32 | P a g e
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

33 | P a g e
 Experiment # 04
OBJECTIVE:
To design and implement a logic gate circuit for the given Boolean expression

BACKGROUND THEORY:
In computer science, a Boolean expression is an expression in a programming language that
produces a Boolean value when evaluated, i.e. one of true or false. A Boolean expression
may be composed of a combination of the Boolean constants true or false, Boolean-typed
variables, Boolean-valued operators, and Boolean-valued functions. Boolean expressions
correspond to propositional formulas in logic and are a special case of Boolean circuits.

Most programming languages have the Boolean operators OR, AND and NOT; in C and
some newer languages, these are represented by "||" (double pipe character), "&&" (double
ampersand) and "!" (Exclamation point) respectively, while the corresponding bitwise
operations are represented by "|", "&" and "~" (tilde). In theoretical literature the symbols
used are often "+" (plus), "·" (dot) and over bar, or "∨" (cup), " ∧" (cap) and "¬" or "_"
(prime).

In Boolean expressions, we observe the regular order of operations: Multiplication (AND)

comes before addition (OR). Thus, when we write , we mean .We can use
parentheses when this order of operations isn't what we want. For NOT, the bar over the
expression indicates the extent of the expression to which it applies; thus,
represents NOT x OR y), while represents (NOT A) OR (NOT B).
A warning: Students new to Boolean expressions frequently try to abbreviate as ,
that is, they draw a single line over the whole expression, rather than two separate lines over
the two individual pieces. This abbreviation is wrong.

EXAMPLE PROBLEM

Every expression directly corresponds to a circuit and vice versa. To determine the
expression corresponding to a logic circuit, we feed expressions through the circuit just as
values propagate through it. Suppose we do this for our below circuit

Figure: 3.1

34 | P a g e
LAB TASK

Design a logic gate circuit for the Boolean expression given below:

Y = Á BC + A B́ C + AB Ć
A B C Y

L L L L

L L H L

L H L L

L H H H

H L L L

H L H H

H H L H

H H H L

HARDWARE REQUIRED:
 Power supply with cables
 Breadboard
 Logic gate ICs: (1) AND Gate (2) OR Gate (3) NOT Gate
 LEDs
 Logic Probe (optional)

PROCEDURE:

1. Build the circuit on the bread board or electronic workbench software.

2. Check the Output (Y) of the circuit after applying Inputs (A, B, C)
3. Compute the truth tables.

35 | P a g e
Home Activity:

By using Multisim, construct a logic gate circuit of given Boolean expression and also
determine the truth table of this expression:

Y= ( Á B) + ABĆ
Put your name and roll number on design suite and attach the screen shot of your
design suite at the end of experiment#4

REVIEW QUESTIONS:

Q.1) Does the theoretical calculations confirmed by Experimental findings? If yes, what is the
advantage in designing the circuits on paper rather than going straight to Hardware implementation
without calculation?

Yes we can confirm the theoretical calculation but the advantage of the circuit designing is it reduce

The chances of error

Q.2) Write the Boolean expression for each of the logic circuits

a)_____AB+C______________ b)_____(A’B)’_______________

36 | P a g e
c)______(A+B)C______________

Q.3) What have you learnt from this experiment?

I have learnt how to made circuit with different logic gates and make the boolean expression

Accurate and gives the truth table of the boolean expression.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand fairly complex Boolean expressions.

LO2: Design a Logic Circuit for a given Boolean expression

Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

37 | P a g e
 Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 05

OBJECTIVE:

To simplify complex logic circuits using De Morgan’s theorem and Boolean algebra
identities

BACKGROUND THEORY:

Following are some Boolean identities and laws which will be very useful during
simplification of Logic expressions:

Additive Multiplicative Boolean Laws

0+A=A 0A=0
1+A=1 1A=A Basic Identity

A+A=A A.A=A Identity Law

Á+ A=1 Á . A=0 Inverse Law
Á=A Double Inverse Law
A+B=B+A A.B=B.A Commutative Law
(A + B) + C = A + (B + C) (A B) C = A (B C) Associative Law

38 | P a g e
A (B + C) = A B + A C A + (B C) = (A + B) (A + C) Distributive Law

De Morgan’s Laws

De Morgan proposed two laws that are an important part of Boolean algebra. The two
De Morgan's laws are stated as follows:

Law # 1: The complement of a product of two variables is equal to the sum of complements
of the individual variables

Law # 2: The complement of a sum of two variables is equal to the product of complements
of the individual variables.

EXAMPLE CONVERSION OF COMPLEX LOGIC FUNCTION TO SIMPLE LOGIC

FUNCTION

To illustrate, let's take the following expression and reduce it using De Morgan's Theorems:

Correct Method Incorrect Method

39 | P a g e
Following the advice of breaking the longest Following is the incorrect method for applying
(uppermost) bar first, we should begin by De Morgan’s Theorem:
breaking the bar covering the entire expression
as a first step:

LAB TASK:
Simplify the following Boolean expression using De Morgan’s theorem and Boolean
identities:
Y = A . B+´ A . C+ Á B́ C
Draw the logic gate circuit of Original Boolean Expression in the given space and implement
the circuit to complete the truth table of original Boolean Expression.

40 | P a g e
41 | P a g e
 A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
Space for Simplification

Y = A . B+´ A . C+ Á B́ C
steY = A . B+´ A . C+ Á B́ C

Simplified Expression A’+B’C’

Draw the logic gate circuit of simplified Boolean Expression in the given space and
implement the circuit to complete the truth table of Simplified Boolean Expression.

42 | P a g e
 A B C Y
L L L 1
L L H 1
L H L 1
L H H 1
H L L 1
H L H 0
H H L 0
H H H 0

HARDWARE REQUIRED:
 Power supply with cables
 Breadboard
 Logic gate ICs: 1) AND Gate 2) OR Gate 3) NOT Gate
 LEDs
 Logic Probe (optional)
PROCEDURE:

1. First of all, implement the logic circuit of the original expression for task 1 and build
the truth table.
2. Simplify the expression of task 1 using Boolean identities and De Morgan laws.
3. Now implement the logic circuit of the simplified expression and built its truth table.
4. Compare the two truth tables for task 1

43 | P a g e
 5. Repeat the same procedure for task 2.

Home Activity:

Simplify the following Boolean expression by using De Morgan’s theorem and

Boolean identities, construct both original and simplified logic gate circuits on Multisim
and also verify by means of truth table:

´
Y= A+ B( A+C´ ¿)+ AC ¿
Put your name and roll number on design suite and attach the screen shot of your circuit
design suite at the end of experiment#5 (also attach necessary working on a separate sheet)

REVIEW QUESTIONS:

Q.1) Determine which of the logic circuits are equivalent.

44 | P a g e
B and d have same output

Q.2) List at least two advantages of simplifying Boolean expressions:

1: it will contain the reduced number of logic gates than the unsimplified original circuit

2: it will also reduce the cost of hardware.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand and validate De Morgan’s Theorem.

LO2: Observe the advantages of simplifying a complex Boolean expression in Logic circuits

Lab’s Evaluation Sheet

45 | P a g e
 Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 06
OBJECTIVE:

To understand and use the Karnaugh maps in designing Logic circuits using Truth
tables.

BACKGROUND THEORY:

The Karnaugh map, also known as the K-map, is a method to simplify Boolean
algebra expressions. Maurice Karnaugh introduced it in 1953 as a refinement of Edward
Veitch's 1952 Veitch diagram. The Karnaugh map reduces the need for extensive calculations
by taking advantage of humans' pattern-recognition capability. It also permits the rapid
identification and elimination of potential race conditions. The required Boolean results are

46 | P a g e
transferred from a truth table onto a two-dimensional grid where the cells are ordered in Gray
code, and each cell position represents one combination of input conditions, while each cell
value represents the corresponding output value. Optimal groups of 1s or 0s are identified,
which represent the terms of a canonical form of the logic in the original truth table. These
terms can be used to write a minimal Boolean expression representing the required logic.
Some important terms related to K-maps are as follows:

Sum of Products (SOP): A Sum of Products (SOP) expression contains: – Only AND
(product) operations at the “outermost” level – Each term must be a sum of literals.

Example SOP expression: Y = A.B + B.C + A.C

Product of Sum (POS): A Product of Sums (POS) expression contains: – Only OR (sum)
operations at the “outermost” level – Each term that is summed must be a product of literals.

Example POS expression: Y = (A+B+C) . (A+B) .(A+C)

Minterm: A min term is a special product of literals, in which each input variable appears
exactly once. A function with ‘n’ variables has 2 n minterms (since each variable can appear
complemented or not). If you have a truth table for a function, you can write a sum of
minterms expression just by picking out the rows of the table where the function output is ‘1’.

Maxterm: A maxterm is a sum of literals, in which each input variable appears exactly once.
A function with ‘n’ variables has 2 n maxterms. If you have a truth table for a function, you
can write a product of maxterms expression by picking out the rows of the table where the
function output is ‘0’.

2-Input K-Map
In the truth table of a 2-Input Logic system:

3-Input K-Map
In the truth table of a 3-Input Logic system:

47 | P a g e
4-Input K-Map
In the truth table of a 4-Input Logic system:

48 | P a g e
 AN EXAMPLE SYSTEM SIMPLIFICATION USING K-MAP

The easiest way to simplify an expression with a Karnaugh map is to follow these steps:
a) Build the expression's truth table.
b) Starting with a blank Karnaugh map, take each row of the truth table where the output is 1
and mark the corresponding minterm in the map with a 1.
c) Form rectangular blocks of neighboring cells where each cell contains a 1. The size of
these blocks must be a power of two, e.g. one, two, four, eight, etc. Large blocks will give
simpler final equations, so try to make the blocks as large as possible.
d) Find the equation for each block. Each block will have variables which remain constant
and the block's equation is the ANDing of these variables. Now build an OR function with
the block equations as arguments. You have created the sum or products simplified
expression.

Example:

The given Boolean algebraic expression is

m = á bc + ab́ c + abć + abc

First build the truth table as below:

To use a Karnaugh map we draw the following map which has a position (square)
corresponding to each of the 8 possible combinations of the 3 Boolean variables. The upper
left position corresponds to the 000 row of the truth table, the lower right position
corresponds to 101.

49 | P a g e
The 1s are in the same places as they were in the original truth table. The 1 in the first row is
at position 110 (a = 1, b = 1, c = 0).

The minimization is done by drawing circles around sets of adjacent 1s. Adjacency is
horizontal, vertical, or both. The circles must always contain 2n 1s where n is an integer.

We have circled two 1s. The fact that the circle spans the two possible values of a
(0 and 1) means that the a term is eliminated from the Boolean expression corresponding to
this circle.

Now we have drawn circles around all the 1s. Thus the expression reduces to

m = bc + ac + ab

HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 Logic gate ICs: 1) 7408 AND 2) 7404 NOT 3) 7432 OR
 LEDs
 Logic Probe (optional)

PROCEDURE:

1. Solve the initial equation of the system by K-Map.

2. Simplify the equation as much as possible using De Morgan’s Theorem and/or
Boolean identities. (attach working on separate sheet)
3. Now build the logic circuits for the simplified Boolean expression and complete the
table.

50 | P a g e
LAB TASK
From the given truth table of a Logic Circuit, determine the simplified Boolean expression of
the system in SOP (Sum of Products) form (attach working on a separate sheet):

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Space for Simplification

51 | P a g e
 B+AC’D+A’C
Simplified Expression

Simplified logic circuit and determine its truth table

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

Home Activity: Design a lighting control system of a room which consists of three
switches. To turn the light on, it is necessary that 2 out of 3 switches must be turned o

Otherwise the light must stay off.

52 | P a g e
 Determine the simplified Boolean expression of the system in SOP (Sum of Products)
form. Construct simplified logic gate circuits of the given system on Multisim and also
verify it by means of truth table:
Put your name and roll number on circuit design suite and attach the screen shot of your
designed circuit at the end of experiment#6 (also attach necessary working on a separate
sheet)

REVIEW QUESTIONS:

Q.1) What have you learnt from this experiment?

In this experiment I have learnt that how can we made the circuit on given scenerio and

The usage of logic gates, ics. We work on different ics how can we turn on leds and how
they will be turned off on the changing of outputs of switches.and implementation of k-
map circuit.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand and use K-Maps.

LO2: Design and/or synthesis and logic circuits using K-Maps.

Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

53 | P a g e
 Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 07
OBJECTIVE:
To understand the concept of universal NAND and NOR Gates and implement Logic
Circuits using only NAND or NOR gates.

BACKGROUND THEORY:
Because the NAND function has functional completeness all logic systems can
be converted into NAND gates. This is also true of NOR gates. In principle, any
combinatorial logic function can be realized with enough NAND gates and/or NOR Gates.

NAND GATE EQUIVALENT OF BASIC LOGIC GATES

Gate Description Desired Gate NAND Equivalent

A NOT gate is made by joining the inputs of

54 | P a g e
 a NAND gate together. Since a NAND gate
NOT is equivalent to an AND gate followed by a
NOT gate, joining the inputs of a NAND
gate leaves only the NOT gate.

An AND gate is made by following a

AND NAND gate with a NOT gate

If the truth table for a NAND gate is

examined or by applying De Morgan's Laws,
it can be seen that if any of the inputs
are 0, then the output will be 1. To be an
OR gate, however, the output must be 1 if
OR any input is 1. Therefore, if the inputs are
inverted, any high input will trigger a high
output.

A NOR gate is simply an inverted OR gate.

NOR Output is high when neither input A nor
input B is high

XOR An XOR gate is constructed similarly to an

OR gate, except with an additional
NAND gate inserted such that if both inputs
are high, the inputs to the final NAND gate
will also be high, and the output will be low

XNOR An XNOR gate is simply an XOR gate with

an inverted output

NOR GATE EQUIVALENT OF BASIC LOGIC GATES

Gate Desired Gate NOR Equivalent

NOT

AND

55 | P a g e
 OR

NAND

XOR

XNOR

AND OR INVERTER (AOI) TO NANDGATE CONVERSION STEPS

1. If starting from a logic expression, implement the design with fundamental (And, Or, not)
gates logic.
2. In the fundamental implementation, identify and replace every AND, OR, and INVERTER
gate with its NAND equivalent.
3. Redraw the circuit.
4. Identify and eliminate any double inversions (i.e. back-to-back inverters).
5. Redraw the final circuit.

Example
Boolean expression to be converted into Universal NAND equivalent:

1. Implement the circuit using fundamental gates Logic:

56 | P a g e
2. Identify and replace every AND, OR and/or NOT gate with its NAND equivalent.

3. Redraw the circuit (using NAND counterparts).

57 | P a g e
 4. Identify and eliminate any double inversions (i.e. back-to-back inverters).

5. Redraw the final circuit.

NOTE: The same procedure can be followed for conversion of fundamntal gates to Universal
NOR Gates
HARDWARE REQUIRED:
 Digital and analog training system (ETS-7000A)

58 | P a g e
  Breadboard
 NAND gate IC
 Logic Probe (optional)
PROCEDURE:
1. Construct the NAND equivalent circuit on bread board.
2. Apply inputs and check corresponding Outputs.
3. Note the readings in Table 5.1, 5.2, 5.3 and 5.4
4. Compare the tables 5.1 with 5.2 and 5.3 with 5.4

LAB TASK 1:
Consider the Boolean expression given below:

a) Construct an fundamental (And, Or, Not) gate circuit for the expression and implement the
circuit.

Space for fundamental gate level circuit of the given expression:

Truth table for the fundamental (And, Or, Not) gate circuit

Input Input Input Output

A B C X
L L L 0
L L H 0
L H L 0
L H H 0
H L L 1
H L H 0
H H L 1

59 | P a g e
 H H H 1

Table: 6.1
b) Convert the fundamental gate circuit into its Universal NAND equivalent.

NAND Gate equivalent of the given expression:

Truth table for the NAND circuit

Input Input Input Output

A B C X
L L L 0
L L H 0
L H L 0
L H H 0
H L L 1
H L H 0
H H L 1
H H H 1
Table: 6.2
LAB TASK 2:

Design the equivalent circuit for the following expression using Universal NOR Gate (attach
working on separate sheet):
Á . B́+ Ć=Y

60 | P a g e
 a) Construct an fundamental gate level circuit for the expression and develop its Truth Table

Space for fundamental gate level circuit of the given expression:

Truth table for the fundamental logic gate circuit

Input Input Input Output
A B C X
L L L H
L L H H
L H L H
L H H L
H L L H
H L H L
H H L H
H H H L
Table: 6.3
b) Convert the fundamental gate level circuit into its Universal NOR equivalent.

NOR Gate equivalent of the given expression:

61 | P a g e
Truth table for the NOR circuit

Input Input Input Output

A B C X
L L L H
L L H H
L H L H
L H H L
H L L H
H L H L
H H L H
H H H L
Table: 6.4
Home Activity:
Use Multisim circuit design suite to Implement both fundamental (And, Or, Not) gates
and NAND equivalent logic gate circuits on relevant IC for given Boolean expression and
also verify both circuits by means of truth table .
Y= ( Á´. B ) + A.B
Put your name and roll number on circuit design suite and attach the screen shot of
your designed circuits at the end of experiment#7 (also attach necessary working on a
separate sheet)

62 | P a g e
REVIEW QUESTIONS:

Q.1) List at least two advantages of universal gates:

1: we have no need of any other logic gates(or and etc) for implementing boolean
functions.

2:in reducing the number of interconnections and total no of gates in digital systems,
are highlighted. We can cancel out the gates which are in series.

Q.2) What have you learnt from this experiment?

To convert the logic gates in to universal logic gates and implementation.

63 | P a g e
LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the importance of NAND and NOR Gates as Universal gates.
LO2: Apply the rules of converting AOI Gates to their Universal NAND or Universal NOR
equivalents.

Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

64 | P a g e
 Experiment # 08
OBJECTIVE:
To understand and practically observe the working of 7485 Magnitude comparator.

BACKGROUND THEORY:
A digital comparator or magnitude comparator is a hardware electronic device that
takes two numbers as input in binary form and determines whether one number is greater
than, less than or equal to the other number. Comparators are used in central processing unit s
(CPUs) and microcontrollers (MCUs).

The operation of a single bit digital comparator can be expressed as a truth table shown
below:

Inputs Outputs

A B A > B A = B A < B

0 0 0 1 0

0 1 0 0 1

1 0 1 0 0

1 1 0 1 0

Gate 1 produces the function A>B and gate 3 gives A<B while gate 2 is an XNOR gate
giving an equality output.

HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 IC 7485 (Magnitude comparator)
 LEDs
 Logic Probe (optional)

65 | P a g e
PROCEDURE:

1. The connection diagram of 7485 Magnitude Comparator is shown below:

A0 … A3 & B0 … B : 2, 4-Bit data to be compared.

Pins 5, 6, and 7 : Comparator outputs.
Pins 2, 3 and 4 : Cascading outputs, to be used if connecting another comparator.
Vcc , GND : Supply Pins for the IC.

2. Make supply connections to the IC.

3. Now apply the inputs to the comparator and check the corresponding outputs.
4. Complete the following Truth Table as per observations:

S #. A3 A2 A1 A0 B3 B2 B1 B0 A>B A=B A<B

1 0 0 0 1 1 0 1 0 0 0 1
2 1 0 0 0 1 0 1 0 0 0 1
3 1 1 1 1 1 0 1 0 1 0 1
4 1 0 1 0 1 0 1 0 0 1 0
5 0 1 1 0 0 1 1 1 0 0 1
6 0 1 1 1 0 1 1 1 0 1 0
7 1 1 0 1 1 1 1 0 0 0 1
8 0 1 0 0 1 1 1 1 0 0 1

66 | P a g e
Home Activity:

With the help of 7485 ICs, Design and Implement 8-bit magnitude comparator on
Multisim Circuit Design Suite.

Put your name and roll number on circuit design suite and attach the screen shot of
your designed circuit at the end of experiment#8 (also attach necessary working on a separate
sheet)

Review Questions:

Q.1) Write two applications of magnitude comparator?

1: magnitude comparators are used in CPU and also in micro controllers (MCUs).

2:magnitude comparators are used in biometric applications and in password verification.

Q.2) What have you learnt from this experiment?

We learnt about the workng on 2 bit , 4 bit and 8 bit magnitude comparator.

67 | P a g e
LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the working of Digital Comparators.

LO2: Experimentally verify the behavior of 7485 IC

Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5

68 | P a g e
 4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 09
OBJECTIVE:
To understand the working of half adder and full adder and verify its truth table

BACKGROUND THEORY:
In electronics, an adder or summer is a digital circuit that performs addition of numbers.
In many computers and other kinds of processors, adders are used not only in the arithmetic
logic unit(s), but also in other parts of the processor, where they are used to calculate
addresses, table indices, and similar operations.

 HALF ADDER:
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and
carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition.
The simplest half-adder design, pictured on the right, incorporates an XOR gate for S and an
AND gate for C. With the addition of an OR gate to combine their carry outputs, two half
adders can be combined to make a full adder.

69 | P a g e
 Inputs Outputs

A B Sum C. out

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

70 | P a g e
 FULL ADDER:
A full adder adds binary numbers and accounts for values carried in as well as out. A one-
bit full adder adds three one-bit numbers, often written as A, B, and Carry in (Cin); A and B
are the operands, and Cin is a bit carried in from the previous less significant stage.
The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit
binary numbers. The circuitproduces a two-bit output, output carry and sum typically
represented by the signals carry out (Cout) and Sum (S).

Inputs Outputs
A B C. in Sum C. out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

71 | P a g e
72 | P a g e
HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 Logic gate ICs: 1) 7486 XOR 2) 7408 AND 3) 7432 OR
 LEDs
 Logic Probe (optional)

PROCEDURE:

1. Construct the circuit for Half Adder on Breadboard

2. Apply all Input combinations to the circuit.
3. Check and note the outputs for the corresponding inputs and record the values in the
observation table.
4. Now construct the circuit for Full Adder on Breadboard
5. Repeat steps 2 and 3.

OBSERVATION:

Inputs Outputs Inputs Outputs

A B Sum Cout A B Cin Sum Cout
0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 1 0
1 0 0 1 0 1 0 1 0
1 1 1 1 0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

73 | P a g e
REVIEW QUESTIONS:

Q.1) Mention an application of both Half Adder and Full Adder Circuit:

The ALU (arithmetic logic circuitry) of a computer uses half adder to compute the binary
addition operation on two bits.
___________________________________________________________________________

Full adder, it adds n-bits at the time.

___________________________________________________________________________

Q.2) What have you learnt from this experiment?

The working on half and full adder and verifying their truth tables and how it is carry
in and out.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the concept of Half Adder and Full Adder.

LO2: Observe the behavior of HalfAdder and Full Adder in Logic circuits

74 | P a g e
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

75 | P a g e
 Examined By: Mubeen Ahmed Khan Date

Experiment # 10
OBJECTIVE:
To understand the working of half subtractor and full subtractor and verify its truth table

BACKGROUND THEORY:
In electronics, asubtractor is a digital circuit that performs subtraction of numbers and can be
designed using the same approach as that of an adder. First taking the 2’s complement of the
subtrahend and adding it to the minued. The 2’s complement can be obtained by taking the
1’s complement and adding 1.

To perform A - B, we complement the bit of B, add them to the bit of A, and add 1 to the
input carry as follow:

 HALF SUBTRACTOR:
Subtracting a single-bit binary value B from another A (i.e. A - B) produces a difference bit
D and a borrow out bit B-out. This operation is called half subtraction and the circuit to
realize it is called a half subtractor.

Inputs Outputs
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

76 | P a g e
 FULL SUBTRACTOR:
The full-subtractor is a combinational circuit which is used to perform subtraction of three
bits. It has three inputs, X (minuend) and Y(subtrahend) and Bi (borrow in) and two outputs
D (difference) and Bo (borrow out). The full subtractor is a combination of X-OR, AND,
NOT, OR Gates. The two half subtractor put together gives a full subtractor.

Inputs Outputs
A B Br-in D Br-out
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

77 | P a g e
HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 Logic gate ICs: 1) 7486 XOR 2) 7408 AND 3) 7404 NOT 4) 7432 OR
 LEDs
 Logic Probe (optional)

PROCEDURE:

1. Construct the circuit for half subtractor on breadboard or electronic workbench

2. Apply all Input combinations to the circuit.
3. Check and note the outputs for the corresponding inputs and record the values in the
observation table.
4. Now construct the circuit for full subtractor on breadboard or electronic workbench
5. Repeat steps 2 and 3.

OBSERVATION:

Inputs Outputs Inputs Outputs

A B Difference Borrow A B Br-in Difference Borrow
0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 1 1 1
1 0 1 0 0 1 0 1 1
1 1 0 0 0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Half Subtractor

Full Subtractor

78 | P a g e
s

REVIEW QUESTIONS:

Q.1) Mention an application of both half subtractor and full subtractor circuit:

Half subtractor is used in digital electronics

___________________________________________________________________________

Full subtractor is used in processors to compute tables, address etc.

___________________________________________________________________________

Q.2) What have you learnt from this experiment?

We have learnt about the concept of half and full subtractor , its implementation its
circuit and truth tables.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the concept of half subtractor and full subtractor.

LO2: Observe the behavior of half subtractor and full subtractor in Logic circuits.

79 | P a g e
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

80 | P a g e
 Examined By: Mubeen Ahmed Khan Date

Experiment # 11
OBJECTIVE:
To investigate the operation of seven segment display and practically observe the
working of 7447 BCD to seven segment Decoder.

BACKGROUND THEORY:
Typically 7-segment displays consist of seven individual colored LED’s (called the
segments), within one single display package. In order to produce the required numbers or
HEX characters from 0 to 9 and A to F respectively, on the display the correct combination of
LED segments need to be illuminated and BCD to 7-segment Display Decoders such as the
74LS47 do just that.

A standard 7-segment LED display generally has 8 input connections, one for each
LED segment and one that acts as a common terminal or connection for all the internal
display segments. Some single displays have also have an additional input pin to display a
decimal point in their lower right or left hand corner.

In electronics there are two important types of 7-segment LED digital display:

The Common Cathode Display (CCD) – In the common cathode display, all the cathode
connections of the LED’s are joined together to logic “0” or ground. The individual segments
are illuminated by application of a “HIGH”, logic “1” signal to the individual Anode
terminals.

The Common Anode Display (CAD) – In the common anode display, all the anode
connections of the LED’s are joined together to logic “1” and the individual segments are
illuminated by connecting the individual Cathode terminals to a “LOW”, logic “0” signal.

81 | P a g e
82 | P a g e
BCD to 7-Segment Display Decoders:
A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or
74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a
smaller 4-bit binary number (half a byte) to be used to display all the denary numbers from 0
to 9.

83 | P a g e
HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 7447 (BCD to 7 Segment Decoder)
 LEDs / Seven Segment Display
 Logic Probe (optional)

PROCEDURE:

1. The connection diagram of 7447 IC (BCD to 7-segment decoder) is shown below:

A, B, C, D : BCD inputs.
a–g : Decoded outputs.
Lamp Test : If grounded, turns all the outputs high, regardless of input
applied.
RBI & RBO : Blanking Input & Blanking Output respectively
Vcc , GND : Supply Pins for the IC.

2. Make supply connections to the IC.

3. Now apply the inputs to the Decoder on specified pins (A to D),
4. Connect a common anode 7 segment display on the outputs (a to g).
5. Observe the output on 7 Segment display.
6. Note down the observations in observation table.

84 | P a g e
Observation Table:

Decima BCD Inputs Outputs

l D C B A á b́ ć d́ é f́ ǵ
Digits
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
10 1 0 1 0 1 1 1 0 1 1 1
11 1 0 1 1 0 0 1 1 1 1 1
12 1 1 0 0 1 0 0 1 1 1 0
13 1 1 0 1 0 1 1 1 1 0 1
14 1 1 1 0 1 0 0 1 1 1 1
15 1 1 1 1 1 0 0 0 1 1 1

85 | P a g e
Home Activity:

Repeat the above lab task to generate the Simulink file on Multisim by using 74LS48
decoder package and verify it.
Put your name and roll number on circuit design suite and attach the screen shot of
your designed circuit at the end of experiment#11 (also attach necessary working on a
separate sheet)

REVIEW QUESTIONS:

Q.1) What will be displayed on 7-segment when the BCD inputs are 1111? ___0_____

Q.2) What is the function of LAMP TEST input?

The input when made active high will light all the segments regardless of the current 4
bit input being recorded.

Q.3) What have you learnt from this experiment?

86 | P a g e
How to convert the binary numbers into decimal and display the decimal numbers

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the working of 7 Segment displays.

LO2: Experimentally verify the behavior of BCD to 7 Segment Decoders

Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Sr. No. Categories Total Marks/Grade Marks /Grade

87 | P a g e
 Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 12
OBJECTIVE:
To investigate the operation of Multiplexers and practically observe the working of
74153 Dual 4-to-1 Multiplexer.

BACKGROUND THEORY:

In electronics, a multiplexer (or mux) is a device that selects one of several analog or
digital input signals and forwards the selected input into a single line. A multiplexer of 2 n
inputs has n select lines, which are used to select which input line to send to the output.
Multiplexers are mainly used to increase the amount of data that can be sent over the network
within a certain amount of time and bandwidth. A multiplexer is also called a data selector.
An electronic multiplexer makes it possible for several signals to share one device or
resource, for example one A/D converter or one communication line, instead of having one
device per input signal.

Fig. 12.1. Schematic of a 2-to-1 Multiplexer. It can be equated to a controlled switch

88 | P a g e
 Conversely, a de-multiplexer (or de-mux) is a device taking a single input signal and
selecting one of many data-output-lines, which is connected to the single input. A multiplexer
is often used with a complementary de-multiplexer on the receiving end. The schematic
below shows a 1-to-2 de-multiplexer on the left and an equivalent switch on the right.

Fig. 12.2. Schematic of a 1-to-2 De-multiplexer. Like a Multiplexer it can be equated to a

controlled switch

An electronic multiplexer can be considered as a multiple-input, single-output switch, and a

de-multiplexer as a single-input, multiple-output switch.

DESIGN PROCESS OF A MULTIPLEXER BASED CIRCUIT

The design process explained below uses 2-to-1 Multiplexer as an example system. Here we
have 21 = 2 inputs, so we must have n = 1 selector pins for the multiplexer.

S A B Z
0 1 1 1
0 1
0 1 0
0 0
1 1 1 1
0 0
0 1 1
0 0

Table 12.1. Truth Table of 2 x1 MUX

89 | P a g e
In case of Multiplexers, the selector pin ‘S’ determines which output should appear on output,
as

− If S = 0, then A is the Output (Z = A).

− If S = 1, then B is the Output (Z = B).

Keeping in view the above mentioned conditions, the Truth Table in Table 10.1 can be
simplified as:

S Z
0 A
1 B

Table 12.2. Simplified Truth Table

By closely observing the Table 12.1, we can extract the following equation for 2-to-1
Multiplexer:

Fig. 12.3. Logic circuit of 2 x1 MUX

The same method can be used to design Multiplexers with higher no. of inputs and
correspondingly higher no. of selector pins.

HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 74153 (Dual 4-to-1 Multiplexer)
 LEDs
 Logic Probe (optional)

PROCEDURE:
1. The connection diagram of 74153 Dual 4-to-1 Multiplexer is shown below:

90 | P a g e
 Fig. 12.4. Connection diagram of Dual 4x1 MUX IC

a) 1G, 2G: Pins for enabling multiplexers 1 & 2 respectively. Must be grounded for
enabling the required Multiplexer.
b) 1C0...1C3 and 2C0…2C3: The 4 inputs of Multiplexers 1 & 2 respectively.
c) A, B: Selector pins.
d) Y1, Y2: Output pins for Multiplexers 1 & 2 respectively.
e) Vcc, GND: Supply Pins for the IC.

2. Make supply connections to IC. Then ground the strobe pin 1G to enable Multiplexer

3. Now apply the inputs to the multiplexer on specified pins (1C1 to 1C3) and apply
selector combinations. Observe the output on Pin Y1. Use following Truth Table for
assistance and verifying results:

Table 12.3. Truth Table of 4 x1 MUX

4. After verifying results, design the Gate level circuit for 4-to-1 Multiplexer using
design process used in designing of 2-to-1 Multiplexer (attach working on a separate
sheet). Draw the circuit for 4x1 Multiplexer below:

Equation for 4-to-1 Multiplexer A . B . C 0+ A . B .C 1+ A . B . C 2+ A . B . C 3

91 | P a g e
 Murk
Matlani
1912275

REVIEW QUESTIONS:

Q.1) The data input and data select waveforms are applied to the multiplexer. Determine the
output waveform in relation to the inputs.

92 | P a g e
s

Q.2) Write the applications of each MUX and De-MUX in digital circuit.

If there are many loud speakers then we can use the ux to send the data on one single

Line.

It can also be used to send data of multiple security cameras on one line to display on

Single screen.

Q.3) Use three 2x1 MUX and connect them to make one 4x1 MUX

93 | P a g e
Q.4) What have you learnt from this experiment?

I have learnt how to design implement and use of DEMUX.

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the working of Multiplexers and De-multiplexers.

LO2: Experimentally verify the behavior of Multiplexers
LO3: Use Multiplexers to make circuit designing fast and simple.

94 | P a g e
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 13
95 | P a g e
OBJECTIVE:
To apply the knowledge of Combinational Logic design for solving Real World
Scenarios.

BACKGROUND THEORY:

After getting considerable knowledge in the field of Combinational circuits design

using K-Maps and there simplification using Boolean algebra and De-Morgan’s theorem, it
would be of very little use if we don’t apply them to solve various Real world situations and
to perform specific tasks.

LAB TASK:
The main target of the current lab is to study a couple of Real World problems and to
perform specific tasks by designing appropriate Combinational circuits. For the following
given situations, design appropriate Combinational circuits to perform the required functions
and implement the designed circuits on Hardware:

Scenario 1: Design a safety mechanism of an automobile which checks for seat belt and
car door before starting. If either seat belt is not fastened or door is not closed, the car engine
will not start even if the key is available in the ignition of the car.

Scenario 2: A bulb in staircases has two switches, one switch being at the ground floor and
the other one at the first floor. The bulb can be turned ON and also can be turned OFF by and
one of the switches irrespective of the state of the other switch.

Scenario 3: There are three input switches (A, B and C) in a system. The output (Y) will
only be turned on when the input combination contains more ones (1’s) than zeros (0’s).

Scenario 4: There are 3 input switches (A, B and C) in a system. The output (Y) will only
turn on when the number of turned on switches are odd.

Scenario 5: Design a combination detector logic circuit for 0000, 0010, 1000 and 1010.

96 | P a g e
 SCENARIO 1
(Attach working on a separate sheet)

Truth Table Logic Circuit

Logic Expression

SCENARIO 2

(Attach working on a separate sheet)

Truth Table Logic Circuit

Logic Expression

97 | P a g e
 SCENARIO 3

(Attach working on a separate sheet)

Truth Table

Logic Expression

Logic Circuit

98 | P a g e
 SCENARIO 4

(Attach working on a separate sheet)

Truth Table

Logic Expression

Logic Circuit

99 | P a g e
 SCENARIO 5

(Attach working on a separate sheet)

Truth Table

Logic Expression

Logic Circuit

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Use the knowledge of Combinational Logic design to solve Real World problems and
to analyze the usefulness of Digital circuits in handling fairly complex problem

100 | P a g e
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 14
101 | P a g e
OBJECTIVE:
To familiarize with the concept of sequential circuits and study the working of SR
Latch, Gated SR Flip Flop and D-type Flip Flop.

BACKGROUND THEORY:

Unlike Combinational Logic circuits that change state depending upon the actual
signals being applied to their inputs at that time, Sequential Logic circuits have some form of
inherent “Memory” built in to them as they are able to take into account their previous input
state as well as those actually present, a sort of “before” and “after” effect is involved with
sequential logic circuits.In other words, the output state of a “sequential logic circuit” is a
function of the following three states, the “present input”, the “past input” and/or the “past
output”. Sequential Logic circuits remember these conditions and stay fixed in their current
state until the next clock signal changes one of the states, giving sequential logic circuits
“Memory”.Sequential logic circuits are generally termed as two state or Bistable devices
which can have their output or outputs set in one of two basic states, a logic level “1” or a
logic level “0” and will remain “latched” (hence the name latch) indefinitely in this current
state or condition until some other input trigger pulse or signal is applied which will cause the
bistable to change its state once again.

Following is the Block Diagram of a Sequential logic. Note that a sequential logic is
mainly a combinational logic with memory element (flip flops) added to it:

Fig. 14.1. Block diagram of sequential circuit

102 | P a g e
SR-LATCH
The SR Latch, also known as SR flip-flop, can be considered as one of the most basic
sequential logic circuit possible. This simple flip-flop is basically a one-bit memory bistable
device that has two inputs, one which will “SET” the device (meaning the output = “1”), and
is labelled ‘S’ and another which will “RESET” the device (meaning the output =
“0”),labelled ‘R’.Then the SR description stands for “Set-Reset”. The reset input resets the
flip- flop back to its original state with an output Q that will be either at a logic level “1” or
logic “0” depending upon this set/reset condition.

The basic SR Latch can be implemented by using either NAND Gates (NAND Latch)
or NOR gates (NOR Latch), both of them are shown as under:
NAND LATCH NOR LATCH
To make single bit SR NAND Latch, As well as using NAND gates, it is also
connect together a pair of cross- coupled 2- possible to construct simple one-bit SR
input NAND gates as shown, to form a Set- Flip-flops using two cross-coupled NOR
Reset Bistable also known as an active gates connected in the same configuration.
LOW SR NAND Gate Latch, so that there The circuit will work in a similar way to
is feedback from each output to one of the the NAND gate circuit above, except that
other NAND gate inputs. This device the inputs are active HIGH and the invalid
consists of two inputs, one called the Set, condition exists when both its inputs are at
‘S’ and the other called the Reset, ‘R’ with logic level “1”, and this is shown below:
two corresponding outputs ‘Q’ and its
inverse or complement Q (Q’) as shown
below:

Fig. 14.2a. SR NAND Latch Circuit

Fig. 14.2b. SR NOR Latch Circuit

S R Q Q’ S R Q Q’
0 1 1 0 1 0 1 0
1 1 1 0 0 0 1 0
1 0 0 1 0 1 0 1
0 0 1 1 Invalid 1 1 1 1 Invalid

Table 14.1a. Truth table of SR NAND Latch Table 14.1b. Truth table of SR NOR Latch

GATED SR Latch
It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only
changes state when certain conditions are met regardless of the condition of either the Set or
the Reset inputs. By connecting a 2-input AND gate in series with each input terminal of the
SR Flip-flop a Gated SR Flip-flop can be created. This extra conditional input is called an
“Enable” input and is given the prefix of “E“. The addition of this input means that the output
at Q only changes state when it is HIGH and can therefore be used as a clock (CLK) input
making it level-sensitive. The circuit symbol with internal circuitryis shown below:

103 | P a g e
 Fig. 14.3. Gated SR-type flip flop symbol and logic circuit

When the Enable input “E” is at logic level “0”, the outputs of the two AND gates are also at
logic level “0”, (AND Gate principles) regardless of the condition of the two inputs S and R,
latching the two outputs Q and Q into their last known state. When the enable input “E”
changes to logic level “1” the circuit responds as a normal SR bistable flip-flop with the two
AND gates becoming transparent to the Set and Reset signals.This additional enable input
can also be connected to a clock timing signal (CLK) adding clock synchronization to the
flip-flop creating what is sometimes called a “Clocked SR Flip-flop“. So a Gated Bistable SR
Flip-flop operates as a standard bistable latch but the outputs are only activated when a logic
“1” is applied to its E input and deactivated by a logic “0”.The Truth Table for Gated SR Flip
Flop is as follows:

E/C S R Q Q’
0 X X Qprev Qprev
1 1 0 1 0
1 0 0 1 0
1 0 1 0 1
1 1 1 1 1

Table 14.2. Truth table of Gated SR-type flip flop

Major Drawback in an SR Flip Flop:

Both S & R inputs cannot be ‘0’ (NAND Latch) or ‘1’ (NOR Latch) at the same time as it
may cause the latch to produce undesirable results at output.

D-TYPE Latch
One way to eliminate the undesirable condition of the indeterminate state in SR Latch is to
ensure that the inputs ‘S’ & ‘R’ are never equal to ‘1’ at the same time. This is done in the D-
Latch (or D-type Flip Flop). This latch has only two inputs: ‘D (Data)’ and ‘E/C
(Enable/Control)’. The ‘D’ input goes directly to the ‘S’ input and its complement is applied
to the ‘R’ input. The resulting Gate level circuit with circuit symbol is shown below:

104 | P a g e
 Fig. 14.4. Gated D-type Flip Flop symbol and logic circuit

E/C D Q Q’ Comment

0 X Qprev Qprev No change

1 0 0 1 Reset

1 1 1 0 Set

Table 14.3. Truth table of Gated D-type Latch

HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 Logic ICs a) NOT gate b) AND gate c) NOR gate
 LEDs
 Logic Probe (optional)

PROCEDURE:

1. Connect the circuit of SR Latch as shown in figure 12.3 and verify the Truth Table.

2. Now connect the inverter between S and R inputs (D-type Latch configuration) and
verify the truth table for D-type Latch.

105 | P a g e
REVIEW QUESTIONS:

Q.1) Draw the output waveform of each type of Latches (S R Latch, Gated S R Latch
and Gated D-Latch)

[S R Latch]

[Gated S R Latch]

[Gated D type Latch]

LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the concept of Sequential Logic

LO2: Understand the working of SR Latch, Gated SR Latch and D Type Latch

106 | P a g e
 Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

107 | P a g e
 Examined By: Mubeen Ahmed Khan Date

Experiment # 15
OBJECTIVE:
To understand the working of JK Type Flip Flop, and study the error safe
configuration of JK Flip Flop (Master-Slave configuration).

BACKGROUND THEORY:
This simple JK flip Flop is the most widely used of all the flip-flop designs and is
considered to be a universal flip-flop circuit. The JK flip flop is basically a gated SR Flip-flop
with the addition of a clock input circuitry that prevents the illegal or invalid output condition
that can occur when both inputs S and Rare equal to logic level “1”. Due to this additional
clocked input, a JK flip-flop has four possible input combinations:

1. Logic 1
2. Logic 0
3. No change
4. Toggle

Fig. 15.1. Gated JK-type flip flop symbol and logic circuit

Inpu Outpu Descriptio Comments

t t n
J K Q Q’
0 0 0 0 Memory same as
0 0 0 1 no change for the
0 1 1 0 Reset Q » 0 SR Latch
0 1 0 1
1 0 0 1 Set Q » 1

108 | P a g e
 1 0 1 0
1 1 0 1 Toggle toggle
1 1 1 0 action

Table 15.1. Truth table of Gated JK flip flop

Although above circuit is an improvement on the clocked SR flip-flop it still suffers

from timing problems called “race” if the output ‘Q’ changes state before the timing pulse of
the clock input has time to go “OFF”. To avoid this the timing pulse period (T) must be kept
as short as possible (high frequency). As this is sometimes not possible with modern TTL
IC’s the much improved Master-Slave JK Flip-flop was developed.

THE MASTER -SLAVE JK FLIP -FLOP

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in

a series configuration with the slave having an inverted clock pulse. The outputs from Q and
Q from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the “Slave” flip flop. This feedback
configuration from the slave’s output to the master’s input gives the characteristic toggle of
the JK flip flop as shown below:

Fig. 15.2. Gated Master-Salve JK flip flop circuit

The input signals J and K are connected to the gated “master” SR flip flop which
“locks” the input condition while the clock (CLK) input is “HIGH” at logic level “1”. As the
clock input of the “slave” flip flop is the inverse (complement) of the “master” clock input,
the “slave” SR flip flop does not toggle. The outputs from the “master” flip flop are only
“seen” by the gated “slave” flip flop when the clock input goes “LOW” to logic level “0”.
Following is the working mechanism:

− When the clock is “LOW”, the outputs from the “master” flip flop are latched and any
additional changes to its inputs are ignored. The gated “slave” flip flop now responds to the
state of its inputs passed over by the “master” section.

− Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop
are fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low”
transition the same inputs are reflected on the output of the “slave” making this type of flip
flop edge or pulse-triggered.

− Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to
the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip

109 | P a g e
flop is a “Synchronous” device as it only passes data with the timing of the clock signal.

HARDWARE REQUIRED:

 Power supply with cables

 Breadboard
 7473 Dual JK Flip Flops
 LEDs
 Logic Probe (optional)

PROCEDURE:

1. The connection diagram of 7473 or 7476 Dual JK Flip Flop is shown below:

7473 7476

Fig. 15.3. Connection diagram of Dual JK flip flop IC

a) 1J, 2J, 1K, and 2K: Pins for J and K inputs for flip flops 1 & 2 respectively.
b) 1CLK and 1CLK: Clearing Inputs for Flip Flops 1 & 2 respectively. Activated
by grounding pins where required.
c) 1CK, 2CK: Clock inputs for Flip Flops 1 & 2 respectively.
d) Q1, Q2, Q1, and Q2’: Output pins for Flip Flops 1 & 2 respectively.

2. Connect the circuit as shown in figure 13.2 for Master Slave JK Flip Flop.

3. Now apply the inputs to the Flip Flop on specified pins (J1, J2, K1& K2). Apply
Clock input on 1CLR and inverted clock on 2 CLR. Observe the output on Pins Q1
&Q2’.

4. Note the observations in the following Truth Table compare it with Table 13.1.

110 | P a g e
 Input Output Description
J K Q Q’
Table 15.2. Truth table of experimental findings
0 0 0 0 MEMORY
Review Questions: 0 0 0 0
0 1 0 1 RESET Q_>0
Q.1) Complete the following timing diagram
of J-k flip flop. 0 1 0 1
1 0 1 0 SET Q_>0
1 0 1 0
1 1 0 1 TOGGLE
1 1

Q.2) Give some application of J-K type flip flop

Stop watch, clock

Decade counter

Q.3) what have you learnt from this experiment.

In this experiment I have learnt how JK flip flop works and its implementation and on
different circuits its usage.

111 | P a g e
LEARNING OUTCOMES:

Upon successful completion of the lab, students will be able to:

LO1: Understand the operations of JK Flip Flop.

LO2: Understand the possible shortcoming in JK Flip Flops and its correction by the concept
of JK Master Slave Flip Flop

Lab’s Evaluation Sheet

Students Registration No 1912275

Date Performed:
Section: E

Date of Submission

Sr. No. Categories Total Marks/Grade Marks /Grade

112 | P a g e
 Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 16
OBJECTIVE:
To understand the operation of Asynchronous and Synchronous Sequential circuit
and implement them by using JK Flip Flops.

BACKGROUND THEORY
In digital circuit theory, sequential logic is a type of logic circuit whose output
depends not only on the present value of its input signals but on the sequence of past inputs,
the input history. This is in contrast to combinational logic, whose output is a function of only
the present input. That is, sequential logic has state (memory) while combinational logic does
not. Or, in other words, sequential logic is combinational logic with memory.

In digital logic and computing, a counter is a device which stores (and sometimes

displays) the number of times a particular event or process has occurred, often in relationship
to a clock signal. The most common type is a sequential digital logic circuit with an input line
called the "clock" and multiple output lines.

Synchronous sequential Circuit

In Synchronous circuit the circuit generate sequence with repetitive of pulses or clock.
The basic memory element in sequential logic is the flip-flop. The output of each flip-flop
only changes when triggered by the clock pulse, so changes to the logic signals throughout
the circuit all begin at the same time, at regular intervals, synchronized by the clock.

Asynchronous sequential Circuit

Asynchronous sequential logic is not synchronized by a clock signal; the outputs of

113 | P a g e
the circuit change directly in response to changes in inputs. The advantage of asynchronous
logic is that it can be faster than synchronous logic, because the circuit doesn't have to wait
for a clock signal to process inputs. Asynchronous logic is more difficult to design and is
subject to problems not encountered in synchronous designs.

Signal Edge
A signal edge is a transition in a digital signal either from low to high (0 to 1) or from
high to low (1 to 0). It is called an "edge" because the square wave which represents a signal
has edges at those points.

1) Rising Edge
A rising edge is the transition from low to high. It is also named positive edge. When
a circuit is rising edge-triggered, it becomes active when its clock signal goes from
low to high, and ignores the high-to-low transition.

2) Falling Edge
A falling edge is the high to low transition. It is also known as the negative edge.
When a circuit is falling edge-triggered, it becomes active when the clock signal goes
from high to low, and ignores the low-to-high transition.

Falling Edge of Pulse Rising Edge of Pulse

Current State Next State
D C B A D C B A
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 1 0 1 0
1 0 1 0 1 0 1 1
1 0 1 1 1 1 0 0
1 1 0 0 1 1 0 1
1 1 0 1 1 1 1 0
1 1 1 0 1 1 1 1
1 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1

114 | P a g e
1 0 0 1 0 0 0 0

Clock Timing diagram of 4-bit Up-Counter

Circuits of 4-bit sequential Up-Counters

4-bit Up-Counter Asynchronous Sequential circuit

4-bit Up-Counter Synchronous Sequential circuit

115 | P a g e
HARDWARE REQUIRED:

 Power Supply with cables

 Breadboard
 7473 or 7476 Dual JK Flip Flops
 LEDs
 Logic Probes (optional)

7473 Dual JK Flip Flop with Clear 7476 Dual JK Flip Flop with Clear & Pre-Set
PROCEDURE (for Asynchronous Sequential circuit)
1. The connection diagram of 7473 or 7476 Dual JK Flip Flop is shown above
2. Connect 2 IC on Bread Board and Multisim.
3. Connect J & K input of all Flip Flop to VCC
4. Connect the clock input of first flip flop to square wave generator or switch
5. Connect the output Q of first flip flop to clock input of second flip flop
6. Connect LED on the Q output
7. Make connection of remaining flip flop like in step 5 and 6

Clock D C B A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

116 | P a g e
PROCEDURE (for Synchronous Sequential circuit)
1. The connection diagram of 7473 or 7476 Dual JK Flip Flop is shown above
2. Connect 2 IC on Bread Board and Multisim.
3. Connect J & K input of first Flip Flop to VCC.
4. Connect clock of all flip flop to square wave generator or switch
5. Short the J and K input of second flip flop to the Q output of first Flip flop
6. Take an 2-input AND Gate and connect its input to output Q of first and second flip
flop
7. Connect the output of AND Gate to J&K input of third flip flop
8. Take another 2-input AND Gate and connect its input to output Q of third flip flop
and output of first AND Gate
9. Connect the output of second AND Gate to J&K input of forth flip flop
10. Connect LED on the Q output

Clock D C B A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Review Questions:

Q.1) What is the difference between synchronous and asynchronous counters?

Q.2) Draw the timing waveforms for 4-bit Asynchronous Up Counter

117 | P a g e
Q.3) Draw the timing waveforms for 4-bit Synchronous Up Counter

118 | P a g e
Q.3) What have you learnt from this experiment.

LEARNING OUTCOMES

Upon successful completion of the lab, students will be able to:

LO1: design counter by flip flop.

LO2: Understand the difference between Asynchronous and Synchronous Sequential Up-
Counter

Lab’s Evaluation Sheet

Students Registration No
Date Performed:
Section:
Date of Submission

119 | P a g e
 Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

Experiment # 17
OBJECTIVE:
To understand the operation of Up and Down Synchronous Counters and
implementing using JK Flip Flops.

BACKGROUND THEORY:
A sequential circuit that goes through a prescribed sequence of states upon the
application of input pulses is called a Counter. A counter is a device that stores the number of
times a particular event or process has occurred. A counter consists of cascaded flip flops so
that the output of one flip flop drives the input of the next. The output Q of any given flip
flop is a binary digit or bit. The complete set of outputs (Q2, Q1, Q0) gives the total number
of pulses in binary arithmetic, hence the name binary counter. A binary counter counts from 0
to 2N-1, where N is the number of flip flops/bits in the counter.

The counter that we shall consider uses JK flip flops. These devices generate binary
numbers in a specified count sequence when triggered by an incoming clock waveform. The
output of JK flip flop changes only at the time of the negative/positive edge (edge triggered)
of a pulse at the clock input. On each trigger, the counter advances to the next number in the
sequence. After reaching the final state in the sequence, the counter then recycles.

There are fundamentally two types of counters that we can make with flip-flops. The
first is called an asynchronous or ripple counter. In this type of counter, we feed the first or
lowest order flip-flop with the clock, and it is arranged to change state on every clock input.
The Q output of the first device is then fed to the clock input of the second, which will
change state once for every change of the first device. The Q output of the second device is
fed to the clock input of the third, etc. However, the second flip-flop cannot change state until

120 | P a g e
the first has already changed, and the third cannot change state until both the first and the
second have changed. This means that there is a delay between the outputs of each device
that takes its input from a previous one. (Below is the timing diagram of a negative edge
triggered 3-bit asynchronous counter.)

This delay is the internal propagation delay of the flip-flop in use. Therefore, the
count takes a brief time to stabilize, and the circuit cannot be used in time-critical circuits.
The term Asynchronous refers to events that do not occur at the same time. With respect to
counter operation, asynchronous means that the flip flops within the counter are not
connected in a way to cause all flip flops’ change states at the same time.

The term synchronous refers to events that do occur simultaneously. With respect to
counter operation, synchronous means that the counter is connected such that all the flip flops
change state at the same time, they are wired in a way that links all the flip flops’ clock inputs
together.

IC configuration:

Binary 4-bit synchronous up counter

121 | P a g e
 Binary 4-bit synchronous down counter

HARDWARE REQUIRED:

 74LS76 IC
 Breadboard
 Logic gate ICs: 1) 7408 AND 2) 7404 NOT 3) 7432 OR
 LEDs
 Logic Probe (optional)
PROCEDURE:
1. Construct the circuits for both counters on breadboard and Multisim.
2. Apply clock input to observe the output of the counter.
3. Note down the output values on a truth table and confirm that these are matching with
the desired values.

Up Counter Down Counter

States QD QC QB QA States QD QC QB QA
0 15
1 14
2 13
3 12
4 11
5 10
6 9
7 8

122 | P a g e
 8 7
9 6
10 5
11 4
12 3
13 2
14 1
15 0

REVIEW QUESTIONS:

Q.1) What is the difference between synchronous and asynchronous counters?

Q.2) How can we design a counter that counts up to a particular decimal number and then
resets itself for re-counting?

LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:

LO1: Understand the difference between Up and Down Synchronous Counter.

LO2: Design the counters using JK flip flops.

Lab’s Evaluation Sheet

Students Registration No
Date Performed:
Section:

123 | P a g e
 Date of Submission

Marks /Grade
Sr. No. Categories Total Marks/Grade
Obtained
1 Student’s Behavior 3

2 Lab Performance 4
3 On Time Submission 5
4 Home Activity 8

Net Result 20

Examined By: Mubeen Ahmed Khan Date

124 | P a g e