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2.introduction To HDLs

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25 views15 pages

2.introduction To HDLs

Uploaded by

Ramesh Nair
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Introduction

 Gateway Design Automation


 Cadence purchased Gateway in 1989.
 Verilog was placed in the public domain.
 Open Verilog International (OVI)
 IEEE Standard
VLSI Design Flow
 System Specification
 Initial Step
 Higher Level Description
 Architectural Design
 Basic Architecture
 Functional Design
 Behavioral design
 Function to be implemented
 Logic Design
 Arithmetic and Logic Operations

 Circuit Design
- Circuit Level modeling
 Physical Design
- Circuit to layout
Verilog
 A modeling language for a very efficient event driven
digital logic simulator.
 Used as a specification language for logic synthesis.
 Now, one of the two most commonly-used languages
in digital hardware design.
 Virtually every chip (FPGA, ASIC, etc.) is designed in
part using one of these two languages.
 Combines structural and behavioral modeling styles.
Concurrent Language
 Verilog or any HDL has to have the power to model
concurrency which is natural to a piece of hardware.
 Pieces of two hardware which are even independent of
each other.
 Verilog gives the following constructs for concurrency:
– always – assign – module instantiation – non-
blocking assignments inside a sequential block
Concurrency
 The simulating machine is sequential.
 No-matter how many processors I have, I can write one
more process which also have to be simulated
concurrently.
 So, the processes are scheduled sequentially so that we
have a feeling of parallelism.
Example
Identifiers in Verilog
 Any Sequence of letter, digits, dollar sign, underscore.
 First character must be a letter or underscore.
 It cannot be a dollar sign.
 Cannot use characters such as hyphen, brackets, or #
in verilog names
Logic Values
 Predefined logic value system or value set : ‘0’, ‘1’ ,’x’
and ‘z’;

 ‘x’ means uninitialized or unknown logic value

 ‘z’ means high impedance value


Data Types
 Nets: wire, supply1, supply0
 reg
 wire:
 i) Analogous to a wire in an ASIC.
 ii) Cannot store or hold a value.
 Integer
The reg Data Type
 Register Data Type: Comparable to a variable in a
programming language.
 Default initial value: ‘x’
 module reg_ex1; reg Q; wire D; always @(posedge clk)
Q=D;
 A reg is not always equivalent to a hardware register,
flipflop or latch.
 module reg_ex2; // purely combinational reg c; always
@(a or b) c
Difference between driving and
assigning
 Programming languages provide variables that can
contain arbitrary values of a particular type.
 They are implemented as simple memory locations.
 Assigning to these variables is the simple process of
storing a value into the memory location.
 Verilog reg operates in the same way. Previous
assignments have no effect on the final result
Wire
 Consider a set of tristate drivers connected to a
common bus.
 The output of the wire depends on all the outputs and
not on the last one.
 To model connectivity, any value driven by a device
must be driven continuously onto that wire, in parallel
with the other driving values
Numbers
 Format of integer constants: Width’ radix value;
 Verilog keeps track of the sign if it is assigned to an
integer or assigned to a parameter.
 Once verilog looses sign the designer has to be careful.
Sequential Blocks
 Sequential block is a group of statements between a
begin and an end.
 A sequential block, in an always statement executes
repeatedly.
 Inside an initial statement, it operates only once.

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