UNIT-1

Introduction to Low Power VLSI

1.1 Introduction
❖ VLSI-Very Large Scale Integration- Very-large-scale integration (VLSI) is the
process of creating an integrated circuit (IC) by combining hundreds of thousands of
transistors or devices into a single chip.
❖ Design for low power has become nowadays one of the major concerns for complex,
very-large-scale-integration (VLSI) circuits.

❖ Micron Technology ==> 1μm, 2μm, 3μm, etc

❖ Sub-Micron Technology ==> 0.8μm, 0.6μm, 0.35μm 0.25μm etc
❖ Deep Sub-Micron Technology ==> 0.18μm, 0.13μm
❖ Nanotechnology ==> 90nm, 65nm etc
1.2 Historical Background

❖ Moore’s law-Component density in an IC would double every 18 months.

❖ Evolution of IC Technology
Table 1.1 Evolution of IC Technology
Year Technology Number of Typical Product
Components
1947 Invention of transistor 1 -
1950–1960 Discrete components 1 Junction diodes and
transistors
1961–1965 Small-scale 10-100 Planner devices,
integration logic gates,
flip-flops
1966–1970 Medium-scale 100–1000 Counters, MUXs,
integration decoders,
adders
1971–1979 Large-scale 1000–20,000 8-bit μp, RAM, ROM
integration
1980–1984 Very-large-scale 20,000–50,000 DSPs, RISC
integration processors,
16-bit, 32-bit
μP
1985– Ultra-large-scale > 50,000 64-bit μp, dual-core
integration μP
MUX-Multiplexer, μP-Microprocessor, RAM-Random-Access Memory, ROM -
Read-Only Memory, DSP-Digital Signal Processor, RISC-Reduced Instruction Set
Computer

❖ Landmark Years of Semiconductor Industry

✓ 1947: Invention of transistor by William Shockley in Bell Laboratories.
✓ 1959: Fabrication of several transistors on a single chip (IC).
✓ 1965: Birth of Moore’s law; based on simple observation, Gordon Moore predicted
that the complexity of ICs, for minimum cost, would double every year.
✓ 1971: Development of the first microprocessor—“CPU on a chip” by Intel.
✓ 1978: Development of the first microcontroller—“computer on a chip.”
✓ 1975: Moore revised his law, stipulating the doubling in circuit complexity to every
18 months.
✓ 1995: Moore compared the actual performance of two kinds of devices, dynamic
random-access memory (DRAM) and microprocessors, and observed that both
technologies have followed closely.
1.3 Why Low Power?

❖ Important issue in the present day VLSI circuit realization

✓ Increasing Transistor Count
✓ Higher Speed of Operation
✓ Greater Device Leakage Currents

❖ Packaging and Cooling Cost

✓ Contemporary high performance processor consume heavy power
✓ Cost associated with packaging and cooling such devices is prohibitive
✓ Low power methodology to be used to reduce cost of packaging and cooling

❖ Reliability
✓ Every 10°C rise in temperature roughly doubles the failure rate

Fig. 1.1 Different Failure Mechanisms against Temperature

❖ Environment
✓ According to an estimate of the US Environmental Protection Agency (EPA), 80 %
of the power consumption by office equipment is due to computing equipment and a
large part from unused equipment.
✓ Power is dissipated mostly in the form of heat.
✓ The cooling techniques, such as air conditioner, transfer the heat to the environment.
✓ To reduce adverse effect on environment, efforts such as EPA’s Energy Star program
leading to power management standard for desktop and laptops has emerged.
1.4 Sources of Power Dissipations
1.4.1 POWER and ENERGY
Power is the instantaneous power in the device, while energy is the integration of
power with time. Figure 1.2 illustrates the difference between power energy. For
example, in Fig. 1.2, we can see that approach 1 takes less time but consumes more
power than approach 2. But the energy consumed by the two, that is, the area under
the curve for both the approaches is the same, and the battery life is primarily
determined by this energy consumed.
 Fig. 1.2 Power versus Energy

1.4.2 Power dissipation is measured commonly in terms of two types of metrics:

1. Peak power: Peak power consumed by a particular device is the highest amount of
power it can consume at any time. The high value of peak power is generally related
to failures like melting of some interconnections and power-line glitches.
2. Average power: Average power consumed by a device is the mean of the amount
of power it consumes over a time period. High values of average power lead to
problems in packaging and cooling of VLSI chips.

1.4.3 Types of Power Dissipations

❖ Dynamic power is the power consumed when the device is active, that is,
when the signals of the design are changing values.
❖ Static power is the power consumed when the device is powered up but
no signals are changing value. In CMOS devices, the static power
consumption is due to leakage mechanism. Various components of
power dissipation in CMOS devices can therefore be categorized as
shown in Fig. 1.3.

Fig. 1.3 Types of power dissipation

1.4.4 Dynamic Power Dissipation

❖ Dynamic power is the power consumed when the device is active, that is,
when the signals of the design are changing values. It is generally
categorized into three types:
✓ Switching Power
✓ Short-Circuit Power
✓ Glitching Power

1.4.4.1 Switching Power Dissipation

❖ The first and primary source of dynamic power consumption is the
Switching power dissipation occurs due the power required to charging
and discharging of the output capacitance on a gate. Figure 1.4 illustrates
switching power for charging a capacitor.

Fig. 1.4 Dynamic (switching) power.

The energy per transition is given by
𝟏
𝑬𝒏𝒆𝒓𝒈𝒚/𝑻𝒓𝒂𝒏𝒔𝒊𝒕𝒊𝒐𝒏=𝟐 × 𝑪𝑳 × 𝑽𝟐𝒅𝒅 (1.1)
Where CL is the load capacitance and Vdd is the supply voltage
Switching power is therefore expressed as:

𝑬𝒏𝒆𝒓𝒈𝒚
𝑷𝒔𝒘𝒊𝒕𝒄𝒉 = 𝑻𝒓𝒂𝒏𝒔𝒊𝒕𝒊𝒐𝒏 × 𝒇 = 𝑪𝑳 × 𝑽𝟐𝒅𝒅 × 𝑷𝒕𝒓𝒂𝒏𝒔 × 𝒇𝒄𝒍𝒐𝒄𝒌 (1.2)

Where f is the frequency of transitions, Ptrans is the probability of an output transition

and fclock is the frequency of the system clock

In addition to the switching power dissipation for charging and discharging the load
capacitance, switching power dissipation also occurs for charging and discharging of the
internal node capacitance. Thus, total switching power dissipation is given by
𝟐
𝐏𝐭𝐨𝐭𝐚𝐥𝐬𝐰𝐢𝐭𝐜𝐡 = 𝐂𝐋 × 𝐕𝐝𝐝 × 𝐏𝐭𝐫𝐚𝐧𝐬 × 𝐟𝐜𝐥𝐨𝐜𝐤 + ∑ 𝛂𝐢 × 𝐂𝐢 × 𝐕𝐝𝐝 × (𝐕𝐝𝐝 − 𝐕𝐭𝐡 ) × 𝐟𝐜𝐥𝐨𝐜𝐤 (1.3)

Where αi and Ci are the transition probability and capacitance, respectively, for an internal
node i.
1.4.4.2 Short-Circuit Power Dissipation
In addition to the switching power, short-circuit power also contributes to the
dynamic power. Figure 1.5 illustrates short-circuit currents. Short-circuit currents occur when
both the negative metal–oxide–semiconductor (NMOS) and positive metal–oxide–
semiconductor (PMOS) transistors are ON. Let Vtn be the threshold voltage of the NMOS
transistor and Vtp is the threshold voltage of the PMOS transistor. Then, in the period when
the voltage value is between Vtn and Vdd–Vtp, while the input is switching either from 1 to 0
or vice versa, both the PMOS and the NMOS transistors remain ON, and the short-circuit
current follows from Vdd to ground (GND).

Fig. 1.5 Short-circuit current or crowbar current.

The expression for short-circuit power is given by
𝝁𝜺𝒐𝒙 𝑾
𝑷𝒔𝒉𝒐𝒓𝒕𝒄𝒊𝒓𝒄𝒖𝒊𝒕 = 𝒕𝒔𝒄 × 𝑽𝒅𝒅 × 𝑰𝒑𝒆𝒂𝒌 × 𝒇𝒄𝒍𝒐𝒄𝒌 = 𝟏𝟐𝑳𝑫 × (𝑽𝒅𝒅 − 𝑽𝒕𝒉 )𝟑 × 𝒕𝒔𝒄 × 𝒇𝒄𝒍𝒐𝒄𝒌 (1.4)
✓ Where tsc is the rise/fall time duration of the short-circuit current
✓ Ipeak is the total internal switching current (short-circuit current plus the current to charge
the internal capacitance)
✓ μ is the mobility of the charge carrier
✓ εox is the permittivity of the silicon dioxide
✓ W is the width
✓ L is the length
✓ D is the thickness of the silicon dioxide

From the above equation it is evident that the short-circuit power dissipation depends on the
supply voltage, rise/fall time of the input and the clock frequency apart from the physical
parameters. So the short-circuit power can be kept low if the ramp (rise/fall) time of the input
signal is short for each transition. Then the overall dynamic power is determined by the
switching power.

1.4.4.3 Glitching Power Dissipation

The third type of dynamic power dissipation is the glitching power which arises due to finite
delay of the gates. Since the dynamic power is directly proportional to the number of output
transitions of a logic gate, glitching can be a significant source of signal activity and deserves
mention here. Glitches often occur when paths with unequal propagation delays converge at
the same point in the circuit. Glitches occur because the input signals to a particular logic
block arrive at different times, causing a number of intermediate transitions to occur before
the output of the logic block stabilizes. These additional transitions result in power
dissipation, which is categorized as the glitching power.
1.4.5 Static Power Dissipation
Static power is the power consumed when the device is powered up but no signals are
changing value. In CMOS devices, the static power consumption is due to leakage
mechanism.
 Figure 1.6 shows several leakage mechanisms that are responsible for static power
dissipation. Here, I1 is the reverse-bias p–n junction diode leakage current, I2 is the reverse-
biased p–n junction current due to tunneling of electrons from the valence band of the p
region to the conduction band of the n region, I3 is the sub-threshold leakage current between
the source and the drain when the gate voltage is less than the threshold voltage ( Vth), I4 is
the oxide tunneling current due to reduction in the oxide thickness, I5 is the gate current due
to hot carrier injection of electrons (I4 and I5 are commonly known as IGATE leakage
current), I6 is the gate-induced drain leakage current due to high field effect in the drain
junction, and I7 is the channel punch through current due to close proximity of the drain and
the source in short-channel devices. These are generally categorized into four major types:
Sub-threshold leakage, Gate leakage, Gate-induced drain leakage, and Junction leakage
as shown in Fig. 1.7

Fig. 1.6 Leakage currents in an MOS transistor.

Fig. 1.7 Leakage currents in a CMOS inverter.

✓ Apart from these four primary leakages, there are few other leakage currents which
also contribute to static power dissipation, namely,
➢ Reverse-bias P–N junction diode leakage current
➢ Hot carrier injection gate current
➢ Channel punch through current

1.5.1 Low Power Design Methodology

Low-power design methodology needs to be applied throughout the design process
starting from system level to physical or device level to get effective reduction of power
dissipation in digital circuits based on MOS technology. Various approaches can be used at
different level of design hierarchy.
 As the most dominant component has quadratic dependence and other components have
linear dependence on the supply voltage, reducing the supply voltage is the most effective
means to reduce dynamic power consumption. Unfortunately, this reduction in power
dissipation comes at the expense of performance. It is essential to devise suitable mechanism
to contain this loss in performance due to supply voltage scaling for the realization of low-
power high-performance circuits. The loss in performance can be compensated by using
suitable techniques at the different levels of design hierarchy; that is physical level, logic
level, architectural level, and system level. Techniques like device feature size scaling,
parallelism and pipelining, architectural-level transformations, dynamic voltage, and
frequency scaling.
Apart from scaling the supply voltage to reduce dynamic power, another alternative
approach is to minimize the switched capacitance comprising the intrinsic capacitances
and switching activity. Choosing which functions to implement in hardware and which in
software is a major engineering challenge that involves issues such as cost complexity,
performance, and power consumption. From the behavioral description, it is necessary to
perform hardware/software partitioning in a judicious manner such that the area, cost,
performance, and power requirements are satisfied. Transmeta’s Crusoe processor is an
interesting example that demonstrated that processors of high performance with remarkably
low power consumption can be implemented as hardware–software hybrids. The approach is
fundamentally software based, which replaces complex hardware with software, thereby
achieving large power savings.
In CMOS digital circuits, the switching activity can be reduced by algorithmic
optimization, by architectural optimization, by use of suitable logic-style or by logic- level
optimization. The intrinsic capacitances of system-level busses are usually several orders of
magnitude larger than that for the internal nodes of a circuit. As a consequence, a
considerable amount of power is dissipated for transmission of data over I/O pins. It is
possible to save a significant amount of power reducing the number of transactions, i.e., the
switching activity, at the processors I/O interface. One possible approach for reducing the
switching activity is to use suitable encoding
of the data before sending over the I/O interface. The concept is also applicable in the context
of multi-core system-on-a-chip (SOC) design. In many situations the switching activity can
be reduced by using the sign-magnitude representation in place of the conventional two’s
complement representation. Switching activity can be reduced by judicious use of clock
gating, leading to considerable reduction in dynamic power dissipation. Instead of using static
CMOS logic style, one can use other logic styles such as pass-transistor and dynamic CMOS
logic styles or a suitable combination of pass-transistor and static CMOS logic styles to
minimize energy drawn from the supply.

Although the reduction in supply voltage and gate capacitances with device size
scaling has led to the reduction in dynamic power dissipation, the leakage power dissipation
has increased at an alarming rate because of the reduction of threshold voltage to maintain
performance. As the technology is scaling down from submicron to nanometer, the leakage
power is becoming a dominant component of total power dissipation. This has led to vigorous
research for the reduction of leakage power dissipation. Leakage reduction methodologies
can be broadly classified into two categories, depending on whether it reduces standby
leakage or runtime leakage. There are various standby leakage reduction techniques such as
input vector control (IVC), body bias control (BBC), multi-threshold CMOS (MTCMOS),
etc. and runtime leakage reduction techniques such as static dual threshold voltage CMOS
(DTCMOS) technique, adaptive body biasing, dynamic voltage scaling, etc.
 MOS Transistor
2.1 Introduction
✓ The base semiconductor material used for the fabrication of metal–
oxide–semiconductor (MOS) integrated circuits is silicon.
✓ Metal, oxide, and semiconductor form the basic structure of MOS
transistors.
✓ The three conducting materials are: metal, poly-silicon, and diffusion.
✓ Aluminum as metal and polycrystalline silicon or poly-silicon are used
for interconnecting different elements of a circuit.
✓ The insulating layer is made up of silicon dioxide (SiO2).
✓ Patterned layers of the conducting materials are created by a series of
photolithographic techniques and chemical processes involving
oxidation of silicon, diffusion of impurities into the silicon and
deposition, and etching of aluminum on the silicon to provide
interconnection.

2.2 Structure of MOS Transistors

Fig. 2.1 Structure of an MOS transistor

✓ The structure of an MOS transistor is shown in Fig. 2.1.On a lightly doped substrate
of silicon, two islands of diffusion regions of opposite polarity of that of the substrate
are created. These two regions are called source and drain, which are connected via
metal (or poly-silicon) to the other parts of the circuit.
✓ Between these two regions, a thin insulating layer of silicon dioxide is formed, and on
top of this a conducting material made of poly-silicon or metal called gate is
deposited.

2.2.1 nMOS and pMOS Transistors

✓ There are two possible alternatives. The substrate can be lightly doped by either a p-
type or an n-type material, leading to two different types of transistors.
✓ When the substrate is lightly doped by a p-type material, the two diffusion regions are
strongly doped by an n-type material. In this case, the transistor thus formed is called
an nMOS transistor.
 ✓ On the other hand, when the substrate is lightly doped by an ntype material, and the
diffusion regions are strongly doped by a p-type material, a pMOS transistor is
created.

2.2.2 nMOS Enhancement-Mode and Depletion-Mode Transistors

Fig. 2.2 a nMOS enhancement-mode transistor. b nMOS depletion-mode transistor

The region between the two diffusion islands under the oxide layer is called
the channel region. The operation of an MOS transistor is based on the controlled
flow of current between the source and drain through the channel region. In order to
make a useful device, there must be suitable means to establish some channel current
to flow and control it. There are two possible ways to achieve this, which have
resulted in enhancement- and depletion-mode transistors.
After fabrication, the structure of an enhancement-mode nMOS transistor
looks like Fig. 2.2a.
Enhancement-mode nMOS transistor:
✓ In this case, there is no conducting path in the channel region for the situation
Vgs = 0 V that is when no voltage is applied to the gate with respect to the
source.
✓ If the gate is connected to a suitable positive voltage with respect to the
source, then the electric field established between the gate and the substrate
gives rise to a charge inversion region in the substrate under the gate
insulation, and a conducting path is formed between the source and drain.
Current can flow between the source and drain through this conducting path.

Depletion-mode nMOS transistor:

✓ By implanting suitable impurities in the channel region during fabrication,
prior to depositing the insulation and the gate, the conducting path may also be
established in the channel region even under the condition Vgs = 0 V. This
situation is shown in Fig. 2.2b.
✓ Here, Source and drain are normally connected by a conducting path, which
can be removed by applying a suitable negative voltage to the gate. This is
known as the depletion mode of operation.

For example, consider the case when the substrate is lightly doped in p-type
and the channel region implanted with n-type of impurity. This leads to the formation
of an nMOS depletion-mode transistor. In both the cases, the current flow between the
source and drain can be controlled by varying the gate voltage and only one type of
charge carrier, that is, electron or hole takes part in the flow of current. That is the
reason why MOS devices are called unipolar devices, in contrast to bipolar junction
 transistors (BJTs), where both types of charge carriers take part in the flow of current.
Therefore, by using the MOS technology, four basic types of transistors can be
fabricated—nMOS enhancement type, nMOS depletion type, pMOS enhancement
type, and pMOS depletion type. Each type has its own pros and cons. It is also
possible to realize circuits by combining both nMOS and pMOS transistors, known as
Complementary MOS ( CMOS) technology. Commonly used symbols of the four
types of transistors are given in Fig. 2.3.

Fig. 2.3 a nMOS enhancement. b nMOS depletion. c pMOS enhancement. d pMOS depletion-mode transistors

2.3 FLUID MODEL

✓ The Fluid model is one such tool, which can be used to visualize the
behavior of charge-controlled devices such as MOS transistors, charge
coupled devices (CCDs), and bucket-brigade devices (BBDs).
The model is based on two simple ideas:
(a) Electrical Charge is considered as fluid, which can move from one place
to another depending on the difference in their level, of one from the other,
just like a fluid and
(b) Electrical Potentials can be mapped into the geometry of a container, in
which the fluid can move around.
Based on this idea, first, we shall consider the operation of a simple MOS capacitor followed
by the operation of an MOS transistor.
2.3.1 The MOS Capacitor

Fig. 2.4 a An MOS capacitor.b The fluid model

An MOS capacitor is realized by sandwiching a thin oxide layer between a metal or
poly- silicon plate on a silicon substrate of suitable type as shown in Fig 2.4a.
As we know, in case of parallel-plate capacitor, if a positive voltage is applied to one
of the plates, it induces a negative charge on the lower plate. Here, if a positive voltage is
applied to the metal or poly-silicon plate, it will repel the majority carriers of the p-type
substrate creating a depletion region. Gradually, minority carriers (electrons) are generated by
some physical process, such as heat or incident light, or it can be injected into this region.
These minority carriers will be accumulated underneath the MOS electrode, just like a
parallel-plate capacitor.
Based on the fluid model, the MOS electrode generates a pocket in the form of a
surface potential in the silicon substrate, which can be visualized as a container. The shape of
the container is defined by the potential along the silicon surface. The higher the potential,
the deeper is the container, and more charge can be stored in it. However, the minority
carriers present in that region create an inversion layer. This changes the surface potential;
increase in the quantity of charge decreases the positive surface potential under the MOS
electrode. In the presence of inversion charge, the surface potential is shown in Fig. 2.4b by
the solid line. The area between the solid line and the dashed line shows not only the presence
of charge but also the amount of charge. The capacity of the bucket is finite and depends on
the applied electrode voltage. Here, it is shown that the charge is sitting at the bottom of the
container just as a fluid would stay in a bucket. In practice, however, the minority carriers in
the inversion layer actually reside directly at the silicon surface. The surface of the fluid must
be level in the equilibrium condition. If it were not, electrons would move under the influence
of potential difference until a constant surface potential is established. From this simple
model, we may conclude that the amount of charge accumulated in an MOS capacitor is
proportional to the voltage applied between the plates and the area between the plates.
2.3.2 The MOS Transistor
By adding diffusion regions on either side of an MOS capacitor, an MOS transistor is
realized. One of the diffusion regions will form the source and the other one will form the
drain. The capacitor electrode acts as the gate. The cross-sectional view of an MOS transistor
is shown in Fig. 2.5a.
To start with, we may assume that the same voltage is applied to both the source and
drain terminals ( Vdb = Vsb) with respect to the substrate. This defines the potential of these
two regions. In the potential plot, the diffusion regions (where there is plentiful of charge
carriers) can be represented by very deep wells, which are filled with charge carriers up to the
levels of the potentials of the source and drain regions. The potential underneath the MOS
gate electrode determines whether these controlled with the help of the gate voltage. The
potential at the channel region is shown by the dotted lines of Fig. 2.5b. The dotted line 1
corresponding to Vgb = 0 is above the drain and source potentials. As the gate voltage is
gradually increased, more and more holes are repelled from the channel region, and the
potential at the channel region moves downward as shown by the dotted lines 2, 3, etc. In this
situation, the source and drain wells are effectively isolated from each other, and no charge
can move from one well to the other. A point is reached when the potential level at the gate
region is the same as that of the source and diffusion regions. At this point, the channel
region is completely devoid of holes. The gate voltage at which this happens is called the
threshold voltage ( Vt) of the MOS transistor. If the gate voltage is increased further, there is
an accumulation of electrons beneath the SiO2 layer in the channel region, forming an
inversion layer. As the gate voltage is increased further, the potential at the gate region
moves below the source and drain potentials as shown by the dotted lines 3 and 4 in Fig.
2.5b. As a consequence, the barrier between the two regions disappears and the charge from
the source and drain regions spills underneath the gate electrode leading to a uniform surface
potential in the entire region. By varying the gate voltage, the thickness of the inversion layer
can be controlled, which in turn will control the conductivity of the channel as visualized in
Fig. 2.5b. Under the control of the gate voltage, the region under it acts as a movable barrier
that controls the flow of charge between the source and drain areas.
 Fig. 2.5 a An MOS transistor.b The fluid model
❖ Active, linear or unsaturated and Saturation Region
When the source and drain are biased to different potentials ( Vdb ˃ Vsb), there will be a
difference in the potential levels. Let us consider two different situations. In the first case, the
drain voltage is greater than the source voltage by some fixed value, and the gate voltage Vgb
is gradually increased from 0 V. Figure 2.6 shows different situations. Initially, for Vgb = 0
V, the potential level in the channel region is above the potential level of either of the source
and drain regions, and the source and drain are isolated. Now, if the gated voltage is
gradually increased, first, the gate region potential reaches the potential of the source region.
Charge starts moving from the source to the drain as the gate voltage is slightly increased.
The rate of flow of charge moving from the source to the drain region, represented by the
slope of the interface potential in the channel region, keeps on increasing until the gate region
potential level becomes the same as that of the drain potential level. In this situation, the
device is said to be operating in an active, linear, or unsaturated region. If the gate voltage is
increased further, the width of the channel between the source and drain keeps on increasing,
leading to a gradual increase in the drain current.

Fig. 2.6 The fluid model of an MOS transistor

Let us consider another case when the gate voltage is held at a fixed value for a heavily
turned-on channel. To start with, the drain voltage is the same as that of the source voltage,
and it is gradually increased. Figure 2.6a shows the case when the source and drain voltages
are equal. Although the path exists for the flow of charges, there will be no flow because of
the equilibrium condition due to the same level. In Fig. 2.6b, a small voltage difference is
maintained by externally applied voltage level. There will be continuous flow of charge
resulting in drain current. With the increase in voltage difference between the source and
drain, the difference in the fluid level increases, and the layer becomes more and more thin,
signifying faster movement of charges. With the increasing drain potential, the amount of
charge flowing from the source to drain per unit time increases. In this situation, the device is
said to be operating in an active, linear, or unsaturated region. However, there is a limit to it.
It attains a maximum value, when the drain potential Vdb = ( Vgb−Vt). Further increase in
drain voltage does not lead to any change in the rate of charge flow. The device is said to be
in the saturation region. In this condition, the drain current becomes independent of the drain
voltage, and it is fully determined by the gate potential.
❖ MOS Characteristics

Fig. 2.7 (a) Drain Current (Ids) Vs Gate Voltage (Vgs) (b) Voltage-Current
Characteristic ( Vds Vs Ids)
To summarize this section, we can say that an MOS transistor acts as a voltage
controlled device. The device first conducts when the effective gate voltage ( Vgb−Vt) is
more than the source voltage. The conduction characteristic is represented in Fig. 2.7a. On
the other hand, as the drain voltage is increased with respect to the source, the current
increases until Vdb = ( Vgb−Vt). For drain voltage Vdb ˃ ( Vgb−Vt), the channel becomes
pinched off, and there is no further increase in current. A plot of the drain current with
respect to the drain voltage for different gate voltages is shown in Fig. 2.7b.
2.4 Modes of Operation of MOS Transistors

Fig. 2.8 a Accumulation mode, b depletion mode, and c inversion mode of an MOS
transistor
Accumulation Mode: When the gate voltage is very small and much less than the threshold
voltage. Fig. 2.8a shows the distribution of the mobile holes in a p-type substrate. In this
condition, the device is said to be in the accumulation mode
Depletion Mode: As the gate voltage is increased, the holes are repelled from the SiO2–
substrate interface and a depletion region is created under the gate when the gate voltage is
equal to the threshold voltage. In this condition, the device is said to be in depletion mode as
shown in Fig. 2.8b.
Inversion Mode: As the gate voltage is increased further above the threshold voltage,
electrons are attracted to the region under the gate creating a conducting layer in the p
substrate as shown in Fig. 2.8c. The transistor is now said to be in inversion mode.
2.5 Electrical Characteristics of MOS Transistor
❖ Drain Source Current Expression for nMOS Enhancement Type Transistor

Fig. 2.9 Structural view of an MOS transistor

The fluid model, presented in the previous section, gives us some basic understanding of the
operation of an MOS transistor. We have seen that the whole concept of the MOS transistor
is based on the use of the gate voltage to induce charge (inversion layer) in the channel region
between the source and the drain. Application of the source-to-drain voltage Vds causes this
charge to flow through the channel from the source to drain resulting in source-to-drain
current Ids. The Ids depends on two variable parameters—the gate-to-source voltage Vgs and
the drain-to-source voltage Vds. The operation of an MOS transistor can be divided into the
following three regions:
✓ Cutoff region: This is essentially the accumulation mode, when there is no effective
flow of current between the source and drain.
✓ Non-saturated region: This is the active, linear, or weak inversion mode, when the
drain current is dependent on both the gate and the drain voltages.
✓ Saturated region: This is the strong inversion mode, when the drain current is
independent of the drain-to-source voltage but depends on the gate voltage.

In this section, we consider an nMOS enhancement-type transistor and establish its

electrical characteristics. The structural view of the MOS transistor, as shown in Fig. 2.9,
shows the three important parameters of MOS transistors, the channel length L, the
channel width W, and the dielectric thickness D.
The expression for the drain current is given by
Ids= Charge Induced in the Channel (Qc) / Electron Transit Time (tn) (2.1)

With a voltage V applied across the plates, the charge is given by Q = CV, where C is the
capacitance. The basic formula for parallel-plate capacitor is C=εA/D, where ε is the
permittivity of the insulator in units of F/cm. The value of ε depends on the material used to
separate the plates. In this case, it is silicon dioxide (SiO2).For SiO2, εox = 3.9ε0, where ε0 is
the permittivity of the free space.
∈ 𝑊𝐿
For MOS Transistor, 𝐺𝑎𝑡𝑒 𝐶𝑎𝑝𝑎𝑐𝑖𝑡𝑎𝑛𝑐𝑒, 𝐶𝐺 = 𝑜𝑥𝐷 (2.2)
For the MOS transistor, Qc= CG. Veff (2.3)
Where Veff is the Effective gate voltage
Transit Time, tn = Length of the Channel (L) / Velocity of Electron (τn) (2.4)
The Velocity, τn = μn. Eds, where μn is the Mobility of Electron (Typical value
of μn=650cm2/V at Room temperature) and Eds is the Drain to Source electric field due
to the voltage Vds applied between the drain and source, Eds= Vds/ L.

𝜇𝑛 𝑉𝑑𝑠 𝐿2
𝜏𝑛 = and 𝑡𝑛 = 𝜇 (2.5)
𝐿 𝑛 𝑉𝑑𝑠
𝑊𝐿∈𝑜𝑥
𝑄𝑐 = 𝑉𝑒𝑓𝑓 (2.6)
𝐷

For Non-saturated Region

When the gate voltage is above the threshold voltage and there is a voltage
difference of Vds across the channel, the effective gate voltage is
Veff = (Vgs-Vt –Vds/2) (2.7)
Substituting equation (2.7) in Equation (2.6), we get

𝑊𝐿∈ 𝑉
𝑄𝑐 = 𝐷 𝑜𝑥 [(𝑉𝑔𝑠 − 𝑉𝑡 ) − 2𝑑𝑠 ] (2.8)
Substituting the value of tn and Qc in equation (2.1), we get

𝑊𝜇𝑛 ∈𝑜𝑥 𝑉𝑑𝑠

𝐼𝑑𝑠 = [(𝑉𝑔𝑠 − 𝑉𝑡 ) − ] 𝑉𝑑𝑠 (2.9)
𝐿𝐷 2

𝐾𝑊 𝑉𝑑𝑠 2
𝐼𝑑𝑠 = [(𝑉𝑔𝑠 − 𝑉𝑡 )𝑉𝑑𝑠 − ] for Vgs ≥ Vt and Vds< Vgs-Vt (2.10)
𝐿 2
𝜇𝑛 ∈𝑜𝑥
Where 𝐾 = 𝐷
For Saturated Region
2 2
𝑊𝜇 ∈
𝑛 𝑜𝑥 (𝑉𝑔𝑠 −𝑉𝑡 ) 𝑊 (𝑉𝑔𝑠 −𝑉𝑡 )
𝐼𝑑𝑠 = 𝐷𝐿 =𝐾𝐿 for Vgs ≥ Vt and Vds ≥ Vgs-Vt (2.11)
2 2
For Cutoff Region
Ids= 0 for Vgs< Vt (2.12)
✓ Threshold Voltage
𝑉𝑡 = 𝑉𝑡𝑜 + 𝛾√|−2𝜑𝑏 + 𝑉𝑠𝑏 | − √|2𝜑𝑏 | =0.4 + 0.82√0.7 + 𝑉𝑠𝑏 − √0.7
✓ Transistor Transconductance (gm)
𝛿𝐼𝑑𝑠 𝜇𝑛 ∈𝑖𝑛𝑠 ∈𝑜 𝑊
𝑔𝑚 = /𝑉𝑑𝑠=𝐶𝑜𝑛𝑠𝑡𝑎𝑛𝑡 = (𝑉 − 𝑉𝑡 )
𝛿𝑉𝑔𝑠 𝐷 𝐿 𝑔𝑠
✓ Figure of Merit
𝑔𝑚 𝜇𝑛 1
𝑊𝑜 = = 2 (𝑉𝑔𝑠 − 𝑉𝑡 ) =
𝐶𝑔 𝐿 𝑡𝑠𝑑
✓ Body Effect
✓ Channel-Length Modulation
2.6 MOS Transistor as a Switch
❖ nMOS Pass Transistor

✓ nMOS transistor when used as a switch is OFF when Vgs = 0 V and

ON when Vgs = Vdd.
✓ Vin=0V,Vout=0V
✓ Vin=5V,Vout=Vdd-Vtn
❖ pMOS Pass Transistor

✓ PMOS transistor when used as a switch is ON when Vgs = 0 V and OFF when Vgs =
Vdd.
✓ Vin=0V,Vout=|Vtp|
✓ Vin=+5V,Vout= +5V
❖ Transmission Gate

✓ One pMOS and one nMOS transistor can be connected in parallel with
complementary inputs at their gates.
✓ This is known as Transmission Gate
✓ Both the devices are OFF when “0” and “1” logic levels are applied to the
gates of the nMOS and pMOS transistors, respectively.
o Vgsn=0V and Vgsp=+5V, The Switch is OFF
✓ Both the devices are ON when a “1” and a “0” prior to the logic levels are
applied to the gates of the nMOS and pMOS transistors, respectively.
o Vgsn=+5V and Vgsp=0V, The Switch is ON
o Vin=0, Vout=0V and Vin=+5V, Vout=+5V
❖ Transmission gate Case I: Large Capacitive Load

(a) Output node charges from low-to-high level

(b)The output voltage changing with time for different transitions.

(c)The drain currents through the two transistors as a function of the output
voltage.
(d)The equivalent resistances as a function of the output voltage

1. OUTPUT Node Changes from LOW-to-HIGH Level

Region I-Both nMOS and pMOS transistors are in SATURATION, Vout < |Vtp |
𝑊𝑛
𝐼𝑑𝑠𝑛 = 𝐾𝑛 (𝑉 − 𝑉𝑜𝑢𝑡 − 𝑉𝑡𝑛 )2
2𝐿𝑛 𝑑𝑑
𝑊𝑝 2
𝐼𝑑𝑠𝑝 = 𝐾𝑝 (𝑉𝑑𝑑 − |𝑉𝑡𝑝 |)
2𝐿𝑝
𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 2𝐿𝑛 (𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 )
𝑅𝑒𝑞𝑛 = =
𝐼𝑑𝑠𝑛 𝐾𝑛 𝑊𝑛 (𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 − 𝑉𝑡𝑛 )2
𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 2𝐿𝑝 (𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 )
𝑅𝑒𝑞𝑝 = =
𝐼𝑑𝑠𝑝 𝐾𝑝 𝑊𝑝 (𝑉 − |𝑉 |)2
𝑑𝑑 𝑡𝑝

Region II-nMOS is in Saturation and pMOS in Linear, |Vtp| < Vout < Vdd – Vtn

𝑊𝑝 (𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 )2
𝐼𝑑𝑠𝑝 = 𝐾𝑝 [(𝑉𝑑𝑑 − |𝑉𝑡𝑝 |)(𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 ) − ]
𝐿𝑝 2
2𝐿𝑝 1
𝑅𝑒𝑞𝑝 =
𝐾𝑝 𝑊𝑝 [2(𝑉𝑑𝑑 − |𝑉𝑡𝑝 |) − (𝑉𝑑𝑑 − 𝑉𝑜𝑢𝑡 )]

Region III-nMOS is in Cutoff and pMOS in linear, Vout > Vdd − Vtn
2. OUTPUT Node Changes from HIGH-to-LOW Level
 (a) Output node charges from high-to-low level
(b)The output voltage changing with time for different transitions.

(c) The drain currents through the two transistors as a function of the output
voltage.
(d) The equivalent resistances as a function of the output voltage

Region I: Both nMOS and pMOS are in saturation for Vout < |Vtp| .
Region II: nMOS is in the linear region, and pMOS is in saturation for (Vdd−Vtp|)< Vout
<Vtn .
Region III: nMOS is in the linear region, and pMOS is cutoff for Vout<(Vdd -|Vtn|).

❖ Transmission gate Case II: Small Capacitive Load

(a) Charging a small capacitor (b) Variation of the output currents with the input
voltage
(c) Variation of the equivalent resistances with the input voltage
✓ Region I: nMOS is in the linear region, pMOS is cutoff for Vin < |Vtp|
✓ Region II: nMOS is in the linear region, pMOS linear for Vtp < Vin < (Vdd − |Vtn|).
✓ Region III: nMOS is cutoff, pMOS is in the linear region for Vin > (Vdd-|Vtn|).