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Developing Accelerators Using Vitis and PYNQ On AWS F1

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29 views

Developing Accelerators Using Vitis and PYNQ On AWS F1

Uploaded by

TaHashmi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Developing Accelerators using Vitis and PYNQ on AWS F1

Presenters: Cathal McCabe and Mario Ruiz, Xilinx University Program, EMEA
Introduction
Xilinx is the inventor of the FPGA, programmable SoCs, and now, the ACAP. Our highly
flexible programmable silicon, enabled by a suite of advanced software and tools, drives rapid innovation
across a wide span of industries and technologies.
With the decline of Moore’s law, HPC systems need to include specialised heterogeneous accelerators to
continue performance scaling. FPGAs are emerging as an ideal target for a range of HPC applications.

Tutorial
This tutorial will introduce the Xilinx Vitis development environment for developing FPGA accelerators.
Vitis environment enables the user to easily and productively develop accelerated algorithms and then
efficiently implement and deploy them onto heterogeneous CPU-FPGA-ACAP systems. Vitis supports
OpenCL, C and C++. RTL design flows are also supported for experienced hardware developers. Each of
these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source
accelerated libraries. We will also introduce the PYNQ project and show how PYNQ makes the use of Xilinx
accelerator much easier.

The latest available cloud and local hardware will be covered including AWS F1, and the range of Alveo
accelerator boards. Topics to be covered:

• Xilinx Vitis development framework, design flows, and use cases


• AWS and Alveo boards for FPGA acceleration
• An introduction to PYNQ
• Demonstration and hands-on-experience
• Vitis development flow
• Developing, profiling and optimizing applications for FPGA
• Using Xilinx accelerator in the cloud

Pre-requisites
Some basic FPGA awareness would be an advantage, but is not required, although participants should
have some knowledge of parallel processing concepts and/or parallel hardware.
Most of the FPGA design work will be carried out in C++. Intermediate C++ programming experience is
required.
XUP will provide remote access to AWS F1 cloud instances which will be enabled with Xilinx tools and
devices. Attendees must have their own laptop with reasonable screen size to effectively use
the required software. (Tablet, and Netbook type devices are not suitable.)
Internet connection of suitable quality to attend the video conferencing sessions, participate in
discussions, and connect to clouds instances is also required.

© Copyright 2021 Xilinx University Program


Dates, times and Schedule
09:15 – 18:00 CET 30 June 2021. This will be a virtual tutorial and will be fully online (Zoom).

Time (CET)
Presentation Session 09:15 – 12:00
Q&A 12:00 – 12:30
Connect to AWS F1 12:30 – 13:00
Lunch Break 13:00 – 14:00
Hands-on Session 14:00 – 18:00

Applications
Please apply online by 23 June 2021. The tutorial is open to Undergraduate, Master’s, PhD, post-doc,
professor and researchers.
Places are limited. You will receive confirmation of your place shortly after the closing date if your
application has been successful. If the tutorial is oversubscribed, a limit on places per institution may be
applied.

Apply here: https://www.xilinx.com/support/university/workshops/emea-registration-form.html

Contact
Please contact [email protected] for any questions related to this tutorial.

© Copyright 2021 Xilinx

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