RM08001 JLinkUSBProtocol
RM08001 JLinkUSBProtocol
Document RM08001-R7
Date: October 8, 2010
www.segger.com
2 CHAPTER
Disclaimer
Specifications written in this document are believed to be accurate, but are not guar-
anteed to be entirely free of error. The information in this manual is subject to
change for functional or performance improvements without notice. Please make sure
your manual is the latest edition. While the information herein is assumed to be
accurate, SEGGER MICROCONTROLLER GmbH & Co. KG (the manufacturer) assumes
no responsibility for any errors or omissions. The manufacturer makes and you
receive no warranties or conditions, express, implied, statutory or in any communica-
tion with you. The manufacturer specifically disclaims any implied warranty of mer-
chantability or fitness for a particular purpose.
Copyright notice
You may not extract portions of this manual or modify the PDF file in any way without
the prior written permission of the manufacturer. The software described in this doc-
ument is furnished under a license and may only be used or copied in accordance
with the terms of such a license.
© 2010 SEGGER Microcontroller GmbH & Co. KG, Hilden / Germany
Trademarks
Names mentioned in this manual may be trademarks of their respective companies.
Brand and product names are trademarks or registered trademarks of their respec-
tive holders.
Contact address
SEGGER Microcontroller GmbH & Co. KG
In den Weiden 11
D-40721 Hilden
Germany
Tel.+49 2103-2878-0
Fax.+49 2103-2878-28
Email: [email protected]
Internet: http://www.segger.com
Document revisions
For further information on topics or routines not yet specified, please contact us.
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Assumptions
This document assumes that you already have a solid knowledge of the following:
• The software tools used for building your application (assembler, linker, C com-
piler)
• The target processor.
How to use this manual
This manual explains all the functions and macros that the product offers. It assumes
you have a working knowledge of the C language. Knowledge of assembly program-
ming is not required.
Typographic conventions for syntax
This manual uses the following typographic conventions:
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Table of Contents
1 Introduction ......................................................................................................................9
1.1 How to use this manual ............................................................................ 10
1.2 Purpose of this document ......................................................................... 10
1.3 Features of J-Link ARM ............................................................................. 10
2 Licensing........................................................................................................................11
2.1 License terms.......................................................................................... 12
4 USB................................................................................................................................19
4.1 USB communication overview.................................................................... 20
4.2 USB transactions ..................................................................................... 21
4.3 Using USBLib .......................................................................................... 22
5 Emulator protocol...........................................................................................................23
5.1 Communication protocol overview.............................................................. 24
5.2 Protocol commands.................................................................................. 25
5.3 Get system information functions............................................................... 27
5.4 Get state information functions.................................................................. 35
5.5 JTAG & Hardware functions ....................................................................... 39
5.6 Target functions ...................................................................................... 57
5.7 Configuration functions............................................................................. 66
6 Glossary.........................................................................................................................69
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Chapter 1
Introduction
This chapter describes the purpose of this manual and the J-Link ARM emulator which
uses the J-Link USB Protocol.
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Chapter 2
Licensing
This chapter gives information about the licensing terms under which this document
is published.
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Chapter 3
Background information
This chapter provides information required to understand parameters for certain USB
commands when working with the J-Link emulator.
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TRST
TMS
TMS
TCK
TCK
TRST
TMS
TCK
TDI TDO
JTAG
3.1.1 IRPre
The IRPre value is the total number of bits in the instruction registers of the devices
before the DUT counted from nearest device to TDO. The position can usually be seen
in the schematic; the IR len can be found in the manual supplied by the manufactur-
ers of the other devices.
ARM7 and ARM9 have an IR len of four.
For systems with just a single device, IRPre is 0.
For an example using the IRpre value please refer to the paragraph Scan chain exam-
ple on page 15.
3.1.2 DevicePos
The DevicePos value of the DUT is the amount of devices in the scan chain before the
DUT, counted from nearest device to TDO.
For systems with just a single device, DevicePos is 0.
For an example using the DevicePos value please refer to the paragraph Scan chain
example on page 15.
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All three JTAG data buffers are organized the same way:
Bit n of the bit stream is stored in byte n/8, bit n%8. This means the first byte is sent
first, least significant bit (lsb) first.
The same thing is true for data received: The first bit received is the lsb of byte 0.
Size of buffers
All buffers are big enough to hold 2 KByte of data.
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Chapter 4
USB
This chapter explains the USB communication and specifics which have to be taken
care of when using USB communication under Windows and other operating systems.
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4.1.3 Endianess
All data units larger than a single byte are transferred little endian, meaning least
significant bytes are transferred first.
U16 Example
U16 data to send:
0xCDEF
Data sent via USB:
EF CD
U32 Example
U32 data to send:
0x12345678
Data sent via USB:
78 56 34 12
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4.2.1 Timeout
J-Link uses a 5 second timeout for all USB operations.
This means that every command needs to be completed within 5 seconds. If 5 sec-
onds is too short (for example for a long JTAG sequence at a low speed) the JTAG
sequence needs to be split into 2 or more shorter sequences.
4.2.4 IN-transaction
In an IN-transaction, the host requests data from the emulator. This is a is a more
tricky process.
The maximum size of one transaction is 0x8000 bytes.
A transaction is followed by a 0-byte packet if the transaction size is a multiple of 64
bytes, but not the maximum packet size.
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Chapter 5
Emulator protocol
This chapter explains the communication protocol used by the J-Link emulator to
communicate with the host.
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5.3.1 EMU_CMD_VERSION
Description
Retrieves the length and content of the firmware version string of the emulator.
Command
Response
Additional information
This is typically the first command sent.
Sample communication
Retrieve firmware string command.
H->E: 01
Returns the firmware string length.
H<-E: 70
Returns the firmware string.
H<-E: 4A 2D 4C 69 6E 6B 20 63 6F 6D 70 69 6C 65 64 20 J-Link compiled
44 65 63 20 30 33 20 32 30 30 37 20 31 37 3A 31 Dec 03 2007 17:1
35 3A 33 31 20 41 52 4D 20 52 65 76 2E 35 00 00 5:31 ARM Rev.5..
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
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5.3.2 EMU_CMD_GET_SPEEDS
Description
Retrieves the base freq. and the min. divider of the emulator CPU.
Command
Response
Sample communication
Retrieve base freq. and min. divider of emulator CPU.
H->E: C0
Returns 48MHz base freq. with min. divider of 4.
H<-E: 00 6C DC 02 04 00
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5.3.3 EMU_CMD_GET_MAX_MEM_BLOCK
Description
Retrieves the maximum memory blocksize.
Command
Response
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5.3.4 EMU_CMD_GET_CAPS
Description
Retrieves capabilities of the emulator.
Command
Response
Additional information
The capability flags used are described in the table below:
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Sample communication
Retrieve emulator capabilities.
H->E: E8
Returns all capabilities except trace commands.
H<-E: BF 7F FF 3B
5.3.5 EMU_CMD_GET_CAPS_EX
Description
Retrieves extended capabilities of the emulator.
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Command
Response
Additional information
The capability flags used are described in the table below:
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Sample communication
Retrieve emulator capabilities.
H->E: ED
Returns all capabilities except trace commands.
H<-E: BF 7F FF BB 01 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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5.3.6 EMU_CMD_GET_HW_VERSION
Description
Retrieves the product hardware version of the emulator.
Command
Response
Additional information
The product hardware version is returned in the following format.
TTMMmmrr
This stands for:
TT: Hardware type
MM: Major version
mm: Minor version
rr: Revision
Example: The version 0052000 stands for a J-Link Version 5.2 .
If the capability EMU_CMD_GET_HW_VERSION is not enabled Version is always 0x00 .
Sample communication
Retrieve hardware version command.
H->E: F0
Returns the hardware version 0060000 which equals a J-Link V6.
H<-E: 60 EA 00 00
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5.4.1 EMU_CMD_GET_STATE
Description
Retrieves the voltage of the target and the JTAG pin states for TCK, TDI, TDO, TMS,
TRES and TRST.
Command
Response
Sample communication
Retrieve state information command.
H->E: 07
Returns 3.267V; TCK, TRES and TRST are high; TDI, TDO, TMS are low.
H<-E: C3 0C 01 00 00 00 01 01
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5.4.2 EMU_CMD_GET_HW_INFO
Description
Retrieves information about the KS power of the emulator.
Command
Response
Additional information
The flags that can be used as Mask are described in the table below:
The amount of U32 data returned by this command depends on how many flags you
haved used in your Mask. Undefined flags return 0xFFFFFFFF.
Sample communication
Retrieve hadrware information about KS power status and target consumption.
H->E: C1 05 00 00 00
Returns KS power is on and the target consumes 12mA.
H<-E: 01 00 00 00 0C 00 00 00
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5.4.3 EMU_CMD_GET_COUNTERS
Description
Retrieves counter values of how long a target is connected and how many times a
target was connected / disconnected.
Command
Response
Additional information
The flags that can be used as Mask are described in the table below:
The amount of U32 data returned by this command depends on how many flags you
have used in your Mask. Undefined flags return 0xFFFFFFFF.
Sample communication
Requesting value of the power change counter.
H->E: C2 02 00 00 00
Returns 5 power changes.
H<-E: 05 00 00 00
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5.4.4 EMU_CMD_MEASURE_RTCK_REACT
Description
Measures the RTCK reaction time of the target device.
Command
Response
Sample communication
Measure RTCK reaction time command.
H->E: F6
Returns O.K., Min. 0ns, Max. 126ns and Average 25ns reaction time.
H<-E: 00 00 00 00 00 00 00 00 7E 00 00 00 19 00 00 00
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5.5.1 EMU_CMD_RESET_TRST
Description
Resets TRST.
Command
Response
-
Additional information
Activates TRST and releases it after 2ms.
Sample communication
Reset TRST command.
H->E: 02
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5.5.2 EMU_CMD_SET_SPEED
Description
Sets the JTAG speed.
Command
Response
-
Sample communication
Set speed to adaptive clocking command.
H->E: 05 FF FF
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5.5.3 EMU_CMD_SELECT_IF
Description
Select a target interface or retrieves the previously selected interface.
Command
Response
Additional information
The interfaces that can be selected (if available) are described in the table below:
Interface # Define
0 TIF_JTAG
1 TIF_SWD
Table 5.30: EMU_CMD_SELECT_IF interface overview
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5.5.4 EMU_CMD_SET_KS_POWER
Description
Sets KS power on JTAG pin 19 to on or off temporarily.
Command
Response
-
Additional information
JTAG pin 19 may provide 5V power to a target system. For details, please refer to J-
Link User manual.
Sample communication
Set KS power to on command.
H->E: 08 01
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5.5.5 EMU_CMD_HW_CLOCK
Description
Generates one clock and retrieves data from TDI.
Command
Response
Additional information
This command generates one clock and returns the value of TDI on falling edge of
clock.
Default value of clock ping (TCK) is high. So this function generates a low pulse, fol-
lowed by a high pulse on TCK.
Sample communication
Generate one clock.
H->E: C8
Returns TDI data.
H<-E: 00
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5.5.6 EMU_CMD_HW_TMS0
Description
Clears TMS signal.
Command
Response
-
Sample communication
Clear TMS command.
H->E: C9
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5.5.7 EMU_CMD_HW_TMS1
Description
Sets TMS signal.
Command
Response
-
Sample communication
Set TMS command.
H->E: CA
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5.5.8 EMU_CMD_HW_DATA0
Description
Clears TDI signal.
Command
Response
-
Sample communication
Clear TDI command.
H->E: CB
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5.5.9 EMU_CMD_HW_DATA1
Description
Sets TDI signal.
Command
Response
-
Sample communication
Set TDI command.
H->E: CC
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5.5.10 EMU_CMD_HW_JTAG
Description
Handles the JTAG connection. It receives data for TDI and TMS and sends TDO data
back.
Command
Response
Additional information
This command is obsolete. Please use EMU_CMD_HW_JTAG3 on page 50.
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5.5.11 EMU_CMD_HW_JTAG2
Description
Handles the JTAG connection. It receives data for TDI and TMS and sends TDO data
back.
Command
Response
Additional information
This command is obsolete for J-Links with hardware version 5 and above. Please use
EMU_CMD_HW_JTAG3 on page 50.
The hardware version can be retrieved using the command
EMU_CMD_GET_HW_VERSION on page 34.
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5.5.12 EMU_CMD_HW_JTAG3
Description
Handles the JTAG connection. If used with JTAG interface it receives data for TDI and
TMS and sends TDO data back. If used with SWD interface it receives data for SWDIO
(in) and DIR and sends SWDIO (out) data back.
Command (JTAG interface)
Additional information
How the JTAG/SWD sequence is generated is beyond the scope of this manual.
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This command is available for J-Links with hardware version 5 and above only.
SWD support is available for J-Links with hardware version 6 and above only.
The hardware version can be retrieved using the command
EMU_CMD_GET_HW_VERSION on page 34.
Sample communication
Output command and JTAG TDI, TMS data to halt ARM7 CPU.
H->E: CF 00 48 00 86 E3 71 C0 01 00 00 00 0C 20 00 18 02 00 00 00 00 00
Returns TDO data.
H<-E: 20 00 08 00 48 00 00 00 00
Returns O.K.
H<-E: 00
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5.5.13 EMU_CMD_HW_JTAG_WRITE
Description
Handles the JTAG connection. If used with JTAG interface it receives data for TDI and
TMS. No TDO data is sent back. If used with SWD interface it receives data for
SWDIO (in) and DIR . No SWDIO (out) data is sent back. The status of the transmis-
sion is saved in a stick error flag. This flag can be requested via the
EMU_CMD_HW_JTAG_GET_RESULT command. For more information about the
EMU_CMD_HW_JTAG_GET_RESULT command, please refer to
EMU_CMD_HW_JTAG_GET_RESULT on page 53
Command (JTAG interface)
Additional information
How the JTAG/SWD sequence is generated is beyond the scope of this manual.
This command is available for J-Links with hardware version 6 and above only.
The hardware version can be retrieved using the command
EMU_CMD_GET_HW_VERSION on page 34.
Sample communication
Output command and JTAG TDI, TMS data to halt ARM7 CPU.
H->E: CF 00 48 00 86 E3 71 C0 01 00 00 00 0C 20 00 18 02 00 00 00 00 00
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5.5.14 EMU_CMD_HW_JTAG_GET_RESULT
Description
Requests the sticky error bit from the emulator. This bit is set if a
EMU_CMD_HW_JTAG_WRITE command failed. After the
EMU_CMD_HW_JTAG_GET_RESULT command has been performed, the sticky error
bit is cleared.
Command
Response
Sample communication
Output command to get the sticky error bit:
H->E: D6
Returns O.K.
E->H: 00
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5.5.15 EMU_CMD_HW_TRST0
Description
Activates TRST signal.
Command
Response
-
Sample communication
Activate TRST command.
H->E: DE
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5.5.16 EMU_CMD_HW_TRST1
Description
Deactivates TRST signal.
Command
Response
-
Sample communication
Deactivate TRST command.
H->E: DF
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5.5.17 EMU_CMD_WRITE_DCC
Description
Writes to the CPU through JTAG using DCC.
Command
Response
Additional information
Explanation of DCC data generation is beyond the scope of this document.
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5.6.1 EMU_CMD_RESET_TARGET
Description
Resets the target via hardware reset.
Communication
Response
-
Additional information
Activates the target RESET line and releases it after 2ms.
Sample communication
Reset target command.
H->E: 03
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5.6.2 EMU_CMD_HW_RELEASE_RESET_STOP_EX
Description
Resets the CPU and halts as soon as possible. Means as soon as a criteria is matched.
Command
Response
Additional information
In order to halt an ARM7 or ARM9 CPU as soon as possible the emulator can decide if
the CPU is halted by checking for a criteria. This eliminates the USB latency a deci-
sion by the host PC would cause. What happens is that RESET is pulled high and the
emulator tries to halt the CPU with a halting sequence as soon as possible for Num-
Reps tries. To check if halting the CPU was successful the emulator checks for a crite-
ria. A pseudo code could look like the following code:
U16 i = 0;
ResetHigh();
do {
i++;
SendSequence();
} while(((Data & CriteriaMask) != CriteriaData) && (i <= NumReps))
This command is emplemented for ARM7 and ARM9 cores only.
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5.6.3 EMU_CMD_HW_RELEASE_RESET_STOP_TIMED
Description
Resets the CPU and halts as soon as its possible or the timeout expires.
Command
Response
Additional information
For further information please refer to EMU_CMD_HW_RELEASE_RESET_STOP_EX on
page 58. The only difference of this command is that the abort criteria is a timeout
instead of a maximum repeat count.
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5.6.4 EMU_CMD_HW_RESET0
Description
Activates target reset.
Command
Response
-
Sample communication
Activate target reset command.
H->E: DC
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5.6.5 EMU_CMD_HW_RESET1
Description
Deactivates target reset.
Command
Response
-
Sample communication
Deactivate target reset command.
H->E: DD
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5.6.6 EMU_CMD_GET_CPU_CAPS
Description
Retrieves the capabilities of the target CPU.
Command
Response
Additional information
The capability flags used are described in the table below:
Sample communication
Requesting the CPU capabilities.
H->E: E9 07 00 00 00
Returns no capabilites.
H<-E: 01 00 00 00
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5.6.7 EMU_CMD_EXEC_CPU_CMD
Description
Executes functions supported by the CPU.
Command
Response
Additional information
The list below gives an overview about the available CPU commands.
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5.6.8 EMU_CMD_WRITE_MEM_ARM79
Description
Writes to target memory on ARM 7/9 targets.
Command
Response
Sample communication
Writing 0xAB to address 0x12345678.
H->E: F7 04 01 00 00 00 00 00 00 01 78 56 34 12 01 00 00 00 AB
Returns O.K.
H<-E: 00
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5.6.9 EMU_CMD_READ_MEM_ARM79
Description
Reads from target memory on ARM 7/9 targets.
Command
Response
Sample communication
Retrieve 1 byte from address 0x10 command.
H->E: F8 04 01 00 00 00 00 00 00 01 10 00 00 00 01 00 00 00
Returns O.K.
H<-E: 00
Returns data read from address 0x10.
H<-E: 18
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5.7.1 EMU_CMD_READ_CONFIG
Description
Reads the emulator configuration from the J-Link.
Command
Response
Sample communication
Retrieve emulator configuration command.
H->E: F2
Returns emulator configuration.
H<-E: 00 02 FF FF 01 00 00 00 FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
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5.7.2 EMU_CMD_WRITE_CONFIG
Description
Writes the emulator configuration to the J-Link.
Command
Response
-
Sample communication
Send emulator configuration command.
H->E: F3
Send emulator configuration.
H->E: 00 02 FF FF 01 00 00 00 FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
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Chapter 6
Glossary
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Adaptive clocking
A technique in which a clock signal is sent out by J-Link / J-Trace. J-Link / J-Trace
waits for the returned clock before generating the next clock pulse. The technique
allows the J-Link / J-Trace interface unit to adapt to differing signal drive capabilities
and differing cable lengths.
Application Program Interface
A specification of a set of procedures, functions, data structures, and constants that
are used to interface two or more software components together.
Big-endian
Memory organization where the least significant byte of a word is at a higher address
than the most significant byte. See Little-endian.
Device Under Test
The device in the scan chain debugged at the moment.
DUT
See Device Under Test.
EmbeddedICE
The additional hardware provided by debuggable ARM processors to aid debugging.
Halfword
A 16-bit unit of information. Contents are taken as being an unsigned integer
unless otherwise stated.
Host
A computer which provides data and other services to another computer. Especially, a
computer providing debugging services to a target being debugged.
ICache
Instruction cache.
ICE Extension Unit
A hardware extension to the EmbeddedICE logic that provides more breakpoint units.
ID
Identifier.
IEEE 1149.1
The IEEE Standard which defines TAP. Commonly (but incorrectly) referred to as
JTAG.
In-Circuit Emulator (ICE)
A device enabling access to and modification of the signals of a circuit while that cir-
cuit is operating.
Instruction Register
When referring to a TAP controller, a register that controls the operation of the TAP.
IR
See Instruction Register.
Joint Test Action Group (JTAG)
The name of the standards group which created the IEEE 1149.1 specification.
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Little-endian
Memory organization where the least significant byte of a word is at a lower address
than the most significant byte. See also Big-endian.
Memory coherency
A memory is coherent if the value read by a data read or instruction fetch is the
value that was most recently written to that location. Obtaining memory coherency is
difficult when there are multiple possible physical locations that are involved, such as
a system that has main memory, a write buffer, and a cache.
RESET
Abbreviation of System Reset. The electronic signal which causes the target system
other than the TAP controller to be reset. This signal is also known as "nSRST"
"nSYSRST", "nRST", or "nRESET" in some other manuals. See also nTRST.
nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP
controller to be reset. This signal is known as nICERST in some other manuals. See
also nSRST.
Open collector
A signal that may be actively driven LOW by one or more drivers, and is otherwise
passively pulled HIGH. Also known as a "wired AND" signal.
Processor Core
The part of a microprocessor that reads instructions from memory and executes
them, including the instruction fetch unit, arithmetic and logic unit, and the register
bank. It excludes optional coprocessors, caches, and the memory management unit.
RTCK
Returned TCK. The signal which enables Adaptive Clocking.
Scan Chain
A group of one or more registers from one or more TAP controllers connected
between TDI and TDO, through which test data is shifted.
TAP Controller
Logic on a device which allows access to some or all of that device for test purposes.
The circuit functionality is defined in IEEE1149.1.
Target
The actual processor (real silicon or simulated) on which the application program is
running.
TCK
The electronic clock signal which times data on the TAP data lines TMS, TDI, and
TDO.
TDI
The electronic signal input to a TAP controller from the data source (upstream). Usu-
ally, this is seen connecting the J-Link / J-Trace Interface Unit to the first TAP control-
ler.
TDO
The electronic signal output from a TAP controller to the data sink (downstream).
Usually, this is seen connecting the last TAP controller to the J-Link / J-Trace Inter-
face Unit.
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Chapter 7
This chapter lists documents, which we think may be useful to gain deeper under-
standing of technical details.
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Index
A N
Adaptive clocking .................................70 nTRST ............................................... 71
Application Program Interface ................70
O
B Open collector .................................... 71
Big-endian ..........................................70
P
D Processor Core ................................... 71
Device Under Test ................................70
DUT ...................................................70 R
RESET ............................................... 71
E RTCK ................................................. 71
EmbeddedICE .....................................70
EMU_CMD_HW_JTAG_GET_RESULT ........53 S
EMU_CMD_HW_JTAG_WRITE .................52
Scan Chain ......................................... 71
Support ............................................. 69
H Syntax, conventions used ....................... 5
Halfword .............................................70
Host ...................................................70 T
TAP Controller .................................... 71
I Target ............................................... 71
ICache ...............................................70 TCK ................................................... 71
ICE Extension Unit ...............................70 TDI ................................................... 71
ID .....................................................70 TDO .................................................. 71
IEEE 1149.1 ........................................70 Test Access Port (TAP) ......................... 72
In-Circuit Emulator ..............................70 Transistor-transistor logic (TTL) ............. 72
Instruction Register ..............................70
IR ......................................................70 W
Watchpoint ......................................... 72
J Word ................................................. 72
Joint Test Action Group (JTAG) ...............70
L
Little-endian .......................................71
M
Memory coherency ...............................71
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RM08001 Reference manual for J-Link USB Protocol © 2009 SEGGER Microcontroller GmbH & Co. KG