Lab 2 - Introduction To Logic Gates
Lab 2 - Introduction To Logic Gates
Objective(s):
• To describe and verify the operation of AND, OR, NOT, NAND, NOR, XOR, and XNOR gates.
• To practice how to simulate a simple digital circuit using a software package
Outcome(s):
Logic gates are the simplest component of any logic circuit. In order to understand the computer
logic, you should understand and master the logic operators (i.e., gates). A gate is a digital
electronic circuit having only one output, but one or more inputs. The output that appears at the
output of the gate depends on the input combinations.
There are many types of logic gates; such as AND, OR, and NOT, which are usually called the
three basic gates. Other popular gates are NAND and NOR gates; which are simply combinations
of an AND or an OR gate followed by a NOT gate. Other gates include the XOR “Exclusive-OR”
and the XNOR "Exclusive NOR" gates. In this experiment, we will investigate the above
mentioned basic logic gates and study their operations according to their truth table, as prescribed
during lectures.
4. From the File menu, click on save or simply click ctrl + s or command + s (for macbook users)
5. The save window will show up. Browse to the folder, where you want to save your files, write
Lab2_Last Name_FN (ex. Lab2_Juan_Jomer) on the file name, then click save.
6. Now, you are ready to verify the operation of all basic logic. Gates. Let’s start with the NAND gate.
7. From the explorer pane, expand the gates folder by clicking on the + sign beside it.
8. Select the NAND gate and place it into the canvas. Notice that the attribute table of the NAND
gate would show up.
9. Practice changing one of the attributes of the NAND gate. Change the number of inputs from 5 to
2.
10. From the toolbar, select the input tool and add two inputs on the canvas to the left of the NAND
gate. Similarly, add an output to the right of the NAND gate using the output tool. In the attribute
table, give labels to your inputs and output as X, Y, and Z respectively.
11. If required, you could move your component through the canvas using the edit tool. Any
component could be deleted by selecting it using the edit tool then click on the delete key.
12. From the toolbar, select the edit tool to wire your circuit. click on the input X and keep pressing
while moving to the upper input of the NAND gate. Notice that when the mouse cursor is over a
point the receives a wire, a small green circle will be drawn around it. Logisim allows only
horizontal and vertical wires.
13. Now, let’s verify the operation of the NAND gate by constructing its truth table. Currently, the
two inputs, X and Y, are 0s (or colored in dark green), whereas the output Z is 1 (or colored in light
green). This constitutes the first row of the 2-inpur NAND gate truth table.
14. To try other input combinations, select the poke tool, from the toolbar, and click on the input you
want to toggle. Try all input combinations and fill in the following truth table.
Sample truth table for 2-input logic gate
X Y Z
0 0
0 1
1 0
1 1
15. Repeat the previous steps to verify the operation of all other basic logic gates: NOR, NOT, AND,
OR, XOR, and XNOR. Fill in the following truth tables for each gate.
16. Take a screenshot of the canvas where all the logic gates are present. This will be attached in the
lab report under the data and results.
17. Insert the truth tables for each logic gate in the lab report also under the data and results. Make
sure to properly label each truth table.
Instructions: The answers from this part will be attached in the “answers to questions” part of the
laboratory report.
1. Consider the logic circuit shown below. Use the Logisim to simulate it. Verify the circuit operation
and fill in its truth table. Include snapshots from your simulation into your report.
A B C F
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Format of Laboratory Report
Laboratory Reports will be submitted in pdf format. Filename should follow this format:
Last Name, FN_Lab#.pdf (e.g. Juan, Jomer_Lab2.pdf)
Answers to Questions:
Conclusion(s):