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4 Bit Adder M.P. Join AICTE

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Vivek Sharma
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72 views

4 Bit Adder M.P. Join AICTE

Uploaded by

Vivek Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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4-bit adder

INDEX

Sr.No Point Name

Introducton

Components/References/objective
Procedure

Pin Connection iagram

Full-Ad

bit adder Page 3


4-bit adder

Introduction

The topic of the course project is to design a 4-bit adder in the standard 0.25 um CMOS Technology.
of the project I5 to minimize the total delay of the adder (l.e. the delay or
he main
oDjectives worst
case

the circuit), the area used to implement the adder, and its average power consumption. Ihat in mind,
the team was able to spit the project into 2 phases: the research phase and the simulation phase. In the
research phase, the team had to compare different adder architectures clearly defining the advantages
and disadvantages of each one in terms of area and delay to be able to choose what could be the most
efficient adder arch itecture for the design of a 4-bit adder. Another essential task in the research phase
was to decide on the gate level implementation of the circuit, compare the different logic
for each gate, and
families impementations finally decide on
the proper logic family Implementation for
each gate in light of the project objectives stated beforehand. Once the research phase was
accomplished, the team had to move on to the simulation phase. In the simulation phase, the team had
to design each gate separately and optimize it to achieve the optimum delay and
powerconsumption, thensimulate a 1-bit full adder, and finally simulate the whole 4-blt adder. The
simulation phase concludes the project by estimating the worst case delay of the 4-bit adder design and
the average power consumption of the circuit.

4-bit adder Page 4


4-bit adder

objective

TO investigate the logical properties ofgthe exclusive-OR funcion. investigate


hoir id
E
oO
properues.
ere cucuOT's
Dy
m e a n s or
exausve OR gates and to

Referencess

Donald P.Leach: Experimental in Digital Principles, 3rdEdition Malvino/Leach: Digital Principles and
Applications Bartee: Digital Computer Fundamentals, 6thEditon

components

1-74LS04 hex-inverter (NOT)TL IC1-74S08 QUuad-two input ANDTTL IC 1-74532 Quad-two input OR
TTL IC 1-74S86 exclusive OR (EX-OR) TTL IC 1-DC Voltmeter 1- +5V Power supply

4-blt addeer Page 5


4-bit adder

Procedure

1) Connect the circuit in fig 2-1.Using 0=0V dc and 1= +5V dc, erify that the cirauit will
by
perfom the exclusive-oR function 2) 2-
completing the truth table. Connect the dirauit in frig
2.Using 0=OV dc and1+5V de, veriy that the dirauit will pertorm the excusive-OR function
by completng the truth table. 3) Connect the half-adder circuit in fig 2-3b.Using 0= 0V dc and
1+5V dc construct a truth table for this drcuit by applying the Inputs A and B as shown In
table 3 and record the resulting sum and carry Output measured.
4) Use the exdluslve-OR gates to construct the full-adder in Fig 2-4a. Construct ts truth table
using the same procedure as in stepl. For each Input, record the sum and carry output of each
half- adder as well as the OR-gate outpur.

4-bit adder Page 6


4-bit adder

Pin Connection Diagram

4-blt adder Page 7


4-bit adder

Full-Adder

A full-adder Is a logic drcuit having 3 inputs A,B and C ( whidh Is the cary fram the previous
stage) and 2 outputs (Sum and CamyY, whikch will perform according to table 3. The ful-adder
can handlke three binary digits ata ime and can therefore be used to add binary numbers in
general.
The simplest way to construct a full adder is to connect two half- adder and an OR gate as
shown in Hg 2-4. The fullkadder is then the fundamental logic dircuit incorporated in digital
computers to perform aithmetic functions.

(A 6B) A

A EB)

Co-AB t (AEB) C

4-bit adder Page B


4-bit adder

A EARA -(A B)OC

(A®BC

AB
Co AB+ (A DB) C1

SUm

Iagut
Bts

Cary
Cary CI Co

-bit adder Page 9

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